2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
24 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
25 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
26 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
27 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
28 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
29 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38
30 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
31 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
32 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
34 /* macro for wrapper status */
35 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
36 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
37 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
38 #define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
39 #define PWRAP_STATE_INIT_DONE0 (1 << 21)
41 /* macro for WACS FSM */
42 #define PWRAP_WACS_FSM_IDLE 0x00
43 #define PWRAP_WACS_FSM_REQ 0x02
44 #define PWRAP_WACS_FSM_WFDLE 0x04
45 #define PWRAP_WACS_FSM_WFVLDCLR 0x06
46 #define PWRAP_WACS_INIT_DONE 0x01
47 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01
48 #define PWRAP_WACS_SYNC_BUSY 0x00
50 /* macro for device wrapper default value */
51 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5
52 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
54 /* macro for manual command */
55 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
56 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
57 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
58 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
59 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
60 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
61 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
63 /* macro for slave device wrapper registers */
64 #define PWRAP_DEW_BASE 0xbc00
65 #define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
66 #define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
67 #define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
68 #define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
69 #define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
70 #define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
71 #define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
72 #define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
73 #define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
74 #define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
75 #define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
76 #define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
77 #define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
78 #define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
79 #define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
80 #define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
81 #define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
82 #define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
83 #define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
84 #define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
85 #define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
86 #define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
87 #define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
88 #define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
89 #define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
102 PWRAP_STAUPD_MAN_TRIG,
144 PWRAP_CIPHER_KEY_SEL,
152 /* MT8135 only regs */
165 /* MT8173 only regs */
188 static int mt8173_regs[] = {
189 [PWRAP_MUX_SEL] = 0x0,
190 [PWRAP_WRAP_EN] = 0x4,
191 [PWRAP_DIO_EN] = 0x8,
193 [PWRAP_RDDMY] = 0x10,
194 [PWRAP_SI_CK_CON] = 0x14,
195 [PWRAP_CSHEXT_WRITE] = 0x18,
196 [PWRAP_CSHEXT_READ] = 0x1c,
197 [PWRAP_CSLEXT_START] = 0x20,
198 [PWRAP_CSLEXT_END] = 0x24,
199 [PWRAP_STAUPD_PRD] = 0x28,
200 [PWRAP_STAUPD_GRPEN] = 0x2c,
201 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
202 [PWRAP_STAUPD_STA] = 0x44,
203 [PWRAP_WRAP_STA] = 0x48,
204 [PWRAP_HARB_INIT] = 0x4c,
205 [PWRAP_HARB_HPRIO] = 0x50,
206 [PWRAP_HIPRIO_ARB_EN] = 0x54,
207 [PWRAP_HARB_STA0] = 0x58,
208 [PWRAP_HARB_STA1] = 0x5c,
209 [PWRAP_MAN_EN] = 0x60,
210 [PWRAP_MAN_CMD] = 0x64,
211 [PWRAP_MAN_RDATA] = 0x68,
212 [PWRAP_MAN_VLDCLR] = 0x6c,
213 [PWRAP_WACS0_EN] = 0x70,
214 [PWRAP_INIT_DONE0] = 0x74,
215 [PWRAP_WACS0_CMD] = 0x78,
216 [PWRAP_WACS0_RDATA] = 0x7c,
217 [PWRAP_WACS0_VLDCLR] = 0x80,
218 [PWRAP_WACS1_EN] = 0x84,
219 [PWRAP_INIT_DONE1] = 0x88,
220 [PWRAP_WACS1_CMD] = 0x8c,
221 [PWRAP_WACS1_RDATA] = 0x90,
222 [PWRAP_WACS1_VLDCLR] = 0x94,
223 [PWRAP_WACS2_EN] = 0x98,
224 [PWRAP_INIT_DONE2] = 0x9c,
225 [PWRAP_WACS2_CMD] = 0xa0,
226 [PWRAP_WACS2_RDATA] = 0xa4,
227 [PWRAP_WACS2_VLDCLR] = 0xa8,
228 [PWRAP_INT_EN] = 0xac,
229 [PWRAP_INT_FLG_RAW] = 0xb0,
230 [PWRAP_INT_FLG] = 0xb4,
231 [PWRAP_INT_CLR] = 0xb8,
232 [PWRAP_SIG_ADR] = 0xbc,
233 [PWRAP_SIG_MODE] = 0xc0,
234 [PWRAP_SIG_VALUE] = 0xc4,
235 [PWRAP_SIG_ERRVAL] = 0xc8,
236 [PWRAP_CRC_EN] = 0xcc,
237 [PWRAP_TIMER_EN] = 0xd0,
238 [PWRAP_TIMER_STA] = 0xd4,
239 [PWRAP_WDT_UNIT] = 0xd8,
240 [PWRAP_WDT_SRC_EN] = 0xdc,
241 [PWRAP_WDT_FLG] = 0xe0,
242 [PWRAP_DEBUG_INT_SEL] = 0xe4,
243 [PWRAP_DVFS_ADR0] = 0xe8,
244 [PWRAP_DVFS_WDATA0] = 0xec,
245 [PWRAP_DVFS_ADR1] = 0xf0,
246 [PWRAP_DVFS_WDATA1] = 0xf4,
247 [PWRAP_DVFS_ADR2] = 0xf8,
248 [PWRAP_DVFS_WDATA2] = 0xfc,
249 [PWRAP_DVFS_ADR3] = 0x100,
250 [PWRAP_DVFS_WDATA3] = 0x104,
251 [PWRAP_DVFS_ADR4] = 0x108,
252 [PWRAP_DVFS_WDATA4] = 0x10c,
253 [PWRAP_DVFS_ADR5] = 0x110,
254 [PWRAP_DVFS_WDATA5] = 0x114,
255 [PWRAP_DVFS_ADR6] = 0x118,
256 [PWRAP_DVFS_WDATA6] = 0x11c,
257 [PWRAP_DVFS_ADR7] = 0x120,
258 [PWRAP_DVFS_WDATA7] = 0x124,
259 [PWRAP_SPMINF_STA] = 0x128,
260 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
261 [PWRAP_CIPHER_IV_SEL] = 0x130,
262 [PWRAP_CIPHER_EN] = 0x134,
263 [PWRAP_CIPHER_RDY] = 0x138,
264 [PWRAP_CIPHER_MODE] = 0x13c,
265 [PWRAP_CIPHER_SWRST] = 0x140,
266 [PWRAP_DCM_EN] = 0x144,
267 [PWRAP_DCM_DBC_PRD] = 0x148,
270 static int mt8135_regs[] = {
271 [PWRAP_MUX_SEL] = 0x0,
272 [PWRAP_WRAP_EN] = 0x4,
273 [PWRAP_DIO_EN] = 0x8,
275 [PWRAP_CSHEXT] = 0x10,
276 [PWRAP_CSHEXT_WRITE] = 0x14,
277 [PWRAP_CSHEXT_READ] = 0x18,
278 [PWRAP_CSLEXT_START] = 0x1c,
279 [PWRAP_CSLEXT_END] = 0x20,
280 [PWRAP_STAUPD_PRD] = 0x24,
281 [PWRAP_STAUPD_GRPEN] = 0x28,
282 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
283 [PWRAP_STAUPD_STA] = 0x30,
284 [PWRAP_EVENT_IN_EN] = 0x34,
285 [PWRAP_EVENT_DST_EN] = 0x38,
286 [PWRAP_WRAP_STA] = 0x3c,
287 [PWRAP_RRARB_INIT] = 0x40,
288 [PWRAP_RRARB_EN] = 0x44,
289 [PWRAP_RRARB_STA0] = 0x48,
290 [PWRAP_RRARB_STA1] = 0x4c,
291 [PWRAP_HARB_INIT] = 0x50,
292 [PWRAP_HARB_HPRIO] = 0x54,
293 [PWRAP_HIPRIO_ARB_EN] = 0x58,
294 [PWRAP_HARB_STA0] = 0x5c,
295 [PWRAP_HARB_STA1] = 0x60,
296 [PWRAP_MAN_EN] = 0x64,
297 [PWRAP_MAN_CMD] = 0x68,
298 [PWRAP_MAN_RDATA] = 0x6c,
299 [PWRAP_MAN_VLDCLR] = 0x70,
300 [PWRAP_WACS0_EN] = 0x74,
301 [PWRAP_INIT_DONE0] = 0x78,
302 [PWRAP_WACS0_CMD] = 0x7c,
303 [PWRAP_WACS0_RDATA] = 0x80,
304 [PWRAP_WACS0_VLDCLR] = 0x84,
305 [PWRAP_WACS1_EN] = 0x88,
306 [PWRAP_INIT_DONE1] = 0x8c,
307 [PWRAP_WACS1_CMD] = 0x90,
308 [PWRAP_WACS1_RDATA] = 0x94,
309 [PWRAP_WACS1_VLDCLR] = 0x98,
310 [PWRAP_WACS2_EN] = 0x9c,
311 [PWRAP_INIT_DONE2] = 0xa0,
312 [PWRAP_WACS2_CMD] = 0xa4,
313 [PWRAP_WACS2_RDATA] = 0xa8,
314 [PWRAP_WACS2_VLDCLR] = 0xac,
315 [PWRAP_INT_EN] = 0xb0,
316 [PWRAP_INT_FLG_RAW] = 0xb4,
317 [PWRAP_INT_FLG] = 0xb8,
318 [PWRAP_INT_CLR] = 0xbc,
319 [PWRAP_SIG_ADR] = 0xc0,
320 [PWRAP_SIG_MODE] = 0xc4,
321 [PWRAP_SIG_VALUE] = 0xc8,
322 [PWRAP_SIG_ERRVAL] = 0xcc,
323 [PWRAP_CRC_EN] = 0xd0,
324 [PWRAP_EVENT_STA] = 0xd4,
325 [PWRAP_EVENT_STACLR] = 0xd8,
326 [PWRAP_TIMER_EN] = 0xdc,
327 [PWRAP_TIMER_STA] = 0xe0,
328 [PWRAP_WDT_UNIT] = 0xe4,
329 [PWRAP_WDT_SRC_EN] = 0xe8,
330 [PWRAP_WDT_FLG] = 0xec,
331 [PWRAP_DEBUG_INT_SEL] = 0xf0,
332 [PWRAP_CIPHER_KEY_SEL] = 0x134,
333 [PWRAP_CIPHER_IV_SEL] = 0x138,
334 [PWRAP_CIPHER_LOAD] = 0x13c,
335 [PWRAP_CIPHER_START] = 0x140,
336 [PWRAP_CIPHER_RDY] = 0x144,
337 [PWRAP_CIPHER_MODE] = 0x148,
338 [PWRAP_CIPHER_SWRST] = 0x14c,
339 [PWRAP_DCM_EN] = 0x15c,
340 [PWRAP_DCM_DBC_PRD] = 0x160,
348 struct pmic_wrapper_type {
350 enum pwrap_type type;
354 static struct pmic_wrapper_type pwrap_mt8135 = {
356 .type = PWRAP_MT8135,
360 static struct pmic_wrapper_type pwrap_mt8173 = {
362 .type = PWRAP_MT8173,
366 struct pmic_wrapper {
369 struct regmap *regmap;
371 enum pwrap_type type;
374 struct clk *clk_wrap;
375 struct reset_control *rstc;
377 struct reset_control *rstc_bridge;
378 void __iomem *bridge_base;
381 static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
383 return wrp->type == PWRAP_MT8135;
386 static inline int pwrap_is_mt8173(struct pmic_wrapper *wrp)
388 return wrp->type == PWRAP_MT8173;
391 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
393 return readl(wrp->base + wrp->regs[reg]);
396 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
398 writel(val, wrp->base + wrp->regs[reg]);
401 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
403 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
405 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
408 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
410 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
412 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
415 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
417 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
420 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
422 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
424 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
425 (val & PWRAP_STATE_SYNC_IDLE0);
428 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
429 bool (*fp)(struct pmic_wrapper *))
431 unsigned long timeout;
433 timeout = jiffies + usecs_to_jiffies(255);
436 if (time_after(jiffies, timeout))
437 return fp(wrp) ? 0 : -ETIMEDOUT;
443 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
447 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
451 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
457 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
461 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
465 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
467 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
471 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
473 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
478 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
480 return pwrap_read(context, adr, rdata);
483 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
485 return pwrap_write(context, adr, wdata);
488 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
492 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
493 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
494 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
495 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
496 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
498 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSL,
500 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
502 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSH,
505 for (i = 0; i < 4; i++)
506 pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
509 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
511 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
515 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
516 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
522 * pwrap_init_sidly - configure serial input delay
524 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
525 * delay. Do a read test with all possible values and chose the best delay.
527 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
532 signed char dly[16] = {
533 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
536 for (i = 0; i < 4; i++) {
537 pwrap_writel(wrp, i, PWRAP_SIDLY);
538 pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
539 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
540 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
546 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
551 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
556 static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
558 if (pwrap_is_mt8135(wrp)) {
559 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
560 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
561 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
562 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
563 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
565 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
566 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
567 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
568 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
574 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
576 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
579 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
584 ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
591 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
596 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
597 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
598 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
599 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
601 if (pwrap_is_mt8135(wrp)) {
602 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
603 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
605 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
608 /* Config cipher mode @PMIC */
609 pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
610 pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
611 pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
612 pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
613 pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
614 pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
616 /* wait for cipher data ready@AP */
617 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
619 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
623 /* wait for cipher data ready@PMIC */
624 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
626 dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
630 /* wait for cipher mode idle */
631 pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
632 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
634 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
638 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
641 if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
642 pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
643 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
644 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
651 static int pwrap_init(struct pmic_wrapper *wrp)
656 reset_control_reset(wrp->rstc);
657 if (wrp->rstc_bridge)
658 reset_control_reset(wrp->rstc_bridge);
660 if (pwrap_is_mt8173(wrp)) {
662 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
663 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
666 /* Reset SPI slave */
667 ret = pwrap_reset_spislave(wrp);
671 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
673 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
675 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
677 ret = pwrap_init_reg_clock(wrp);
681 /* Setup serial input delay */
682 ret = pwrap_init_sidly(wrp);
686 /* Enable dual IO mode */
687 pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
689 /* Check IDLE & INIT_DONE in advance */
690 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
692 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
696 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
699 pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
700 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
701 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
702 PWRAP_DEW_READ_TEST_VAL, rdata);
706 /* Enable encryption */
707 ret = pwrap_init_cipher(wrp);
711 /* Signature checking - using CRC */
712 if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
715 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
716 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
717 pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
718 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
720 if (pwrap_is_mt8135(wrp))
721 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
723 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
724 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
725 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
726 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
727 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
728 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
729 pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);
730 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
731 pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
733 if (pwrap_is_mt8135(wrp)) {
734 /* enable pwrap events and pwrap bridge in AP side */
735 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
736 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
737 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
738 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
739 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
740 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
741 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
742 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
743 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
745 /* enable PMIC event out and sources */
746 if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
747 pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
748 dev_err(wrp->dev, "enable dewrap fail\n");
752 /* PMIC_DEWRAP enables */
753 if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
754 pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
755 dev_err(wrp->dev, "enable dewrap fail\n");
760 /* Setup the init done registers */
761 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
762 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
763 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
765 if (pwrap_is_mt8135(wrp)) {
766 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
767 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
773 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
776 struct pmic_wrapper *wrp = dev_id;
778 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
780 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
782 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
787 static const struct regmap_config pwrap_regmap_config = {
791 .reg_read = pwrap_regmap_read,
792 .reg_write = pwrap_regmap_write,
793 .max_register = 0xffff,
796 static struct of_device_id of_pwrap_match_tbl[] = {
798 .compatible = "mediatek,mt8135-pwrap",
799 .data = &pwrap_mt8135,
801 .compatible = "mediatek,mt8173-pwrap",
802 .data = &pwrap_mt8173,
807 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
809 static int pwrap_probe(struct platform_device *pdev)
812 struct pmic_wrapper *wrp;
813 struct device_node *np = pdev->dev.of_node;
814 const struct of_device_id *of_id =
815 of_match_device(of_pwrap_match_tbl, &pdev->dev);
816 const struct pmic_wrapper_type *type;
817 struct resource *res;
819 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
823 platform_set_drvdata(pdev, wrp);
826 wrp->regs = type->regs;
827 wrp->type = type->type;
828 wrp->arb_en_all = type->arb_en_all;
829 wrp->dev = &pdev->dev;
831 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
832 wrp->base = devm_ioremap_resource(wrp->dev, res);
833 if (IS_ERR(wrp->base))
834 return PTR_ERR(wrp->base);
836 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
837 if (IS_ERR(wrp->rstc)) {
838 ret = PTR_ERR(wrp->rstc);
839 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
843 if (pwrap_is_mt8135(wrp)) {
844 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
846 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
847 if (IS_ERR(wrp->bridge_base))
848 return PTR_ERR(wrp->bridge_base);
850 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
851 if (IS_ERR(wrp->rstc_bridge)) {
852 ret = PTR_ERR(wrp->rstc_bridge);
853 dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
858 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
859 if (IS_ERR(wrp->clk_spi)) {
860 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
861 return PTR_ERR(wrp->clk_spi);
864 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
865 if (IS_ERR(wrp->clk_wrap)) {
866 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
867 return PTR_ERR(wrp->clk_wrap);
870 ret = clk_prepare_enable(wrp->clk_spi);
874 ret = clk_prepare_enable(wrp->clk_wrap);
878 /* Enable internal dynamic clock */
879 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
880 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
883 * The PMIC could already be initialized by the bootloader.
884 * Skip initialization here in this case.
886 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
887 ret = pwrap_init(wrp);
889 dev_dbg(wrp->dev, "init failed with %d\n", ret);
894 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
895 dev_dbg(wrp->dev, "initialization isn't finished\n");
899 irq = platform_get_irq(pdev, 0);
900 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
901 "mt-pmic-pwrap", wrp);
905 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
906 if (IS_ERR(wrp->regmap))
907 return PTR_ERR(wrp->regmap);
909 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
911 dev_dbg(wrp->dev, "failed to create child devices at %s\n",
919 clk_disable_unprepare(wrp->clk_wrap);
921 clk_disable_unprepare(wrp->clk_spi);
926 static struct platform_driver pwrap_drv = {
928 .name = "mt-pmic-pwrap",
929 .owner = THIS_MODULE,
930 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
932 .probe = pwrap_probe,
935 module_platform_driver(pwrap_drv);
937 MODULE_AUTHOR("Flora Fu, MediaTek");
938 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
939 MODULE_LICENSE("GPL v2");