drivers/soc/rockchip/pm_domains.c

   1 /*
   2  * Rockchip Generic power domain support.
   3  *
   4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <linux/pm_clock.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/clk.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <dt-bindings/power/rk3288-power.h>
  21 #include <dt-bindings/power/rk3366-power.h>
  22 #include <dt-bindings/power/rk3368-power.h>
  23 #include <dt-bindings/power/rk3399-power.h>
  24
  25 struct rockchip_domain_info {
  26         int pwr_mask;
  27         int status_mask;
  28         int req_mask;
  29         int idle_mask;
  30         int ack_mask;
  31 };
  32
  33 struct rockchip_pmu_info {
  34         u32 pwr_offset;
  35         u32 status_offset;
  36         u32 req_offset;
  37         u32 idle_offset;
  38         u32 ack_offset;
  39
  40         u32 core_pwrcnt_offset;
  41         u32 gpu_pwrcnt_offset;
  42
  43         unsigned int core_power_transition_time;
  44         unsigned int gpu_power_transition_time;
  45
  46         int num_domains;
  47         const struct rockchip_domain_info *domain_info;
  48 };
  49
  50 #define MAX_QOS_REGS_NUM        5
  51 #define QOS_PRIORITY            0x08
  52 #define QOS_MODE                0x0c
  53 #define QOS_BANDWIDTH           0x10
  54 #define QOS_SATURATION          0x14
  55 #define QOS_EXTCONTROL          0x18
  56
  57 struct rockchip_pm_domain {
  58         struct generic_pm_domain genpd;
  59         const struct rockchip_domain_info *info;
  60         struct rockchip_pmu *pmu;
  61         int num_qos;
  62         struct regmap **qos_regmap;
  63         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  64         int num_clks;
  65         struct clk *clks[];
  66 };
  67
  68 struct rockchip_pmu {
  69         struct device *dev;
  70         struct regmap *regmap;
  71         const struct rockchip_pmu_info *info;
  72         struct mutex mutex; /* mutex lock for pmu */
  73         struct genpd_onecell_data genpd_data;
  74         struct generic_pm_domain *domains[];
  75 };
  76
  77 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  78
  79 #define DOMAIN(pwr, status, req, idle, ack)     \
  80 {                                               \
  81         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  82         .status_mask = (status >= 0) ? BIT(status) : 0, \
  83         .req_mask = (req >= 0) ? BIT(req) : 0,          \
  84         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
  85         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
  86 }
  87
  88 #define DOMAIN_RK3288(pwr, status, req)         \
  89         DOMAIN(pwr, status, req, req, (req) + 16)
  90
  91 #define DOMAIN_RK3368(pwr, status, req)         \
  92         DOMAIN(pwr, status, req, (req) + 16, req)
  93
  94 #define DOMAIN_RK3399(pwr, status, req)                \
  95         DOMAIN(pwr, status, req, req, req)
  96
  97 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
  98 {
  99         struct rockchip_pmu *pmu = pd->pmu;
 100         const struct rockchip_domain_info *pd_info = pd->info;
 101         unsigned int val;
 102
 103         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
 104         return (val & pd_info->idle_mask) == pd_info->idle_mask;
 105 }
 106
 107 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 108                                          bool idle)
 109 {
 110         const struct rockchip_domain_info *pd_info = pd->info;
 111         struct rockchip_pmu *pmu = pd->pmu;
 112         unsigned int val;
 113
 114         if (pd_info->req_mask == 0)
 115                 return 0;
 116
 117         regmap_update_bits(pmu->regmap, pmu->info->req_offset,
 118                            pd_info->req_mask, idle ? -1U : 0);
 119
 120         dsb(sy);
 121
 122         do {
 123                 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 124         } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
 125
 126         while (rockchip_pmu_domain_is_idle(pd) != idle)
 127                 cpu_relax();
 128
 129         return 0;
 130 }
 131
 132 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
 133 {
 134         int i;
 135
 136         for (i = 0; i < pd->num_qos; i++) {
 137                 regmap_read(pd->qos_regmap[i],
 138                             QOS_PRIORITY,
 139                             &pd->qos_save_regs[0][i]);
 140                 regmap_read(pd->qos_regmap[i],
 141                             QOS_MODE,
 142                             &pd->qos_save_regs[1][i]);
 143                 regmap_read(pd->qos_regmap[i],
 144                             QOS_BANDWIDTH,
 145                             &pd->qos_save_regs[2][i]);
 146                 regmap_read(pd->qos_regmap[i],
 147                             QOS_SATURATION,
 148                             &pd->qos_save_regs[3][i]);
 149                 regmap_read(pd->qos_regmap[i],
 150                             QOS_EXTCONTROL,
 151                             &pd->qos_save_regs[4][i]);
 152         }
 153         return 0;
 154 }
 155
 156 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
 157 {
 158         int i;
 159
 160         for (i = 0; i < pd->num_qos; i++) {
 161                 regmap_write(pd->qos_regmap[i],
 162                              QOS_PRIORITY,
 163                              pd->qos_save_regs[0][i]);
 164                 regmap_write(pd->qos_regmap[i],
 165                              QOS_MODE,
 166                              pd->qos_save_regs[1][i]);
 167                 regmap_write(pd->qos_regmap[i],
 168                              QOS_BANDWIDTH,
 169                              pd->qos_save_regs[2][i]);
 170                 regmap_write(pd->qos_regmap[i],
 171                              QOS_SATURATION,
 172                              pd->qos_save_regs[3][i]);
 173                 regmap_write(pd->qos_regmap[i],
 174                              QOS_EXTCONTROL,
 175                              pd->qos_save_regs[4][i]);
 176         }
 177
 178         return 0;
 179 }
 180
 181 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 182 {
 183         struct rockchip_pmu *pmu = pd->pmu;
 184         unsigned int val;
 185
 186         /* check idle status for idle-only domains */
 187         if (pd->info->status_mask == 0)
 188                 return !rockchip_pmu_domain_is_idle(pd);
 189
 190         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 191
 192         /* 1'b0: power on, 1'b1: power off */
 193         return !(val & pd->info->status_mask);
 194 }
 195
 196 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 197                                              bool on)
 198 {
 199         struct rockchip_pmu *pmu = pd->pmu;
 200
 201         if (pd->info->pwr_mask == 0)
 202                 return;
 203
 204         regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
 205                            pd->info->pwr_mask, on ? 0 : -1U);
 206
 207         dsb(sy);
 208
 209         while (rockchip_pmu_domain_is_on(pd) != on)
 210                 cpu_relax();
 211 }
 212
 213 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 214 {
 215         int i;
 216
 217         mutex_lock(&pd->pmu->mutex);
 218
 219         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 220                 for (i = 0; i < pd->num_clks; i++)
 221                         clk_enable(pd->clks[i]);
 222
 223                 if (!power_on) {
 224                         rockchip_pmu_save_qos(pd);
 225
 226                         /* if powering down, idle request to NIU first */
 227                         rockchip_pmu_set_idle_request(pd, true);
 228                 }
 229
 230                 rockchip_do_pmu_set_power_domain(pd, power_on);
 231
 232                 if (power_on) {
 233                         /* if powering up, leave idle mode */
 234                         rockchip_pmu_set_idle_request(pd, false);
 235
 236                         rockchip_pmu_restore_qos(pd);
 237                 }
 238
 239                 for (i = pd->num_clks - 1; i >= 0; i--)
 240                         clk_disable(pd->clks[i]);
 241         }
 242
 243         mutex_unlock(&pd->pmu->mutex);
 244         return 0;
 245 }
 246
 247 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 248 {
 249         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 250
 251         return rockchip_pd_power(pd, true);
 252 }
 253
 254 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 255 {
 256         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 257
 258         return rockchip_pd_power(pd, false);
 259 }
 260
 261 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 262                                   struct device *dev)
 263 {
 264         struct clk *clk;
 265         int i;
 266         int error;
 267
 268         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 269
 270         error = pm_clk_create(dev);
 271         if (error) {
 272                 dev_err(dev, "pm_clk_create failed %d\n", error);
 273                 return error;
 274         }
 275
 276         i = 0;
 277         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 278                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 279                 error = pm_clk_add_clk(dev, clk);
 280                 if (error) {
 281                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 282                         clk_put(clk);
 283                         pm_clk_destroy(dev);
 284                         return error;
 285                 }
 286         }
 287
 288         return 0;
 289 }
 290
 291 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 292                                    struct device *dev)
 293 {
 294         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 295
 296         pm_clk_destroy(dev);
 297 }
 298
 299 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 300                                       struct device_node *node)
 301 {
 302         const struct rockchip_domain_info *pd_info;
 303         struct rockchip_pm_domain *pd;
 304         struct device_node *qos_node;
 305         struct clk *clk;
 306         int clk_cnt;
 307         int i, j;
 308         u32 id;
 309         int error;
 310
 311         error = of_property_read_u32(node, "reg", &id);
 312         if (error) {
 313                 dev_err(pmu->dev,
 314                         "%s: failed to retrieve domain id (reg): %d\n",
 315                         node->name, error);
 316                 return -EINVAL;
 317         }
 318
 319         if (id >= pmu->info->num_domains) {
 320                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
 321                         node->name, id);
 322                 return -EINVAL;
 323         }
 324
 325         pd_info = &pmu->info->domain_info[id];
 326         if (!pd_info) {
 327                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
 328                         node->name, id);
 329                 return -EINVAL;
 330         }
 331
 332         clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 333         pd = devm_kzalloc(pmu->dev,
 334                           sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
 335                           GFP_KERNEL);
 336         if (!pd)
 337                 return -ENOMEM;
 338
 339         pd->info = pd_info;
 340         pd->pmu = pmu;
 341
 342         for (i = 0; i < clk_cnt; i++) {
 343                 clk = of_clk_get(node, i);
 344                 if (IS_ERR(clk)) {
 345                         error = PTR_ERR(clk);
 346                         dev_err(pmu->dev,
 347                                 "%s: failed to get clk at index %d: %d\n",
 348                                 node->name, i, error);
 349                         goto err_out;
 350                 }
 351
 352                 error = clk_prepare(clk);
 353                 if (error) {
 354                         dev_err(pmu->dev,
 355                                 "%s: failed to prepare clk %pC (index %d): %d\n",
 356                                 node->name, clk, i, error);
 357                         clk_put(clk);
 358                         goto err_out;
 359                 }
 360
 361                 pd->clks[pd->num_clks++] = clk;
 362
 363                 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
 364                         clk, node->name);
 365         }
 366
 367         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
 368                                                  NULL);
 369
 370         if (pd->num_qos > 0) {
 371                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
 372                                               sizeof(*pd->qos_regmap),
 373                                               GFP_KERNEL);
 374                 if (!pd->qos_regmap) {
 375                         error = -ENOMEM;
 376                         goto err_out;
 377                 }
 378
 379                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
 380                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
 381                                                             pd->num_qos,
 382                                                             sizeof(u32),
 383                                                             GFP_KERNEL);
 384                         if (!pd->qos_save_regs[j]) {
 385                                 error = -ENOMEM;
 386                                 goto err_out;
 387                         }
 388                 }
 389
 390                 for (j = 0; j < pd->num_qos; j++) {
 391                         qos_node = of_parse_phandle(node, "pm_qos", j);
 392                         if (!qos_node) {
 393                                 error = -ENODEV;
 394                                 goto err_out;
 395                         }
 396                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
 397                         if (IS_ERR(pd->qos_regmap[j])) {
 398                                 error = -ENODEV;
 399                                 of_node_put(qos_node);
 400                                 goto err_out;
 401                         }
 402                         of_node_put(qos_node);
 403                 }
 404         }
 405
 406         error = rockchip_pd_power(pd, true);
 407         if (error) {
 408                 dev_err(pmu->dev,
 409                         "failed to power on domain '%s': %d\n",
 410                         node->name, error);
 411                 goto err_out;
 412         }
 413
 414         pd->genpd.name = node->name;
 415         pd->genpd.power_off = rockchip_pd_power_off;
 416         pd->genpd.power_on = rockchip_pd_power_on;
 417         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 418         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 419         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 420         pm_genpd_init(&pd->genpd, NULL, false);
 421
 422         pmu->genpd_data.domains[id] = &pd->genpd;
 423         return 0;
 424
 425 err_out:
 426         while (--i >= 0) {
 427                 clk_unprepare(pd->clks[i]);
 428                 clk_put(pd->clks[i]);
 429         }
 430         return error;
 431 }
 432
 433 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 434 {
 435         int i;
 436
 437         for (i = 0; i < pd->num_clks; i++) {
 438                 clk_unprepare(pd->clks[i]);
 439                 clk_put(pd->clks[i]);
 440         }
 441
 442         /* protect the zeroing of pm->num_clks */
 443         mutex_lock(&pd->pmu->mutex);
 444         pd->num_clks = 0;
 445         mutex_unlock(&pd->pmu->mutex);
 446
 447         /* devm will free our memory */
 448 }
 449
 450 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 451 {
 452         struct generic_pm_domain *genpd;
 453         struct rockchip_pm_domain *pd;
 454         int i;
 455
 456         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 457                 genpd = pmu->genpd_data.domains[i];
 458                 if (genpd) {
 459                         pd = to_rockchip_pd(genpd);
 460                         rockchip_pm_remove_one_domain(pd);
 461                 }
 462         }
 463
 464         /* devm will free our memory */
 465 }
 466
 467 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 468                                       u32 domain_reg_offset,
 469                                       unsigned int count)
 470 {
 471         /* First configure domain power down transition count ... */
 472         regmap_write(pmu->regmap, domain_reg_offset, count);
 473         /* ... and then power up count. */
 474         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 475 }
 476
 477 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 478                                      struct device_node *parent)
 479 {
 480         struct device_node *np;
 481         struct generic_pm_domain *child_domain, *parent_domain;
 482         int error;
 483
 484         for_each_child_of_node(parent, np) {
 485                 u32 idx;
 486
 487                 error = of_property_read_u32(parent, "reg", &idx);
 488                 if (error) {
 489                         dev_err(pmu->dev,
 490                                 "%s: failed to retrieve domain id (reg): %d\n",
 491                                 parent->name, error);
 492                         goto err_out;
 493                 }
 494                 parent_domain = pmu->genpd_data.domains[idx];
 495
 496                 error = rockchip_pm_add_one_domain(pmu, np);
 497                 if (error) {
 498                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
 499                                 np->name, error);
 500                         goto err_out;
 501                 }
 502
 503                 error = of_property_read_u32(np, "reg", &idx);
 504                 if (error) {
 505                         dev_err(pmu->dev,
 506                                 "%s: failed to retrieve domain id (reg): %d\n",
 507                                 np->name, error);
 508                         goto err_out;
 509                 }
 510                 child_domain = pmu->genpd_data.domains[idx];
 511
 512                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 513                 if (error) {
 514                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 515                                 parent_domain->name, child_domain->name, error);
 516                         goto err_out;
 517                 } else {
 518                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 519                                 parent_domain->name, child_domain->name);
 520                 }
 521
 522                 rockchip_pm_add_subdomain(pmu, np);
 523         }
 524
 525         return 0;
 526
 527 err_out:
 528         of_node_put(np);
 529         return error;
 530 }
 531
 532 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 533 {
 534         struct device *dev = &pdev->dev;
 535         struct device_node *np = dev->of_node;
 536         struct device_node *node;
 537         struct device *parent;
 538         struct rockchip_pmu *pmu;
 539         const struct of_device_id *match;
 540         const struct rockchip_pmu_info *pmu_info;
 541         int error;
 542
 543         if (!np) {
 544                 dev_err(dev, "device tree node not found\n");
 545                 return -ENODEV;
 546         }
 547
 548         match = of_match_device(dev->driver->of_match_table, dev);
 549         if (!match || !match->data) {
 550                 dev_err(dev, "missing pmu data\n");
 551                 return -EINVAL;
 552         }
 553
 554         pmu_info = match->data;
 555
 556         pmu = devm_kzalloc(dev,
 557                            sizeof(*pmu) +
 558                                 pmu_info->num_domains * sizeof(pmu->domains[0]),
 559                            GFP_KERNEL);
 560         if (!pmu)
 561                 return -ENOMEM;
 562
 563         pmu->dev = &pdev->dev;
 564         mutex_init(&pmu->mutex);
 565
 566         pmu->info = pmu_info;
 567
 568         pmu->genpd_data.domains = pmu->domains;
 569         pmu->genpd_data.num_domains = pmu_info->num_domains;
 570
 571         parent = dev->parent;
 572         if (!parent) {
 573                 dev_err(dev, "no parent for syscon devices\n");
 574                 return -ENODEV;
 575         }
 576
 577         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 578         if (IS_ERR(pmu->regmap)) {
 579                 dev_err(dev, "no regmap available\n");
 580                 return PTR_ERR(pmu->regmap);
 581         }
 582
 583         /*
 584          * Configure power up and down transition delays for CORE
 585          * and GPU domains.
 586          */
 587         rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 588                                   pmu_info->core_power_transition_time);
 589         rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 590                                   pmu_info->gpu_power_transition_time);
 591
 592         error = -ENODEV;
 593
 594         for_each_available_child_of_node(np, node) {
 595                 error = rockchip_pm_add_one_domain(pmu, node);
 596                 if (error) {
 597                         dev_err(dev, "failed to handle node %s: %d\n",
 598                                 node->name, error);
 599                         of_node_put(node);
 600                         goto err_out;
 601                 }
 602
 603                 error = rockchip_pm_add_subdomain(pmu, node);
 604                 if (error < 0) {
 605                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
 606                                 node->name, error);
 607                         of_node_put(node);
 608                         goto err_out;
 609                 }
 610         }
 611
 612         if (error) {
 613                 dev_dbg(dev, "no power domains defined\n");
 614                 goto err_out;
 615         }
 616
 617         of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 618
 619         return 0;
 620
 621 err_out:
 622         rockchip_pm_domain_cleanup(pmu);
 623         return error;
 624 }
 625
 626 static const struct rockchip_domain_info rk3288_pm_domains[] = {
 627         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4),
 628         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9),
 629         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3),
 630         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2),
 631 };
 632
 633 static const struct rockchip_domain_info rk3366_pm_domains[] = {
 634         [RK3366_PD_PERI]        = DOMAIN_RK3368(10, 10, 6),
 635         [RK3366_PD_VIO]         = DOMAIN_RK3368(14, 14, 8),
 636         [RK3366_PD_VIDEO]       = DOMAIN_RK3368(13, 13, 7),
 637         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368(11, 11, 7),
 638         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368(8, 8, 9),
 639         [RK3366_PD_VPU]         = DOMAIN_RK3368(12, 12, 7),
 640         [RK3366_PD_GPU]         = DOMAIN_RK3368(15, 15, 2),
 641 };
 642
 643 static const struct rockchip_domain_info rk3368_pm_domains[] = {
 644         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6),
 645         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8),
 646         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7),
 647         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2),
 648         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2),
 649 };
 650
 651 static const struct rockchip_domain_info rk3399_pm_domains[] = {
 652         [RK3399_PD_TCPD0]       = DOMAIN_RK3399(8, 8, -1),
 653         [RK3399_PD_TCPD1]       = DOMAIN_RK3399(9, 9, -1),
 654         [RK3399_PD_CCI]         = DOMAIN_RK3399(10, 10, -1),
 655         [RK3399_PD_CCI0]        = DOMAIN_RK3399(-1, -1, 15),
 656         [RK3399_PD_CCI1]        = DOMAIN_RK3399(-1, -1, 16),
 657         [RK3399_PD_PERILP]      = DOMAIN_RK3399(11, 11, 1),
 658         [RK3399_PD_PERIHP]      = DOMAIN_RK3399(12, 12, 2),
 659         [RK3399_PD_CENTER]      = DOMAIN_RK3399(13, 13, 14),
 660         [RK3399_PD_VIO]         = DOMAIN_RK3399(14, 14, 17),
 661         [RK3399_PD_GPU]         = DOMAIN_RK3399(15, 15, 0),
 662         [RK3399_PD_VCODEC]      = DOMAIN_RK3399(16, 16, 3),
 663         [RK3399_PD_VDU]         = DOMAIN_RK3399(17, 17, 4),
 664         [RK3399_PD_RGA]         = DOMAIN_RK3399(18, 18, 5),
 665         [RK3399_PD_IEP]         = DOMAIN_RK3399(19, 19, 6),
 666         [RK3399_PD_VO]          = DOMAIN_RK3399(20, 20, -1),
 667         [RK3399_PD_VOPB]        = DOMAIN_RK3399(-1, -1, 7),
 668         [RK3399_PD_VOPL]        = DOMAIN_RK3399(-1, -1, 8),
 669         [RK3399_PD_ISP0]        = DOMAIN_RK3399(22, 22, 9),
 670         [RK3399_PD_ISP1]        = DOMAIN_RK3399(23, 23, 10),
 671         [RK3399_PD_HDCP]        = DOMAIN_RK3399(24, 24, 11),
 672         [RK3399_PD_GMAC]        = DOMAIN_RK3399(25, 25, 23),
 673         [RK3399_PD_EMMC]        = DOMAIN_RK3399(26, 26, 24),
 674         [RK3399_PD_USB3]        = DOMAIN_RK3399(27, 27, 12),
 675         [RK3399_PD_EDP]         = DOMAIN_RK3399(28, 28, 22),
 676         [RK3399_PD_GIC]         = DOMAIN_RK3399(29, 29, 27),
 677         [RK3399_PD_SD]          = DOMAIN_RK3399(30, 30, 28),
 678         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399(31, 31, 29),
 679 };
 680
 681 static const struct rockchip_pmu_info rk3288_pmu = {
 682         .pwr_offset = 0x08,
 683         .status_offset = 0x0c,
 684         .req_offset = 0x10,
 685         .idle_offset = 0x14,
 686         .ack_offset = 0x14,
 687
 688         .core_pwrcnt_offset = 0x34,
 689         .gpu_pwrcnt_offset = 0x3c,
 690
 691         .core_power_transition_time = 24, /* 1us */
 692         .gpu_power_transition_time = 24, /* 1us */
 693
 694         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
 695         .domain_info = rk3288_pm_domains,
 696 };
 697
 698 static const struct rockchip_pmu_info rk3366_pmu = {
 699         .pwr_offset = 0x0c,
 700         .status_offset = 0x10,
 701         .req_offset = 0x3c,
 702         .idle_offset = 0x40,
 703         .ack_offset = 0x40,
 704
 705         .core_pwrcnt_offset = 0x48,
 706         .gpu_pwrcnt_offset = 0x50,
 707
 708         .core_power_transition_time = 24,
 709         .gpu_power_transition_time = 24,
 710
 711         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
 712         .domain_info = rk3366_pm_domains,
 713 };
 714
 715 static const struct rockchip_pmu_info rk3368_pmu = {
 716         .pwr_offset = 0x0c,
 717         .status_offset = 0x10,
 718         .req_offset = 0x3c,
 719         .idle_offset = 0x40,
 720         .ack_offset = 0x40,
 721
 722         .core_pwrcnt_offset = 0x48,
 723         .gpu_pwrcnt_offset = 0x50,
 724
 725         .core_power_transition_time = 24,
 726         .gpu_power_transition_time = 24,
 727
 728         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
 729         .domain_info = rk3368_pm_domains,
 730 };
 731
 732 static const struct rockchip_pmu_info rk3399_pmu = {
 733         .pwr_offset = 0x14,
 734         .status_offset = 0x18,
 735         .req_offset = 0x60,
 736         .idle_offset = 0x64,
 737         .ack_offset = 0x68,
 738
 739         .core_pwrcnt_offset = 0xac,
 740         .gpu_pwrcnt_offset = 0xac,
 741
 742         .core_power_transition_time = 6, /* 0.25us */
 743         .gpu_power_transition_time = 6, /* 0.25us */
 744
 745         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
 746         .domain_info = rk3399_pm_domains,
 747 };
 748
 749 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 750         {
 751                 .compatible = "rockchip,rk3288-power-controller",
 752                 .data = (void *)&rk3288_pmu,
 753         },
 754         {
 755                 .compatible = "rockchip,rk3366-power-controller",
 756                 .data = (void *)&rk3366_pmu,
 757         },
 758         {
 759                 .compatible = "rockchip,rk3368-power-controller",
 760                 .data = (void *)&rk3368_pmu,
 761         },
 762         {
 763                 .compatible = "rockchip,rk3399-power-controller",
 764                 .data = (void *)&rk3399_pmu,
 765         },
 766         { /* sentinel */ },
 767 };
 768
 769 static struct platform_driver rockchip_pm_domain_driver = {
 770         .probe = rockchip_pm_domain_probe,
 771         .driver = {
 772                 .name   = "rockchip-pm-domain",
 773                 .of_match_table = rockchip_pm_domain_dt_match,
 774                 /*
 775                  * We can't forcibly eject devices form power domain,
 776                  * so we can't really remove power domains once they
 777                  * were added.
 778                  */
 779                 .suppress_bind_attrs = true,
 780         },
 781 };
 782
 783 static int __init rockchip_pm_domain_drv_register(void)
 784 {
 785         return platform_driver_register(&rockchip_pm_domain_driver);
 786 }
 787 postcore_initcall(rockchip_pm_domain_drv_register);