drivers/soc/rockchip/pm_domains.c

   1 /*
   2  * Rockchip Generic power domain support.
   3  *
   4  * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/err.h>
  13 #include <linux/pm_clock.h>
  14 #include <linux/pm_domain.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/clk.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <dt-bindings/power/rk3288-power.h>
  21 #include <dt-bindings/power/rk3366-power.h>
  22 #include <dt-bindings/power/rk3368-power.h>
  23 #include <dt-bindings/power/rk3399-power.h>
  24
  25 struct rockchip_domain_info {
  26         int pwr_mask;
  27         int status_mask;
  28         int req_mask;
  29         int idle_mask;
  30         int ack_mask;
  31         bool active_wakeup;
  32 };
  33
  34 struct rockchip_pmu_info {
  35         u32 pwr_offset;
  36         u32 status_offset;
  37         u32 req_offset;
  38         u32 idle_offset;
  39         u32 ack_offset;
  40
  41         u32 core_pwrcnt_offset;
  42         u32 gpu_pwrcnt_offset;
  43
  44         unsigned int core_power_transition_time;
  45         unsigned int gpu_power_transition_time;
  46
  47         int num_domains;
  48         const struct rockchip_domain_info *domain_info;
  49 };
  50
  51 #define MAX_QOS_REGS_NUM        5
  52 #define QOS_PRIORITY            0x08
  53 #define QOS_MODE                0x0c
  54 #define QOS_BANDWIDTH           0x10
  55 #define QOS_SATURATION          0x14
  56 #define QOS_EXTCONTROL          0x18
  57
  58 struct rockchip_pm_domain {
  59         struct generic_pm_domain genpd;
  60         const struct rockchip_domain_info *info;
  61         struct rockchip_pmu *pmu;
  62         int num_qos;
  63         struct regmap **qos_regmap;
  64         u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  65         int num_clks;
  66         struct clk *clks[];
  67 };
  68
  69 struct rockchip_pmu {
  70         struct device *dev;
  71         struct regmap *regmap;
  72         const struct rockchip_pmu_info *info;
  73         struct mutex mutex; /* mutex lock for pmu */
  74         struct genpd_onecell_data genpd_data;
  75         struct generic_pm_domain *domains[];
  76 };
  77
  78 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  79
  80 #define DOMAIN(pwr, status, req, idle, ack, wakeup)     \
  81 {                                               \
  82         .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0,          \
  83         .status_mask = (status >= 0) ? BIT(status) : 0, \
  84         .req_mask = (req >= 0) ? BIT(req) : 0,          \
  85         .idle_mask = (idle >= 0) ? BIT(idle) : 0,       \
  86         .ack_mask = (ack >= 0) ? BIT(ack) : 0,          \
  87         .active_wakeup = wakeup,                        \
  88 }
  89
  90 #define DOMAIN_RK3288(pwr, status, req, wakeup)         \
  91         DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
  92
  93 #define DOMAIN_RK3368(pwr, status, req, wakeup)         \
  94         DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
  95
  96 #define DOMAIN_RK3399(pwr, status, req, wakeup)         \
  97         DOMAIN(pwr, status, req, req, req, wakeup)
  98
  99 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
 100 {
 101         struct rockchip_pmu *pmu = pd->pmu;
 102         const struct rockchip_domain_info *pd_info = pd->info;
 103         unsigned int val;
 104
 105         regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
 106         return (val & pd_info->idle_mask) == pd_info->idle_mask;
 107 }
 108
 109 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
 110                                          bool idle)
 111 {
 112         const struct rockchip_domain_info *pd_info = pd->info;
 113         struct rockchip_pmu *pmu = pd->pmu;
 114         unsigned int val;
 115
 116         if (pd_info->req_mask == 0)
 117                 return 0;
 118
 119         regmap_update_bits(pmu->regmap, pmu->info->req_offset,
 120                            pd_info->req_mask, idle ? -1U : 0);
 121
 122         dsb(sy);
 123
 124         do {
 125                 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
 126         } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
 127
 128         while (rockchip_pmu_domain_is_idle(pd) != idle)
 129                 cpu_relax();
 130
 131         return 0;
 132 }
 133
 134 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
 135 {
 136         int i;
 137
 138         for (i = 0; i < pd->num_qos; i++) {
 139                 regmap_read(pd->qos_regmap[i],
 140                             QOS_PRIORITY,
 141                             &pd->qos_save_regs[0][i]);
 142                 regmap_read(pd->qos_regmap[i],
 143                             QOS_MODE,
 144                             &pd->qos_save_regs[1][i]);
 145                 regmap_read(pd->qos_regmap[i],
 146                             QOS_BANDWIDTH,
 147                             &pd->qos_save_regs[2][i]);
 148                 regmap_read(pd->qos_regmap[i],
 149                             QOS_SATURATION,
 150                             &pd->qos_save_regs[3][i]);
 151                 regmap_read(pd->qos_regmap[i],
 152                             QOS_EXTCONTROL,
 153                             &pd->qos_save_regs[4][i]);
 154         }
 155         return 0;
 156 }
 157
 158 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
 159 {
 160         int i;
 161
 162         for (i = 0; i < pd->num_qos; i++) {
 163                 regmap_write(pd->qos_regmap[i],
 164                              QOS_PRIORITY,
 165                              pd->qos_save_regs[0][i]);
 166                 regmap_write(pd->qos_regmap[i],
 167                              QOS_MODE,
 168                              pd->qos_save_regs[1][i]);
 169                 regmap_write(pd->qos_regmap[i],
 170                              QOS_BANDWIDTH,
 171                              pd->qos_save_regs[2][i]);
 172                 regmap_write(pd->qos_regmap[i],
 173                              QOS_SATURATION,
 174                              pd->qos_save_regs[3][i]);
 175                 regmap_write(pd->qos_regmap[i],
 176                              QOS_EXTCONTROL,
 177                              pd->qos_save_regs[4][i]);
 178         }
 179
 180         return 0;
 181 }
 182
 183 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
 184 {
 185         struct rockchip_pmu *pmu = pd->pmu;
 186         unsigned int val;
 187
 188         /* check idle status for idle-only domains */
 189         if (pd->info->status_mask == 0)
 190                 return !rockchip_pmu_domain_is_idle(pd);
 191
 192         regmap_read(pmu->regmap, pmu->info->status_offset, &val);
 193
 194         /* 1'b0: power on, 1'b1: power off */
 195         return !(val & pd->info->status_mask);
 196 }
 197
 198 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
 199                                              bool on)
 200 {
 201         struct rockchip_pmu *pmu = pd->pmu;
 202
 203         if (pd->info->pwr_mask == 0)
 204                 return;
 205
 206         regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
 207                            pd->info->pwr_mask, on ? 0 : -1U);
 208
 209         dsb(sy);
 210
 211         while (rockchip_pmu_domain_is_on(pd) != on)
 212                 cpu_relax();
 213 }
 214
 215 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
 216 {
 217         int i;
 218
 219         mutex_lock(&pd->pmu->mutex);
 220
 221         if (rockchip_pmu_domain_is_on(pd) != power_on) {
 222                 for (i = 0; i < pd->num_clks; i++)
 223                         clk_enable(pd->clks[i]);
 224
 225                 if (!power_on) {
 226                         rockchip_pmu_save_qos(pd);
 227
 228                         /* if powering down, idle request to NIU first */
 229                         rockchip_pmu_set_idle_request(pd, true);
 230                 }
 231
 232                 rockchip_do_pmu_set_power_domain(pd, power_on);
 233
 234                 if (power_on) {
 235                         /* if powering up, leave idle mode */
 236                         rockchip_pmu_set_idle_request(pd, false);
 237
 238                         rockchip_pmu_restore_qos(pd);
 239                 }
 240
 241                 for (i = pd->num_clks - 1; i >= 0; i--)
 242                         clk_disable(pd->clks[i]);
 243         }
 244
 245         mutex_unlock(&pd->pmu->mutex);
 246         return 0;
 247 }
 248
 249 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
 250 {
 251         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 252
 253         return rockchip_pd_power(pd, true);
 254 }
 255
 256 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
 257 {
 258         struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
 259
 260         return rockchip_pd_power(pd, false);
 261 }
 262
 263 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
 264                                   struct device *dev)
 265 {
 266         struct clk *clk;
 267         int i;
 268         int error;
 269
 270         dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
 271
 272         error = pm_clk_create(dev);
 273         if (error) {
 274                 dev_err(dev, "pm_clk_create failed %d\n", error);
 275                 return error;
 276         }
 277
 278         i = 0;
 279         while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
 280                 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
 281                 error = pm_clk_add_clk(dev, clk);
 282                 if (error) {
 283                         dev_err(dev, "pm_clk_add_clk failed %d\n", error);
 284                         clk_put(clk);
 285                         pm_clk_destroy(dev);
 286                         return error;
 287                 }
 288         }
 289
 290         return 0;
 291 }
 292
 293 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
 294                                    struct device *dev)
 295 {
 296         dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
 297
 298         pm_clk_destroy(dev);
 299 }
 300
 301 static bool rockchip_active_wakeup(struct device *dev)
 302 {
 303         struct generic_pm_domain *genpd;
 304         struct rockchip_pm_domain *pd;
 305
 306         genpd = pd_to_genpd(dev->pm_domain);
 307         pd = container_of(genpd, struct rockchip_pm_domain, genpd);
 308
 309         return pd->info->active_wakeup;
 310 }
 311
 312 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
 313                                       struct device_node *node)
 314 {
 315         const struct rockchip_domain_info *pd_info;
 316         struct rockchip_pm_domain *pd;
 317         struct device_node *qos_node;
 318         struct clk *clk;
 319         int clk_cnt;
 320         int i, j;
 321         u32 id;
 322         int error;
 323
 324         error = of_property_read_u32(node, "reg", &id);
 325         if (error) {
 326                 dev_err(pmu->dev,
 327                         "%s: failed to retrieve domain id (reg): %d\n",
 328                         node->name, error);
 329                 return -EINVAL;
 330         }
 331
 332         if (id >= pmu->info->num_domains) {
 333                 dev_err(pmu->dev, "%s: invalid domain id %d\n",
 334                         node->name, id);
 335                 return -EINVAL;
 336         }
 337
 338         pd_info = &pmu->info->domain_info[id];
 339         if (!pd_info) {
 340                 dev_err(pmu->dev, "%s: undefined domain id %d\n",
 341                         node->name, id);
 342                 return -EINVAL;
 343         }
 344
 345         clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
 346         pd = devm_kzalloc(pmu->dev,
 347                           sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
 348                           GFP_KERNEL);
 349         if (!pd)
 350                 return -ENOMEM;
 351
 352         pd->info = pd_info;
 353         pd->pmu = pmu;
 354
 355         for (i = 0; i < clk_cnt; i++) {
 356                 clk = of_clk_get(node, i);
 357                 if (IS_ERR(clk)) {
 358                         error = PTR_ERR(clk);
 359                         dev_err(pmu->dev,
 360                                 "%s: failed to get clk at index %d: %d\n",
 361                                 node->name, i, error);
 362                         goto err_out;
 363                 }
 364
 365                 error = clk_prepare(clk);
 366                 if (error) {
 367                         dev_err(pmu->dev,
 368                                 "%s: failed to prepare clk %pC (index %d): %d\n",
 369                                 node->name, clk, i, error);
 370                         clk_put(clk);
 371                         goto err_out;
 372                 }
 373
 374                 pd->clks[pd->num_clks++] = clk;
 375
 376                 dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
 377                         clk, node->name);
 378         }
 379
 380         pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
 381                                                  NULL);
 382
 383         if (pd->num_qos > 0) {
 384                 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
 385                                               sizeof(*pd->qos_regmap),
 386                                               GFP_KERNEL);
 387                 if (!pd->qos_regmap) {
 388                         error = -ENOMEM;
 389                         goto err_out;
 390                 }
 391
 392                 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
 393                         pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
 394                                                             pd->num_qos,
 395                                                             sizeof(u32),
 396                                                             GFP_KERNEL);
 397                         if (!pd->qos_save_regs[j]) {
 398                                 error = -ENOMEM;
 399                                 goto err_out;
 400                         }
 401                 }
 402
 403                 for (j = 0; j < pd->num_qos; j++) {
 404                         qos_node = of_parse_phandle(node, "pm_qos", j);
 405                         if (!qos_node) {
 406                                 error = -ENODEV;
 407                                 goto err_out;
 408                         }
 409                         pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
 410                         if (IS_ERR(pd->qos_regmap[j])) {
 411                                 error = -ENODEV;
 412                                 of_node_put(qos_node);
 413                                 goto err_out;
 414                         }
 415                         of_node_put(qos_node);
 416                 }
 417         }
 418
 419         error = rockchip_pd_power(pd, true);
 420         if (error) {
 421                 dev_err(pmu->dev,
 422                         "failed to power on domain '%s': %d\n",
 423                         node->name, error);
 424                 goto err_out;
 425         }
 426
 427         pd->genpd.name = node->name;
 428         pd->genpd.power_off = rockchip_pd_power_off;
 429         pd->genpd.power_on = rockchip_pd_power_on;
 430         pd->genpd.attach_dev = rockchip_pd_attach_dev;
 431         pd->genpd.detach_dev = rockchip_pd_detach_dev;
 432         pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
 433         pd->genpd.flags = GENPD_FLAG_PM_CLK;
 434         pm_genpd_init(&pd->genpd, NULL, false);
 435
 436         pmu->genpd_data.domains[id] = &pd->genpd;
 437         return 0;
 438
 439 err_out:
 440         while (--i >= 0) {
 441                 clk_unprepare(pd->clks[i]);
 442                 clk_put(pd->clks[i]);
 443         }
 444         return error;
 445 }
 446
 447 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
 448 {
 449         int i;
 450
 451         for (i = 0; i < pd->num_clks; i++) {
 452                 clk_unprepare(pd->clks[i]);
 453                 clk_put(pd->clks[i]);
 454         }
 455
 456         /* protect the zeroing of pm->num_clks */
 457         mutex_lock(&pd->pmu->mutex);
 458         pd->num_clks = 0;
 459         mutex_unlock(&pd->pmu->mutex);
 460
 461         /* devm will free our memory */
 462 }
 463
 464 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
 465 {
 466         struct generic_pm_domain *genpd;
 467         struct rockchip_pm_domain *pd;
 468         int i;
 469
 470         for (i = 0; i < pmu->genpd_data.num_domains; i++) {
 471                 genpd = pmu->genpd_data.domains[i];
 472                 if (genpd) {
 473                         pd = to_rockchip_pd(genpd);
 474                         rockchip_pm_remove_one_domain(pd);
 475                 }
 476         }
 477
 478         /* devm will free our memory */
 479 }
 480
 481 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
 482                                       u32 domain_reg_offset,
 483                                       unsigned int count)
 484 {
 485         /* First configure domain power down transition count ... */
 486         regmap_write(pmu->regmap, domain_reg_offset, count);
 487         /* ... and then power up count. */
 488         regmap_write(pmu->regmap, domain_reg_offset + 4, count);
 489 }
 490
 491 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
 492                                      struct device_node *parent)
 493 {
 494         struct device_node *np;
 495         struct generic_pm_domain *child_domain, *parent_domain;
 496         int error;
 497
 498         for_each_child_of_node(parent, np) {
 499                 u32 idx;
 500
 501                 error = of_property_read_u32(parent, "reg", &idx);
 502                 if (error) {
 503                         dev_err(pmu->dev,
 504                                 "%s: failed to retrieve domain id (reg): %d\n",
 505                                 parent->name, error);
 506                         goto err_out;
 507                 }
 508                 parent_domain = pmu->genpd_data.domains[idx];
 509
 510                 error = rockchip_pm_add_one_domain(pmu, np);
 511                 if (error) {
 512                         dev_err(pmu->dev, "failed to handle node %s: %d\n",
 513                                 np->name, error);
 514                         goto err_out;
 515                 }
 516
 517                 error = of_property_read_u32(np, "reg", &idx);
 518                 if (error) {
 519                         dev_err(pmu->dev,
 520                                 "%s: failed to retrieve domain id (reg): %d\n",
 521                                 np->name, error);
 522                         goto err_out;
 523                 }
 524                 child_domain = pmu->genpd_data.domains[idx];
 525
 526                 error = pm_genpd_add_subdomain(parent_domain, child_domain);
 527                 if (error) {
 528                         dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
 529                                 parent_domain->name, child_domain->name, error);
 530                         goto err_out;
 531                 } else {
 532                         dev_dbg(pmu->dev, "%s add subdomain: %s\n",
 533                                 parent_domain->name, child_domain->name);
 534                 }
 535
 536                 rockchip_pm_add_subdomain(pmu, np);
 537         }
 538
 539         return 0;
 540
 541 err_out:
 542         of_node_put(np);
 543         return error;
 544 }
 545
 546 static int rockchip_pm_domain_probe(struct platform_device *pdev)
 547 {
 548         struct device *dev = &pdev->dev;
 549         struct device_node *np = dev->of_node;
 550         struct device_node *node;
 551         struct device *parent;
 552         struct rockchip_pmu *pmu;
 553         const struct of_device_id *match;
 554         const struct rockchip_pmu_info *pmu_info;
 555         int error;
 556
 557         if (!np) {
 558                 dev_err(dev, "device tree node not found\n");
 559                 return -ENODEV;
 560         }
 561
 562         match = of_match_device(dev->driver->of_match_table, dev);
 563         if (!match || !match->data) {
 564                 dev_err(dev, "missing pmu data\n");
 565                 return -EINVAL;
 566         }
 567
 568         pmu_info = match->data;
 569
 570         pmu = devm_kzalloc(dev,
 571                            sizeof(*pmu) +
 572                                 pmu_info->num_domains * sizeof(pmu->domains[0]),
 573                            GFP_KERNEL);
 574         if (!pmu)
 575                 return -ENOMEM;
 576
 577         pmu->dev = &pdev->dev;
 578         mutex_init(&pmu->mutex);
 579
 580         pmu->info = pmu_info;
 581
 582         pmu->genpd_data.domains = pmu->domains;
 583         pmu->genpd_data.num_domains = pmu_info->num_domains;
 584
 585         parent = dev->parent;
 586         if (!parent) {
 587                 dev_err(dev, "no parent for syscon devices\n");
 588                 return -ENODEV;
 589         }
 590
 591         pmu->regmap = syscon_node_to_regmap(parent->of_node);
 592         if (IS_ERR(pmu->regmap)) {
 593                 dev_err(dev, "no regmap available\n");
 594                 return PTR_ERR(pmu->regmap);
 595         }
 596
 597         /*
 598          * Configure power up and down transition delays for CORE
 599          * and GPU domains.
 600          */
 601         rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
 602                                   pmu_info->core_power_transition_time);
 603         rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
 604                                   pmu_info->gpu_power_transition_time);
 605
 606         error = -ENODEV;
 607
 608         for_each_available_child_of_node(np, node) {
 609                 error = rockchip_pm_add_one_domain(pmu, node);
 610                 if (error) {
 611                         dev_err(dev, "failed to handle node %s: %d\n",
 612                                 node->name, error);
 613                         of_node_put(node);
 614                         goto err_out;
 615                 }
 616
 617                 error = rockchip_pm_add_subdomain(pmu, node);
 618                 if (error < 0) {
 619                         dev_err(dev, "failed to handle subdomain node %s: %d\n",
 620                                 node->name, error);
 621                         of_node_put(node);
 622                         goto err_out;
 623                 }
 624         }
 625
 626         if (error) {
 627                 dev_dbg(dev, "no power domains defined\n");
 628                 goto err_out;
 629         }
 630
 631         of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 632
 633         return 0;
 634
 635 err_out:
 636         rockchip_pm_domain_cleanup(pmu);
 637         return error;
 638 }
 639
 640 static const struct rockchip_domain_info rk3288_pm_domains[] = {
 641         [RK3288_PD_VIO]         = DOMAIN_RK3288(7, 7, 4, false),
 642         [RK3288_PD_HEVC]        = DOMAIN_RK3288(14, 10, 9, false),
 643         [RK3288_PD_VIDEO]       = DOMAIN_RK3288(8, 8, 3, false),
 644         [RK3288_PD_GPU]         = DOMAIN_RK3288(9, 9, 2, false),
 645 };
 646
 647 static const struct rockchip_domain_info rk3366_pm_domains[] = {
 648         [RK3366_PD_PERI]        = DOMAIN_RK3368(10, 10, 6, true),
 649         [RK3366_PD_VIO]         = DOMAIN_RK3368(14, 14, 8, false),
 650         [RK3366_PD_VIDEO]       = DOMAIN_RK3368(13, 13, 7, false),
 651         [RK3366_PD_RKVDEC]      = DOMAIN_RK3368(11, 11, 7, false),
 652         [RK3366_PD_WIFIBT]      = DOMAIN_RK3368(8, 8, 9, false),
 653         [RK3366_PD_VPU]         = DOMAIN_RK3368(12, 12, 7, false),
 654         [RK3366_PD_GPU]         = DOMAIN_RK3368(15, 15, 2, false),
 655 };
 656
 657 static const struct rockchip_domain_info rk3368_pm_domains[] = {
 658         [RK3368_PD_PERI]        = DOMAIN_RK3368(13, 12, 6, true),
 659         [RK3368_PD_VIO]         = DOMAIN_RK3368(15, 14, 8, false),
 660         [RK3368_PD_VIDEO]       = DOMAIN_RK3368(14, 13, 7, false),
 661         [RK3368_PD_GPU_0]       = DOMAIN_RK3368(16, 15, 2, false),
 662         [RK3368_PD_GPU_1]       = DOMAIN_RK3368(17, 16, 2, false),
 663 };
 664
 665 static const struct rockchip_domain_info rk3399_pm_domains[] = {
 666         [RK3399_PD_TCPD0]       = DOMAIN_RK3399(8, 8, -1, false),
 667         [RK3399_PD_TCPD1]       = DOMAIN_RK3399(9, 9, -1, false),
 668         [RK3399_PD_CCI]         = DOMAIN_RK3399(10, 10, -1, true),
 669         [RK3399_PD_CCI0]        = DOMAIN_RK3399(-1, -1, 15, true),
 670         [RK3399_PD_CCI1]        = DOMAIN_RK3399(-1, -1, 16, true),
 671         [RK3399_PD_PERILP]      = DOMAIN_RK3399(11, 11, 1, true),
 672         [RK3399_PD_PERIHP]      = DOMAIN_RK3399(12, 12, 2, true),
 673         [RK3399_PD_CENTER]      = DOMAIN_RK3399(13, 13, 14, true),
 674         [RK3399_PD_VIO]         = DOMAIN_RK3399(14, 14, 17, false),
 675         [RK3399_PD_GPU]         = DOMAIN_RK3399(15, 15, 0, false),
 676         [RK3399_PD_VCODEC]      = DOMAIN_RK3399(16, 16, 3, false),
 677         [RK3399_PD_VDU]         = DOMAIN_RK3399(17, 17, 4, false),
 678         [RK3399_PD_RGA]         = DOMAIN_RK3399(18, 18, 5, false),
 679         [RK3399_PD_IEP]         = DOMAIN_RK3399(19, 19, 6, false),
 680         [RK3399_PD_VO]          = DOMAIN_RK3399(20, 20, -1, false),
 681         [RK3399_PD_VOPB]        = DOMAIN_RK3399(-1, -1, 7, false),
 682         [RK3399_PD_VOPL]        = DOMAIN_RK3399(-1, -1, 8, false),
 683         [RK3399_PD_ISP0]        = DOMAIN_RK3399(22, 22, 9, false),
 684         [RK3399_PD_ISP1]        = DOMAIN_RK3399(23, 23, 10, false),
 685         [RK3399_PD_HDCP]        = DOMAIN_RK3399(24, 24, 11, false),
 686         [RK3399_PD_GMAC]        = DOMAIN_RK3399(25, 25, 23, true),
 687         [RK3399_PD_EMMC]        = DOMAIN_RK3399(26, 26, 24, true),
 688         [RK3399_PD_USB3]        = DOMAIN_RK3399(27, 27, 12, true),
 689         [RK3399_PD_EDP]         = DOMAIN_RK3399(28, 28, 22, false),
 690         [RK3399_PD_GIC]         = DOMAIN_RK3399(29, 29, 27, true),
 691         [RK3399_PD_SD]          = DOMAIN_RK3399(30, 30, 28, true),
 692         [RK3399_PD_SDIOAUDIO]   = DOMAIN_RK3399(31, 31, 29, true),
 693 };
 694
 695 static const struct rockchip_pmu_info rk3288_pmu = {
 696         .pwr_offset = 0x08,
 697         .status_offset = 0x0c,
 698         .req_offset = 0x10,
 699         .idle_offset = 0x14,
 700         .ack_offset = 0x14,
 701
 702         .core_pwrcnt_offset = 0x34,
 703         .gpu_pwrcnt_offset = 0x3c,
 704
 705         .core_power_transition_time = 24, /* 1us */
 706         .gpu_power_transition_time = 24, /* 1us */
 707
 708         .num_domains = ARRAY_SIZE(rk3288_pm_domains),
 709         .domain_info = rk3288_pm_domains,
 710 };
 711
 712 static const struct rockchip_pmu_info rk3366_pmu = {
 713         .pwr_offset = 0x0c,
 714         .status_offset = 0x10,
 715         .req_offset = 0x3c,
 716         .idle_offset = 0x40,
 717         .ack_offset = 0x40,
 718
 719         .core_pwrcnt_offset = 0x48,
 720         .gpu_pwrcnt_offset = 0x50,
 721
 722         .core_power_transition_time = 24,
 723         .gpu_power_transition_time = 24,
 724
 725         .num_domains = ARRAY_SIZE(rk3366_pm_domains),
 726         .domain_info = rk3366_pm_domains,
 727 };
 728
 729 static const struct rockchip_pmu_info rk3368_pmu = {
 730         .pwr_offset = 0x0c,
 731         .status_offset = 0x10,
 732         .req_offset = 0x3c,
 733         .idle_offset = 0x40,
 734         .ack_offset = 0x40,
 735
 736         .core_pwrcnt_offset = 0x48,
 737         .gpu_pwrcnt_offset = 0x50,
 738
 739         .core_power_transition_time = 24,
 740         .gpu_power_transition_time = 24,
 741
 742         .num_domains = ARRAY_SIZE(rk3368_pm_domains),
 743         .domain_info = rk3368_pm_domains,
 744 };
 745
 746 static const struct rockchip_pmu_info rk3399_pmu = {
 747         .pwr_offset = 0x14,
 748         .status_offset = 0x18,
 749         .req_offset = 0x60,
 750         .idle_offset = 0x64,
 751         .ack_offset = 0x68,
 752
 753         .core_pwrcnt_offset = 0xac,
 754         .gpu_pwrcnt_offset = 0xac,
 755
 756         .core_power_transition_time = 6, /* 0.25us */
 757         .gpu_power_transition_time = 6, /* 0.25us */
 758
 759         .num_domains = ARRAY_SIZE(rk3399_pm_domains),
 760         .domain_info = rk3399_pm_domains,
 761 };
 762
 763 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 764         {
 765                 .compatible = "rockchip,rk3288-power-controller",
 766                 .data = (void *)&rk3288_pmu,
 767         },
 768         {
 769                 .compatible = "rockchip,rk3366-power-controller",
 770                 .data = (void *)&rk3366_pmu,
 771         },
 772         {
 773                 .compatible = "rockchip,rk3368-power-controller",
 774                 .data = (void *)&rk3368_pmu,
 775         },
 776         {
 777                 .compatible = "rockchip,rk3399-power-controller",
 778                 .data = (void *)&rk3399_pmu,
 779         },
 780         { /* sentinel */ },
 781 };
 782
 783 static struct platform_driver rockchip_pm_domain_driver = {
 784         .probe = rockchip_pm_domain_probe,
 785         .driver = {
 786                 .name   = "rockchip-pm-domain",
 787                 .of_match_table = rockchip_pm_domain_dt_match,
 788                 /*
 789                  * We can't forcibly eject devices form power domain,
 790                  * so we can't really remove power domains once they
 791                  * were added.
 792                  */
 793                 .suppress_bind_attrs = true,
 794         },
 795 };
 796
 797 static int __init rockchip_pm_domain_drv_register(void)
 798 {
 799         return platform_driver_register(&rockchip_pm_domain_driver);
 800 }
 801 postcore_initcall(rockchip_pm_domain_drv_register);