drivers/soc/tegra/fuse/fuse-tegra.c

   1 /*
   2  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/device.h>
  20 #include <linux/kobject.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/io.h>
  26
  27 #include <soc/tegra/common.h>
  28 #include <soc/tegra/fuse.h>
  29
  30 #include "fuse.h"
  31
  32 struct tegra_sku_info tegra_sku_info;
  33 EXPORT_SYMBOL(tegra_sku_info);
  34
  35 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
  36         [TEGRA_REVISION_UNKNOWN] = "unknown",
  37         [TEGRA_REVISION_A01]     = "A01",
  38         [TEGRA_REVISION_A02]     = "A02",
  39         [TEGRA_REVISION_A03]     = "A03",
  40         [TEGRA_REVISION_A03p]    = "A03 prime",
  41         [TEGRA_REVISION_A04]     = "A04",
  42 };
  43
  44 static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
  45 {
  46         u32 val;
  47
  48         val = fuse->read(fuse, round_down(offset, 4));
  49         val >>= (offset % 4) * 8;
  50         val &= 0xff;
  51
  52         return val;
  53 }
  54
  55 static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
  56                          struct bin_attribute *attr, char *buf,
  57                          loff_t pos, size_t size)
  58 {
  59         struct device *dev = kobj_to_dev(kobj);
  60         struct tegra_fuse *fuse = dev_get_drvdata(dev);
  61         int i;
  62
  63         if (pos < 0 || pos >= attr->size)
  64                 return 0;
  65
  66         if (size > attr->size - pos)
  67                 size = attr->size - pos;
  68
  69         for (i = 0; i < size; i++)
  70                 buf[i] = fuse_readb(fuse, pos + i);
  71
  72         return i;
  73 }
  74
  75 static struct bin_attribute fuse_bin_attr = {
  76         .attr = { .name = "fuse", .mode = S_IRUGO, },
  77         .read = fuse_read,
  78 };
  79
  80 static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
  81                                    const struct tegra_fuse_info *info)
  82 {
  83         fuse_bin_attr.size = size;
  84
  85         return device_create_bin_file(dev, &fuse_bin_attr);
  86 }
  87
  88 static const struct of_device_id car_match[] __initconst = {
  89         { .compatible = "nvidia,tegra20-car", },
  90         { .compatible = "nvidia,tegra30-car", },
  91         { .compatible = "nvidia,tegra114-car", },
  92         { .compatible = "nvidia,tegra124-car", },
  93         { .compatible = "nvidia,tegra132-car", },
  94         {},
  95 };
  96
  97 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
  98         .base = NULL,
  99         .soc = NULL,
 100 };
 101
 102 static const struct of_device_id tegra_fuse_match[] = {
 103 #ifdef CONFIG_ARCH_TEGRA_132_SOC
 104         { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
 105 #endif
 106 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 107         { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
 108 #endif
 109 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 110         { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
 111 #endif
 112 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 113         { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
 114 #endif
 115 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 116         { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
 117 #endif
 118         { /* sentinel */ }
 119 };
 120
 121 static int tegra_fuse_probe(struct platform_device *pdev)
 122 {
 123         void __iomem *base = fuse->base;
 124         struct resource *res;
 125         int err;
 126
 127         /* take over the memory region from the early initialization */
 128         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 129         fuse->base = devm_ioremap_resource(&pdev->dev, res);
 130         if (IS_ERR(fuse->base))
 131                 return PTR_ERR(fuse->base);
 132
 133         fuse->clk = devm_clk_get(&pdev->dev, "fuse");
 134         if (IS_ERR(fuse->clk)) {
 135                 dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
 136                         PTR_ERR(fuse->clk));
 137                 return PTR_ERR(fuse->clk);
 138         }
 139
 140         platform_set_drvdata(pdev, fuse);
 141         fuse->dev = &pdev->dev;
 142
 143         if (fuse->soc->probe) {
 144                 err = fuse->soc->probe(fuse);
 145                 if (err < 0)
 146                         return err;
 147         }
 148
 149         if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
 150                                     fuse->soc->info))
 151                 return -ENODEV;
 152
 153         /* release the early I/O memory mapping */
 154         iounmap(base);
 155
 156         return 0;
 157 }
 158
 159 static struct platform_driver tegra_fuse_driver = {
 160         .driver = {
 161                 .name = "tegra-fuse",
 162                 .of_match_table = tegra_fuse_match,
 163                 .suppress_bind_attrs = true,
 164         },
 165         .probe = tegra_fuse_probe,
 166 };
 167 module_platform_driver(tegra_fuse_driver);
 168
 169 bool __init tegra_fuse_read_spare(unsigned int spare)
 170 {
 171         unsigned int offset = fuse->soc->info->spare + spare * 4;
 172
 173         return fuse->read_early(fuse, offset) & 1;
 174 }
 175
 176 u32 __init tegra_fuse_read_early(unsigned int offset)
 177 {
 178         return fuse->read_early(fuse, offset);
 179 }
 180
 181 int tegra_fuse_readl(unsigned long offset, u32 *value)
 182 {
 183         if (!fuse->read)
 184                 return -EPROBE_DEFER;
 185
 186         *value = fuse->read(fuse, offset);
 187
 188         return 0;
 189 }
 190 EXPORT_SYMBOL(tegra_fuse_readl);
 191
 192 static void tegra_enable_fuse_clk(void __iomem *base)
 193 {
 194         u32 reg;
 195
 196         reg = readl_relaxed(base + 0x48);
 197         reg |= 1 << 28;
 198         writel(reg, base + 0x48);
 199
 200         /*
 201          * Enable FUSE clock. This needs to be hardcoded because the clock
 202          * subsystem is not active during early boot.
 203          */
 204         reg = readl(base + 0x14);
 205         reg |= 1 << 7;
 206         writel(reg, base + 0x14);
 207 }
 208
 209 static int __init tegra_init_fuse(void)
 210 {
 211         const struct of_device_id *match;
 212         struct device_node *np;
 213         struct resource regs;
 214
 215         tegra_init_apbmisc();
 216
 217         np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
 218         if (!np) {
 219                 /*
 220                  * Fall back to legacy initialization for 32-bit ARM only. All
 221                  * 64-bit ARM device tree files for Tegra are required to have
 222                  * a FUSE node.
 223                  *
 224                  * This is for backwards-compatibility with old device trees
 225                  * that didn't contain a FUSE node.
 226                  */
 227                 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
 228                         u8 chip = tegra_get_chip_id();
 229
 230                         regs.start = 0x7000f800;
 231                         regs.end = 0x7000fbff;
 232                         regs.flags = IORESOURCE_MEM;
 233
 234                         switch (chip) {
 235 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 236                         case TEGRA20:
 237                                 fuse->soc = &tegra20_fuse_soc;
 238                                 break;
 239 #endif
 240
 241 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 242                         case TEGRA30:
 243                                 fuse->soc = &tegra30_fuse_soc;
 244                                 break;
 245 #endif
 246
 247 #ifdef CONFIG_ARCH_TEGRA_114_SOC
 248                         case TEGRA114:
 249                                 fuse->soc = &tegra114_fuse_soc;
 250                                 break;
 251 #endif
 252
 253 #ifdef CONFIG_ARCH_TEGRA_124_SOC
 254                         case TEGRA124:
 255                                 fuse->soc = &tegra124_fuse_soc;
 256                                 break;
 257 #endif
 258
 259                         default:
 260                                 pr_warn("Unsupported SoC: %02x\n", chip);
 261                                 break;
 262                         }
 263                 } else {
 264                         /*
 265                          * At this point we're not running on Tegra, so play
 266                          * nice with multi-platform kernels.
 267                          */
 268                         return 0;
 269                 }
 270         } else {
 271                 /*
 272                  * Extract information from the device tree if we've found a
 273                  * matching node.
 274                  */
 275                 if (of_address_to_resource(np, 0, &regs) < 0) {
 276                         pr_err("failed to get FUSE register\n");
 277                         return -ENXIO;
 278                 }
 279
 280                 fuse->soc = match->data;
 281         }
 282
 283         np = of_find_matching_node(NULL, car_match);
 284         if (np) {
 285                 void __iomem *base = of_iomap(np, 0);
 286                 if (base) {
 287                         tegra_enable_fuse_clk(base);
 288                         iounmap(base);
 289                 } else {
 290                         pr_err("failed to map clock registers\n");
 291                         return -ENXIO;
 292                 }
 293         }
 294
 295         fuse->base = ioremap_nocache(regs.start, resource_size(&regs));
 296         if (!fuse->base) {
 297                 pr_err("failed to map FUSE registers\n");
 298                 return -ENXIO;
 299         }
 300
 301         fuse->soc->init(fuse);
 302
 303         pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
 304                 tegra_revision_name[tegra_sku_info.revision],
 305                 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
 306                 tegra_sku_info.core_process_id);
 307         pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
 308                 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
 309
 310         return 0;
 311 }
 312 early_initcall(tegra_init_fuse);