2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/device.h>
19 #include <linux/kobject.h>
20 #include <linux/kernel.h>
21 #include <linux/platform_device.h>
23 #include <linux/of_address.h>
26 #include <soc/tegra/common.h>
27 #include <soc/tegra/fuse.h>
31 static u32 (*fuse_readl)(const unsigned int offset);
33 struct tegra_sku_info tegra_sku_info;
34 EXPORT_SYMBOL(tegra_sku_info);
36 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
37 [TEGRA_REVISION_UNKNOWN] = "unknown",
38 [TEGRA_REVISION_A01] = "A01",
39 [TEGRA_REVISION_A02] = "A02",
40 [TEGRA_REVISION_A03] = "A03",
41 [TEGRA_REVISION_A03p] = "A03 prime",
42 [TEGRA_REVISION_A04] = "A04",
45 static u8 fuse_readb(const unsigned int offset)
49 val = fuse_readl(round_down(offset, 4));
50 val >>= (offset % 4) * 8;
56 static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
57 struct bin_attribute *attr, char *buf,
58 loff_t pos, size_t size)
62 if (pos < 0 || pos >= fuse_size)
65 if (size > fuse_size - pos)
66 size = fuse_size - pos;
68 for (i = 0; i < size; i++)
69 buf[i] = fuse_readb(pos + i);
74 static struct bin_attribute fuse_bin_attr = {
75 .attr = { .name = "fuse", .mode = S_IRUGO, },
79 static const struct of_device_id car_match[] __initconst = {
80 { .compatible = "nvidia,tegra20-car", },
81 { .compatible = "nvidia,tegra30-car", },
82 { .compatible = "nvidia,tegra114-car", },
83 { .compatible = "nvidia,tegra124-car", },
84 { .compatible = "nvidia,tegra132-car", },
88 static void tegra_enable_fuse_clk(void __iomem *base)
92 reg = readl_relaxed(base + 0x48);
94 writel(reg, base + 0x48);
97 * Enable FUSE clock. This needs to be hardcoded because the clock
98 * subsystem is not active during early boot.
100 reg = readl(base + 0x14);
102 writel(reg, base + 0x14);
105 int tegra_fuse_readl(unsigned long offset, u32 *value)
108 return -EPROBE_DEFER;
110 *value = fuse_readl(offset);
114 EXPORT_SYMBOL(tegra_fuse_readl);
116 int tegra_fuse_create_sysfs(struct device *dev, int size,
117 u32 (*readl)(const unsigned int offset))
122 fuse_bin_attr.size = size;
123 fuse_bin_attr.read = fuse_read;
128 return device_create_bin_file(dev, &fuse_bin_attr);
131 static int __init tegra_init_fuse(void)
133 struct device_node *np;
134 void __iomem *car_base;
139 tegra_init_apbmisc();
141 np = of_find_matching_node(NULL, car_match);
142 car_base = of_iomap(np, 0);
144 tegra_enable_fuse_clk(car_base);
147 pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
151 if (tegra_get_chip_id() == TEGRA20)
152 tegra20_init_fuse_early();
154 tegra30_init_fuse_early();
156 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
157 tegra_revision_name[tegra_sku_info.revision],
158 tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
159 tegra_sku_info.core_process_id);
160 pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
161 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
165 early_initcall(tegra_init_fuse);