2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/kernel.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/random.h>
28 #include <soc/tegra/fuse.h>
32 #define FUSE_BEGIN 0x100
34 /* Tegra30 and later */
35 #define FUSE_VENDOR_CODE 0x100
36 #define FUSE_FAB_CODE 0x104
37 #define FUSE_LOT_CODE_0 0x108
38 #define FUSE_LOT_CODE_1 0x10c
39 #define FUSE_WAFER_ID 0x110
40 #define FUSE_X_COORDINATE 0x114
41 #define FUSE_Y_COORDINATE 0x118
43 #define FUSE_HAS_REVISION_INFO BIT(0)
45 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
46 defined(CONFIG_ARCH_TEGRA_114_SOC) || \
47 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
48 defined(CONFIG_ARCH_TEGRA_132_SOC)
49 static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
51 return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
54 static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
59 err = clk_prepare_enable(fuse->clk);
61 dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
65 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
67 clk_disable_unprepare(fuse->clk);
72 static void __init tegra30_fuse_add_randomness(void)
76 randomness[0] = tegra_sku_info.sku_id;
77 randomness[1] = tegra_read_straps();
78 randomness[2] = tegra_read_chipid();
79 randomness[3] = tegra_sku_info.cpu_process_id << 16;
80 randomness[3] |= tegra_sku_info.core_process_id;
81 randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
82 randomness[4] |= tegra_sku_info.soc_speedo_id;
83 randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
84 randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
85 randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
86 randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
87 randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
88 randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
89 randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
91 add_device_randomness(randomness, sizeof(randomness));
94 static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
96 fuse->read_early = tegra30_fuse_read_early;
97 fuse->read = tegra30_fuse_read;
99 tegra_init_revision();
100 fuse->soc->speedo_init(&tegra_sku_info);
101 tegra30_fuse_add_randomness();
105 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
106 static const struct tegra_fuse_info tegra30_fuse_info = {
107 .read = tegra30_fuse_read,
112 const struct tegra_fuse_soc tegra30_fuse_soc = {
113 .init = tegra30_fuse_init,
114 .speedo_init = tegra30_init_speedo_data,
115 .info = &tegra30_fuse_info,
119 #ifdef CONFIG_ARCH_TEGRA_114_SOC
120 static const struct tegra_fuse_info tegra114_fuse_info = {
121 .read = tegra30_fuse_read,
125 const struct tegra_fuse_soc tegra114_fuse_soc = {
126 .init = tegra30_fuse_init,
127 .speedo_init = tegra114_init_speedo_data,
128 .info = &tegra114_fuse_info,
132 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
133 static const struct tegra_fuse_info tegra124_fuse_info = {
134 .read = tegra30_fuse_read,
138 const struct tegra_fuse_soc tegra124_fuse_soc = {
139 .init = tegra30_fuse_init,
140 .speedo_init = tegra124_init_speedo_data,
141 .info = &tegra124_fuse_info,