2 * drivers/spi/amba-pl022.c
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
29 * - add timeout on polled transfers
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/device.h>
35 #include <linux/ioport.h>
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/spi/spi.h>
39 #include <linux/workqueue.h>
40 #include <linux/delay.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/amba/bus.h>
44 #include <linux/amba/pl022.h>
46 #include <linux/slab.h>
47 #include <linux/dmaengine.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/scatterlist.h>
52 * This macro is used to define some register default values.
53 * reg is masked with mask, the OR:ed with an (again masked)
54 * val shifted sb steps to the left.
56 #define SSP_WRITE_BITS(reg, val, mask, sb) \
57 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
60 * This macro is also used to define some default values.
61 * It will just shift val by sb steps to the left and mask
62 * the result with mask.
64 #define GEN_MASK_BITS(val, mask, sb) \
65 (((val)<<(sb)) & (mask))
68 #define DO_NOT_DRIVE_TX 1
70 #define DO_NOT_QUEUE_DMA 0
77 * Macros to access SSP Registers with their offsets
79 #define SSP_CR0(r) (r + 0x000)
80 #define SSP_CR1(r) (r + 0x004)
81 #define SSP_DR(r) (r + 0x008)
82 #define SSP_SR(r) (r + 0x00C)
83 #define SSP_CPSR(r) (r + 0x010)
84 #define SSP_IMSC(r) (r + 0x014)
85 #define SSP_RIS(r) (r + 0x018)
86 #define SSP_MIS(r) (r + 0x01C)
87 #define SSP_ICR(r) (r + 0x020)
88 #define SSP_DMACR(r) (r + 0x024)
89 #define SSP_ITCR(r) (r + 0x080)
90 #define SSP_ITIP(r) (r + 0x084)
91 #define SSP_ITOP(r) (r + 0x088)
92 #define SSP_TDR(r) (r + 0x08C)
94 #define SSP_PID0(r) (r + 0xFE0)
95 #define SSP_PID1(r) (r + 0xFE4)
96 #define SSP_PID2(r) (r + 0xFE8)
97 #define SSP_PID3(r) (r + 0xFEC)
99 #define SSP_CID0(r) (r + 0xFF0)
100 #define SSP_CID1(r) (r + 0xFF4)
101 #define SSP_CID2(r) (r + 0xFF8)
102 #define SSP_CID3(r) (r + 0xFFC)
105 * SSP Control Register 0 - SSP_CR0
107 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
108 #define SSP_CR0_MASK_FRF (0x3UL << 4)
109 #define SSP_CR0_MASK_SPO (0x1UL << 6)
110 #define SSP_CR0_MASK_SPH (0x1UL << 7)
111 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
114 * The ST version of this block moves som bits
115 * in SSP_CR0 and extends it to 32 bits
117 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
118 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
119 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
120 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
124 * SSP Control Register 0 - SSP_CR1
126 #define SSP_CR1_MASK_LBM (0x1UL << 0)
127 #define SSP_CR1_MASK_SSE (0x1UL << 1)
128 #define SSP_CR1_MASK_MS (0x1UL << 2)
129 #define SSP_CR1_MASK_SOD (0x1UL << 3)
132 * The ST version of this block adds some bits
135 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
136 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
137 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
138 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
139 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
140 /* This one is only in the PL023 variant */
141 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
144 * SSP Status Register - SSP_SR
146 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
147 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
148 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
149 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
150 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
153 * SSP Clock Prescale Register - SSP_CPSR
155 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
158 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
160 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
161 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
162 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
163 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
166 * SSP Raw Interrupt Status Register - SSP_RIS
168 /* Receive Overrun Raw Interrupt status */
169 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
170 /* Receive Timeout Raw Interrupt status */
171 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
172 /* Receive FIFO Raw Interrupt status */
173 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
174 /* Transmit FIFO Raw Interrupt status */
175 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
178 * SSP Masked Interrupt Status Register - SSP_MIS
180 /* Receive Overrun Masked Interrupt status */
181 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
182 /* Receive Timeout Masked Interrupt status */
183 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
184 /* Receive FIFO Masked Interrupt status */
185 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
186 /* Transmit FIFO Masked Interrupt status */
187 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
190 * SSP Interrupt Clear Register - SSP_ICR
192 /* Receive Overrun Raw Clear Interrupt bit */
193 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
194 /* Receive Timeout Clear Interrupt bit */
195 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
198 * SSP DMA Control Register - SSP_DMACR
200 /* Receive DMA Enable bit */
201 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
202 /* Transmit DMA Enable bit */
203 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
206 * SSP Integration Test control Register - SSP_ITCR
208 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
209 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
212 * SSP Integration Test Input Register - SSP_ITIP
214 #define ITIP_MASK_SSPRXD (0x1UL << 0)
215 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
216 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
217 #define ITIP_MASK_RXDMAC (0x1UL << 3)
218 #define ITIP_MASK_TXDMAC (0x1UL << 4)
219 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
222 * SSP Integration Test output Register - SSP_ITOP
224 #define ITOP_MASK_SSPTXD (0x1UL << 0)
225 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
226 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
227 #define ITOP_MASK_SSPOEn (0x1UL << 3)
228 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
229 #define ITOP_MASK_RORINTR (0x1UL << 5)
230 #define ITOP_MASK_RTINTR (0x1UL << 6)
231 #define ITOP_MASK_RXINTR (0x1UL << 7)
232 #define ITOP_MASK_TXINTR (0x1UL << 8)
233 #define ITOP_MASK_INTR (0x1UL << 9)
234 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
235 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
236 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
237 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
240 * SSP Test Data Register - SSP_TDR
242 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
246 * we use the spi_message.state (void *) pointer to
247 * hold a single state value, that's why all this
248 * (void *) casting is done here.
250 #define STATE_START ((void *) 0)
251 #define STATE_RUNNING ((void *) 1)
252 #define STATE_DONE ((void *) 2)
253 #define STATE_ERROR ((void *) -1)
258 #define QUEUE_RUNNING (0)
259 #define QUEUE_STOPPED (1)
261 * SSP State - Whether Enabled or Disabled
263 #define SSP_DISABLED (0)
264 #define SSP_ENABLED (1)
267 * SSP DMA State - Whether DMA Enabled or Disabled
269 #define SSP_DMA_DISABLED (0)
270 #define SSP_DMA_ENABLED (1)
275 #define SSP_DEFAULT_CLKRATE 0x2
276 #define SSP_DEFAULT_PRESCALE 0x40
279 * SSP Clock Parameter ranges
281 #define CPSDVR_MIN 0x02
282 #define CPSDVR_MAX 0xFE
287 * SSP Interrupt related Macros
289 #define DEFAULT_SSP_REG_IMSC 0x0UL
290 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
291 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
293 #define CLEAR_ALL_INTERRUPTS 0x3
297 * The type of reading going on on this chip
307 * The type of writing going on on this chip
317 * struct vendor_data - vendor-specific config parameters
318 * for PL022 derivates
319 * @fifodepth: depth of FIFOs (both)
320 * @max_bpw: maximum number of bits per word
321 * @unidir: supports unidirection transfers
322 * @extended_cr: 32 bit wide control register 0 with extra
323 * features and extra features in CR1 as found in the ST variants
324 * @pl023: supports a subset of the ST extensions called "PL023"
335 * struct pl022 - This is the private SSP driver data structure
336 * @adev: AMBA device model hookup
337 * @vendor: Vendor data for the IP block
338 * @phybase: The physical memory where the SSP device resides
339 * @virtbase: The virtual memory where the SSP is mapped
340 * @master: SPI framework hookup
341 * @master_info: controller-specific data from machine setup
342 * @regs: SSP controller register's virtual address
343 * @pump_messages: Work struct for scheduling work to the workqueue
344 * @lock: spinlock to syncronise access to driver data
345 * @workqueue: a workqueue on which any spi_message request is queued
346 * @busy: workqueue is busy
347 * @run: workqueue is running
348 * @pump_transfers: Tasklet used in Interrupt Transfer mode
349 * @cur_msg: Pointer to current spi_message being processed
350 * @cur_transfer: Pointer to current spi_transfer
351 * @cur_chip: pointer to current clients chip(assigned from controller_state)
352 * @tx: current position in TX buffer to be read
353 * @tx_end: end position in TX buffer to be read
354 * @rx: current position in RX buffer to be written
355 * @rx_end: end position in RX buffer to be written
356 * @readingtype: the type of read currently going on
357 * @writingtype: the type or write currently going on
360 struct amba_device *adev;
361 struct vendor_data *vendor;
362 resource_size_t phybase;
363 void __iomem *virtbase;
365 struct spi_master *master;
366 struct pl022_ssp_controller *master_info;
367 /* Driver message queue */
368 struct workqueue_struct *workqueue;
369 struct work_struct pump_messages;
370 spinlock_t queue_lock;
371 struct list_head queue;
374 /* Message transfer pump */
375 struct tasklet_struct pump_transfers;
376 struct spi_message *cur_msg;
377 struct spi_transfer *cur_transfer;
378 struct chip_data *cur_chip;
383 enum ssp_reading read;
384 enum ssp_writing write;
387 #ifdef CONFIG_DMA_ENGINE
388 struct dma_chan *dma_rx_channel;
389 struct dma_chan *dma_tx_channel;
390 struct sg_table sgt_rx;
391 struct sg_table sgt_tx;
397 * struct chip_data - To maintain runtime state of SSP for each client chip
398 * @cr0: Value of control register CR0 of SSP - on later ST variants this
399 * register is 32 bits wide rather than just 16
400 * @cr1: Value of control register CR1 of SSP
401 * @dmacr: Value of DMA control Register of SSP
402 * @cpsr: Value of Clock prescale register
403 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
404 * @enable_dma: Whether to enable DMA or not
405 * @write: function ptr to be used to write when doing xfer for this chip
406 * @read: function ptr to be used to read when doing xfer for this chip
407 * @cs_control: chip select callback provided by chip
408 * @xfer_type: polling/interrupt/DMA
410 * Runtime state of the SSP controller, maintained per chip,
411 * This would be set according to the current message that would be served
420 enum ssp_reading read;
421 enum ssp_writing write;
422 void (*cs_control) (u32 command);
427 * null_cs_control - Dummy chip select function
428 * @command: select/delect the chip
430 * If no chip select function is provided by client this is used as dummy
433 static void null_cs_control(u32 command)
435 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
439 * giveback - current spi_message is over, schedule next message and call
440 * callback of this message. Assumes that caller already
441 * set message->status; dma and pio irqs are blocked
442 * @pl022: SSP driver private data structure
444 static void giveback(struct pl022 *pl022)
446 struct spi_transfer *last_transfer;
448 struct spi_message *msg;
449 void (*curr_cs_control) (u32 command);
452 * This local reference to the chip select function
453 * is needed because we set curr_chip to NULL
454 * as a step toward termininating the message.
456 curr_cs_control = pl022->cur_chip->cs_control;
457 spin_lock_irqsave(&pl022->queue_lock, flags);
458 msg = pl022->cur_msg;
459 pl022->cur_msg = NULL;
460 pl022->cur_transfer = NULL;
461 pl022->cur_chip = NULL;
462 queue_work(pl022->workqueue, &pl022->pump_messages);
463 spin_unlock_irqrestore(&pl022->queue_lock, flags);
465 last_transfer = list_entry(msg->transfers.prev,
469 /* Delay if requested before any change in chip select */
470 if (last_transfer->delay_usecs)
472 * FIXME: This runs in interrupt context.
473 * Is this really smart?
475 udelay(last_transfer->delay_usecs);
478 * Drop chip select UNLESS cs_change is true or we are returning
479 * a message with an error, or next message is for another chip
481 if (!last_transfer->cs_change)
482 curr_cs_control(SSP_CHIP_DESELECT);
484 struct spi_message *next_msg;
486 /* Holding of cs was hinted, but we need to make sure
487 * the next message is for the same chip. Don't waste
488 * time with the following tests unless this was hinted.
490 * We cannot postpone this until pump_messages, because
491 * after calling msg->complete (below) the driver that
492 * sent the current message could be unloaded, which
493 * could invalidate the cs_control() callback...
496 /* get a pointer to the next message, if any */
497 spin_lock_irqsave(&pl022->queue_lock, flags);
498 if (list_empty(&pl022->queue))
501 next_msg = list_entry(pl022->queue.next,
502 struct spi_message, queue);
503 spin_unlock_irqrestore(&pl022->queue_lock, flags);
505 /* see if the next and current messages point
508 if (next_msg && next_msg->spi != msg->spi)
510 if (!next_msg || msg->state == STATE_ERROR)
511 curr_cs_control(SSP_CHIP_DESELECT);
515 msg->complete(msg->context);
516 /* This message is completed, so let's turn off the clocks! */
517 clk_disable(pl022->clk);
518 amba_pclk_disable(pl022->adev);
522 * flush - flush the FIFO to reach a clean state
523 * @pl022: SSP driver private data structure
525 static int flush(struct pl022 *pl022)
527 unsigned long limit = loops_per_jiffy << 1;
529 dev_dbg(&pl022->adev->dev, "flush\n");
531 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
532 readw(SSP_DR(pl022->virtbase));
533 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
535 pl022->exp_fifo_level = 0;
541 * restore_state - Load configuration of current chip
542 * @pl022: SSP driver private data structure
544 static void restore_state(struct pl022 *pl022)
546 struct chip_data *chip = pl022->cur_chip;
548 if (pl022->vendor->extended_cr)
549 writel(chip->cr0, SSP_CR0(pl022->virtbase));
551 writew(chip->cr0, SSP_CR0(pl022->virtbase));
552 writew(chip->cr1, SSP_CR1(pl022->virtbase));
553 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
554 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
555 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
556 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
560 * Default SSP Register Values
562 #define DEFAULT_SSP_REG_CR0 ( \
563 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
564 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
565 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
566 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
567 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
570 /* ST versions have slightly different bit layout */
571 #define DEFAULT_SSP_REG_CR0_ST ( \
572 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
573 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
574 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
575 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
576 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
577 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
578 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
581 /* The PL023 version is slightly different again */
582 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
583 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
584 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
585 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
586 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
589 #define DEFAULT_SSP_REG_CR1 ( \
590 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
591 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
592 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
593 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
596 /* ST versions extend this register to use all 16 bits */
597 #define DEFAULT_SSP_REG_CR1_ST ( \
598 DEFAULT_SSP_REG_CR1 | \
599 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
600 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
601 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
602 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
603 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
607 * The PL023 variant has further differences: no loopback mode, no microwire
608 * support, and a new clock feedback delay setting.
610 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
611 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
612 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
613 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
614 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
615 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
616 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
617 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
618 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
621 #define DEFAULT_SSP_REG_CPSR ( \
622 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
625 #define DEFAULT_SSP_REG_DMACR (\
626 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
627 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
631 * load_ssp_default_config - Load default configuration for SSP
632 * @pl022: SSP driver private data structure
634 static void load_ssp_default_config(struct pl022 *pl022)
636 if (pl022->vendor->pl023) {
637 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
638 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
639 } else if (pl022->vendor->extended_cr) {
640 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
641 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
643 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
644 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
646 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
647 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
648 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
649 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
653 * This will write to TX and read from RX according to the parameters
656 static void readwriter(struct pl022 *pl022)
660 * The FIFO depth is different inbetween primecell variants.
661 * I believe filling in too much in the FIFO might cause
662 * errons in 8bit wide transfers on ARM variants (just 8 words
663 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
665 * To prevent this issue, the TX FIFO is only filled to the
666 * unused RX FIFO fill length, regardless of what the TX
667 * FIFO status flag indicates.
669 dev_dbg(&pl022->adev->dev,
670 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
671 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
673 /* Read as much as you can */
674 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
675 && (pl022->rx < pl022->rx_end)) {
676 switch (pl022->read) {
678 readw(SSP_DR(pl022->virtbase));
681 *(u8 *) (pl022->rx) =
682 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
685 *(u16 *) (pl022->rx) =
686 (u16) readw(SSP_DR(pl022->virtbase));
689 *(u32 *) (pl022->rx) =
690 readl(SSP_DR(pl022->virtbase));
693 pl022->rx += (pl022->cur_chip->n_bytes);
694 pl022->exp_fifo_level--;
697 * Write as much as possible up to the RX FIFO size
699 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
700 && (pl022->tx < pl022->tx_end)) {
701 switch (pl022->write) {
703 writew(0x0, SSP_DR(pl022->virtbase));
706 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
709 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
712 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
715 pl022->tx += (pl022->cur_chip->n_bytes);
716 pl022->exp_fifo_level++;
718 * This inner reader takes care of things appearing in the RX
719 * FIFO as we're transmitting. This will happen a lot since the
720 * clock starts running when you put things into the TX FIFO,
721 * and then things are continously clocked into the RX FIFO.
723 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
724 && (pl022->rx < pl022->rx_end)) {
725 switch (pl022->read) {
727 readw(SSP_DR(pl022->virtbase));
730 *(u8 *) (pl022->rx) =
731 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
734 *(u16 *) (pl022->rx) =
735 (u16) readw(SSP_DR(pl022->virtbase));
738 *(u32 *) (pl022->rx) =
739 readl(SSP_DR(pl022->virtbase));
742 pl022->rx += (pl022->cur_chip->n_bytes);
743 pl022->exp_fifo_level--;
747 * When we exit here the TX FIFO should be full and the RX FIFO
754 * next_transfer - Move to the Next transfer in the current spi message
755 * @pl022: SSP driver private data structure
757 * This function moves though the linked list of spi transfers in the
758 * current spi message and returns with the state of current spi
759 * message i.e whether its last transfer is done(STATE_DONE) or
760 * Next transfer is ready(STATE_RUNNING)
762 static void *next_transfer(struct pl022 *pl022)
764 struct spi_message *msg = pl022->cur_msg;
765 struct spi_transfer *trans = pl022->cur_transfer;
767 /* Move to next transfer */
768 if (trans->transfer_list.next != &msg->transfers) {
769 pl022->cur_transfer =
770 list_entry(trans->transfer_list.next,
771 struct spi_transfer, transfer_list);
772 return STATE_RUNNING;
778 * This DMA functionality is only compiled in if we have
779 * access to the generic DMA devices/DMA engine.
781 #ifdef CONFIG_DMA_ENGINE
782 static void unmap_free_dma_scatter(struct pl022 *pl022)
784 /* Unmap and free the SG tables */
785 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
786 pl022->sgt_tx.nents, DMA_TO_DEVICE);
787 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
788 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
789 sg_free_table(&pl022->sgt_rx);
790 sg_free_table(&pl022->sgt_tx);
793 static void dma_callback(void *data)
795 struct pl022 *pl022 = data;
796 struct spi_message *msg = pl022->cur_msg;
798 BUG_ON(!pl022->sgt_rx.sgl);
802 * Optionally dump out buffers to inspect contents, this is
803 * good if you want to convince yourself that the loopback
804 * read/write contents are the same, when adopting to a new
808 struct scatterlist *sg;
811 dma_sync_sg_for_cpu(&pl022->adev->dev,
816 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
817 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
818 print_hex_dump(KERN_ERR, "SPI RX: ",
826 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
827 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
828 print_hex_dump(KERN_ERR, "SPI TX: ",
839 unmap_free_dma_scatter(pl022);
841 /* Update total bytes transfered */
842 msg->actual_length += pl022->cur_transfer->len;
843 if (pl022->cur_transfer->cs_change)
845 cs_control(SSP_CHIP_DESELECT);
847 /* Move to next transfer */
848 msg->state = next_transfer(pl022);
849 tasklet_schedule(&pl022->pump_transfers);
852 static void setup_dma_scatter(struct pl022 *pl022,
855 struct sg_table *sgtab)
857 struct scatterlist *sg;
858 int bytesleft = length;
864 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
866 * If there are less bytes left than what fits
867 * in the current page (plus page alignment offset)
868 * we just feed in this, else we stuff in as much
871 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
872 mapbytes = bytesleft;
874 mapbytes = PAGE_SIZE - offset_in_page(bufp);
875 sg_set_page(sg, virt_to_page(bufp),
876 mapbytes, offset_in_page(bufp));
878 bytesleft -= mapbytes;
879 dev_dbg(&pl022->adev->dev,
880 "set RX/TX target page @ %p, %d bytes, %d left\n",
881 bufp, mapbytes, bytesleft);
884 /* Map the dummy buffer on every page */
885 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
886 if (bytesleft < PAGE_SIZE)
887 mapbytes = bytesleft;
889 mapbytes = PAGE_SIZE;
890 sg_set_page(sg, virt_to_page(pl022->dummypage),
892 bytesleft -= mapbytes;
893 dev_dbg(&pl022->adev->dev,
894 "set RX/TX to dummy page %d bytes, %d left\n",
895 mapbytes, bytesleft);
903 * configure_dma - configures the channels for the next transfer
904 * @pl022: SSP driver's private data structure
906 static int configure_dma(struct pl022 *pl022)
908 struct dma_slave_config rx_conf = {
909 .src_addr = SSP_DR(pl022->phybase),
910 .direction = DMA_FROM_DEVICE,
911 .src_maxburst = pl022->vendor->fifodepth >> 1,
913 struct dma_slave_config tx_conf = {
914 .dst_addr = SSP_DR(pl022->phybase),
915 .direction = DMA_TO_DEVICE,
916 .dst_maxburst = pl022->vendor->fifodepth >> 1,
921 struct dma_chan *rxchan = pl022->dma_rx_channel;
922 struct dma_chan *txchan = pl022->dma_tx_channel;
923 struct dma_async_tx_descriptor *rxdesc;
924 struct dma_async_tx_descriptor *txdesc;
927 /* Check that the channels are available */
928 if (!rxchan || !txchan)
931 switch (pl022->read) {
933 /* Use the same as for writing */
934 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
937 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
940 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
943 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
947 switch (pl022->write) {
949 /* Use the same as for reading */
950 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
953 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
956 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
959 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
963 /* SPI pecularity: we need to read and write the same width */
964 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
965 rx_conf.src_addr_width = tx_conf.dst_addr_width;
966 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
967 tx_conf.dst_addr_width = rx_conf.src_addr_width;
968 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
970 rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
971 (unsigned long) &rx_conf);
972 txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
973 (unsigned long) &tx_conf);
975 /* Create sglists for the transfers */
976 pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
977 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
979 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
981 goto err_alloc_rx_sg;
983 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
985 goto err_alloc_tx_sg;
987 /* Fill in the scatterlists for the RX+TX buffers */
988 setup_dma_scatter(pl022, pl022->rx,
989 pl022->cur_transfer->len, &pl022->sgt_rx);
990 setup_dma_scatter(pl022, pl022->tx,
991 pl022->cur_transfer->len, &pl022->sgt_tx);
993 /* Map DMA buffers */
994 sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
995 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
999 sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1000 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1004 /* Send both scatterlists */
1005 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1007 pl022->sgt_rx.nents,
1009 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1013 txdesc = txchan->device->device_prep_slave_sg(txchan,
1015 pl022->sgt_tx.nents,
1017 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1021 /* Put the callback on the RX transfer only, that should finish last */
1022 rxdesc->callback = dma_callback;
1023 rxdesc->callback_param = pl022;
1025 /* Submit and fire RX and TX with TX last so we're ready to read! */
1026 cookie = rxdesc->tx_submit(rxdesc);
1027 if (dma_submit_error(cookie))
1029 cookie = txdesc->tx_submit(txdesc);
1030 if (dma_submit_error(cookie))
1032 rxchan->device->device_issue_pending(rxchan);
1033 txchan->device->device_issue_pending(txchan);
1040 txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
1042 rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
1043 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1044 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1046 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1047 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1049 sg_free_table(&pl022->sgt_tx);
1051 sg_free_table(&pl022->sgt_rx);
1056 static int __init pl022_dma_probe(struct pl022 *pl022)
1058 dma_cap_mask_t mask;
1060 /* Try to acquire a generic DMA engine slave channel */
1062 dma_cap_set(DMA_SLAVE, mask);
1064 * We need both RX and TX channels to do DMA, else do none
1067 pl022->dma_rx_channel = dma_request_channel(mask,
1068 pl022->master_info->dma_filter,
1069 pl022->master_info->dma_rx_param);
1070 if (!pl022->dma_rx_channel) {
1071 dev_err(&pl022->adev->dev, "no RX DMA channel!\n");
1075 pl022->dma_tx_channel = dma_request_channel(mask,
1076 pl022->master_info->dma_filter,
1077 pl022->master_info->dma_tx_param);
1078 if (!pl022->dma_tx_channel) {
1079 dev_err(&pl022->adev->dev, "no TX DMA channel!\n");
1083 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1084 if (!pl022->dummypage) {
1085 dev_err(&pl022->adev->dev, "no DMA dummypage!\n");
1086 goto err_no_dummypage;
1089 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1090 dma_chan_name(pl022->dma_rx_channel),
1091 dma_chan_name(pl022->dma_tx_channel));
1096 dma_release_channel(pl022->dma_tx_channel);
1098 dma_release_channel(pl022->dma_rx_channel);
1099 pl022->dma_rx_channel = NULL;
1104 static void terminate_dma(struct pl022 *pl022)
1106 struct dma_chan *rxchan = pl022->dma_rx_channel;
1107 struct dma_chan *txchan = pl022->dma_tx_channel;
1109 rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
1110 txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
1111 unmap_free_dma_scatter(pl022);
1114 static void pl022_dma_remove(struct pl022 *pl022)
1117 terminate_dma(pl022);
1118 if (pl022->dma_tx_channel)
1119 dma_release_channel(pl022->dma_tx_channel);
1120 if (pl022->dma_rx_channel)
1121 dma_release_channel(pl022->dma_rx_channel);
1122 kfree(pl022->dummypage);
1126 static inline int configure_dma(struct pl022 *pl022)
1131 static inline int pl022_dma_probe(struct pl022 *pl022)
1136 static inline void pl022_dma_remove(struct pl022 *pl022)
1142 * pl022_interrupt_handler - Interrupt handler for SSP controller
1144 * This function handles interrupts generated for an interrupt based transfer.
1145 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1146 * current message's state as STATE_ERROR and schedule the tasklet
1147 * pump_transfers which will do the postprocessing of the current message by
1148 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1149 * more data, and writes data in TX FIFO till it is not full. If we complete
1150 * the transfer we move to the next transfer and schedule the tasklet.
1152 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1154 struct pl022 *pl022 = dev_id;
1155 struct spi_message *msg = pl022->cur_msg;
1159 if (unlikely(!msg)) {
1160 dev_err(&pl022->adev->dev,
1161 "bad message state in interrupt handler");
1166 /* Read the Interrupt Status Register */
1167 irq_status = readw(SSP_MIS(pl022->virtbase));
1169 if (unlikely(!irq_status))
1173 * This handles the FIFO interrupts, the timeout
1174 * interrupts are flatly ignored, they cannot be
1177 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1179 * Overrun interrupt - bail out since our Data has been
1182 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1183 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1184 dev_err(&pl022->adev->dev,
1185 "RXFIFO is full\n");
1186 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1187 dev_err(&pl022->adev->dev,
1188 "TXFIFO is full\n");
1191 * Disable and clear interrupts, disable SSP,
1192 * mark message with bad status so it can be
1195 writew(DISABLE_ALL_INTERRUPTS,
1196 SSP_IMSC(pl022->virtbase));
1197 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1198 writew((readw(SSP_CR1(pl022->virtbase)) &
1199 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1200 msg->state = STATE_ERROR;
1202 /* Schedule message queue handler */
1203 tasklet_schedule(&pl022->pump_transfers);
1209 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1211 /* Disable Transmit interrupt */
1212 writew(readw(SSP_IMSC(pl022->virtbase)) &
1213 (~SSP_IMSC_MASK_TXIM),
1214 SSP_IMSC(pl022->virtbase));
1218 * Since all transactions must write as much as shall be read,
1219 * we can conclude the entire transaction once RX is complete.
1220 * At this point, all TX will always be finished.
1222 if (pl022->rx >= pl022->rx_end) {
1223 writew(DISABLE_ALL_INTERRUPTS,
1224 SSP_IMSC(pl022->virtbase));
1225 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1226 if (unlikely(pl022->rx > pl022->rx_end)) {
1227 dev_warn(&pl022->adev->dev, "read %u surplus "
1228 "bytes (did you request an odd "
1229 "number of bytes on a 16bit bus?)\n",
1230 (u32) (pl022->rx - pl022->rx_end));
1232 /* Update total bytes transfered */
1233 msg->actual_length += pl022->cur_transfer->len;
1234 if (pl022->cur_transfer->cs_change)
1236 cs_control(SSP_CHIP_DESELECT);
1237 /* Move to next transfer */
1238 msg->state = next_transfer(pl022);
1239 tasklet_schedule(&pl022->pump_transfers);
1247 * This sets up the pointers to memory for the next message to
1248 * send out on the SPI bus.
1250 static int set_up_next_transfer(struct pl022 *pl022,
1251 struct spi_transfer *transfer)
1255 /* Sanity check the message for this bus width */
1256 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1257 if (unlikely(residue != 0)) {
1258 dev_err(&pl022->adev->dev,
1259 "message of %u bytes to transmit but the current "
1260 "chip bus has a data width of %u bytes!\n",
1261 pl022->cur_transfer->len,
1262 pl022->cur_chip->n_bytes);
1263 dev_err(&pl022->adev->dev, "skipping this message\n");
1266 pl022->tx = (void *)transfer->tx_buf;
1267 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1268 pl022->rx = (void *)transfer->rx_buf;
1269 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1271 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1272 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1277 * pump_transfers - Tasklet function which schedules next transfer
1278 * when running in interrupt or DMA transfer mode.
1279 * @data: SSP driver private data structure
1282 static void pump_transfers(unsigned long data)
1284 struct pl022 *pl022 = (struct pl022 *) data;
1285 struct spi_message *message = NULL;
1286 struct spi_transfer *transfer = NULL;
1287 struct spi_transfer *previous = NULL;
1289 /* Get current state information */
1290 message = pl022->cur_msg;
1291 transfer = pl022->cur_transfer;
1293 /* Handle for abort */
1294 if (message->state == STATE_ERROR) {
1295 message->status = -EIO;
1300 /* Handle end of message */
1301 if (message->state == STATE_DONE) {
1302 message->status = 0;
1307 /* Delay if requested at end of transfer before CS change */
1308 if (message->state == STATE_RUNNING) {
1309 previous = list_entry(transfer->transfer_list.prev,
1310 struct spi_transfer,
1312 if (previous->delay_usecs)
1314 * FIXME: This runs in interrupt context.
1315 * Is this really smart?
1317 udelay(previous->delay_usecs);
1319 /* Drop chip select only if cs_change is requested */
1320 if (previous->cs_change)
1321 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1324 message->state = STATE_RUNNING;
1327 if (set_up_next_transfer(pl022, transfer)) {
1328 message->state = STATE_ERROR;
1329 message->status = -EIO;
1333 /* Flush the FIFOs and let's go! */
1336 if (pl022->cur_chip->enable_dma) {
1337 if (configure_dma(pl022)) {
1338 dev_dbg(&pl022->adev->dev,
1339 "configuration of DMA failed, fall back to interrupt mode\n");
1340 goto err_config_dma;
1346 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1349 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1351 u32 irqflags = ENABLE_ALL_INTERRUPTS;
1353 /* Enable target chip */
1354 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1355 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1357 pl022->cur_msg->state = STATE_ERROR;
1358 pl022->cur_msg->status = -EIO;
1362 /* If we're using DMA, set up DMA here */
1363 if (pl022->cur_chip->enable_dma) {
1364 /* Configure DMA transfer */
1365 if (configure_dma(pl022)) {
1366 dev_dbg(&pl022->adev->dev,
1367 "configuration of DMA failed, fall back to interrupt mode\n");
1368 goto err_config_dma;
1370 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1371 irqflags = DISABLE_ALL_INTERRUPTS;
1374 /* Enable SSP, turn on interrupts */
1375 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1376 SSP_CR1(pl022->virtbase));
1377 writew(irqflags, SSP_IMSC(pl022->virtbase));
1380 static void do_polling_transfer(struct pl022 *pl022)
1382 struct spi_message *message = NULL;
1383 struct spi_transfer *transfer = NULL;
1384 struct spi_transfer *previous = NULL;
1385 struct chip_data *chip;
1387 chip = pl022->cur_chip;
1388 message = pl022->cur_msg;
1390 while (message->state != STATE_DONE) {
1391 /* Handle for abort */
1392 if (message->state == STATE_ERROR)
1394 transfer = pl022->cur_transfer;
1396 /* Delay if requested at end of transfer */
1397 if (message->state == STATE_RUNNING) {
1399 list_entry(transfer->transfer_list.prev,
1400 struct spi_transfer, transfer_list);
1401 if (previous->delay_usecs)
1402 udelay(previous->delay_usecs);
1403 if (previous->cs_change)
1404 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1407 message->state = STATE_RUNNING;
1408 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1411 /* Configuration Changing Per Transfer */
1412 if (set_up_next_transfer(pl022, transfer)) {
1414 message->state = STATE_ERROR;
1417 /* Flush FIFOs and enable SSP */
1419 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1420 SSP_CR1(pl022->virtbase));
1422 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1423 /* FIXME: insert a timeout so we don't hang here indefinately */
1424 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end)
1427 /* Update total byte transfered */
1428 message->actual_length += pl022->cur_transfer->len;
1429 if (pl022->cur_transfer->cs_change)
1430 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1431 /* Move to next transfer */
1432 message->state = next_transfer(pl022);
1435 /* Handle end of message */
1436 if (message->state == STATE_DONE)
1437 message->status = 0;
1439 message->status = -EIO;
1446 * pump_messages - Workqueue function which processes spi message queue
1447 * @data: pointer to private data of SSP driver
1449 * This function checks if there is any spi message in the queue that
1450 * needs processing and delegate control to appropriate function
1451 * do_polling_transfer()/do_interrupt_dma_transfer()
1452 * based on the kind of the transfer
1455 static void pump_messages(struct work_struct *work)
1457 struct pl022 *pl022 =
1458 container_of(work, struct pl022, pump_messages);
1459 unsigned long flags;
1461 /* Lock queue and check for queue work */
1462 spin_lock_irqsave(&pl022->queue_lock, flags);
1463 if (list_empty(&pl022->queue) || pl022->run == QUEUE_STOPPED) {
1465 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1468 /* Make sure we are not already running a message */
1469 if (pl022->cur_msg) {
1470 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1473 /* Extract head of queue */
1475 list_entry(pl022->queue.next, struct spi_message, queue);
1477 list_del_init(&pl022->cur_msg->queue);
1479 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1481 /* Initial message state */
1482 pl022->cur_msg->state = STATE_START;
1483 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1484 struct spi_transfer,
1487 /* Setup the SPI using the per chip configuration */
1488 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1490 * We enable the clocks here, then the clocks will be disabled when
1491 * giveback() is called in each method (poll/interrupt/DMA)
1493 amba_pclk_enable(pl022->adev);
1494 clk_enable(pl022->clk);
1495 restore_state(pl022);
1498 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1499 do_polling_transfer(pl022);
1501 do_interrupt_dma_transfer(pl022);
1505 static int __init init_queue(struct pl022 *pl022)
1507 INIT_LIST_HEAD(&pl022->queue);
1508 spin_lock_init(&pl022->queue_lock);
1510 pl022->run = QUEUE_STOPPED;
1513 tasklet_init(&pl022->pump_transfers,
1514 pump_transfers, (unsigned long)pl022);
1516 INIT_WORK(&pl022->pump_messages, pump_messages);
1517 pl022->workqueue = create_singlethread_workqueue(
1518 dev_name(pl022->master->dev.parent));
1519 if (pl022->workqueue == NULL)
1526 static int start_queue(struct pl022 *pl022)
1528 unsigned long flags;
1530 spin_lock_irqsave(&pl022->queue_lock, flags);
1532 if (pl022->run == QUEUE_RUNNING || pl022->busy) {
1533 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1537 pl022->run = QUEUE_RUNNING;
1538 pl022->cur_msg = NULL;
1539 pl022->cur_transfer = NULL;
1540 pl022->cur_chip = NULL;
1541 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1543 queue_work(pl022->workqueue, &pl022->pump_messages);
1549 static int stop_queue(struct pl022 *pl022)
1551 unsigned long flags;
1552 unsigned limit = 500;
1555 spin_lock_irqsave(&pl022->queue_lock, flags);
1557 /* This is a bit lame, but is optimized for the common execution path.
1558 * A wait_queue on the pl022->busy could be used, but then the common
1559 * execution path (pump_messages) would be required to call wake_up or
1560 * friends on every SPI message. Do this instead */
1561 while (!list_empty(&pl022->queue) && pl022->busy && limit--) {
1562 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1564 spin_lock_irqsave(&pl022->queue_lock, flags);
1567 if (!list_empty(&pl022->queue) || pl022->busy)
1569 else pl022->run = QUEUE_STOPPED;
1571 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1576 static int destroy_queue(struct pl022 *pl022)
1580 status = stop_queue(pl022);
1581 /* we are unloading the module or failing to load (only two calls
1582 * to this routine), and neither call can handle a return value.
1583 * However, destroy_workqueue calls flush_workqueue, and that will
1584 * block until all work is done. If the reason that stop_queue
1585 * timed out is that the work will never finish, then it does no
1586 * good to call destroy_workqueue, so return anyway. */
1590 destroy_workqueue(pl022->workqueue);
1595 static int verify_controller_parameters(struct pl022 *pl022,
1596 struct pl022_config_chip const *chip_info)
1598 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1599 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1600 dev_err(&pl022->adev->dev,
1601 "interface is configured incorrectly\n");
1604 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1605 (!pl022->vendor->unidir)) {
1606 dev_err(&pl022->adev->dev,
1607 "unidirectional mode not supported in this "
1608 "hardware version\n");
1611 if ((chip_info->hierarchy != SSP_MASTER)
1612 && (chip_info->hierarchy != SSP_SLAVE)) {
1613 dev_err(&pl022->adev->dev,
1614 "hierarchy is configured incorrectly\n");
1617 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1618 && (chip_info->com_mode != DMA_TRANSFER)
1619 && (chip_info->com_mode != POLLING_TRANSFER)) {
1620 dev_err(&pl022->adev->dev,
1621 "Communication mode is configured incorrectly\n");
1624 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1625 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
1626 dev_err(&pl022->adev->dev,
1627 "RX FIFO Trigger Level is configured incorrectly\n");
1630 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1631 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
1632 dev_err(&pl022->adev->dev,
1633 "TX FIFO Trigger Level is configured incorrectly\n");
1636 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1637 if ((chip_info->ctrl_len < SSP_BITS_4)
1638 || (chip_info->ctrl_len > SSP_BITS_32)) {
1639 dev_err(&pl022->adev->dev,
1640 "CTRL LEN is configured incorrectly\n");
1643 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1644 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1645 dev_err(&pl022->adev->dev,
1646 "Wait State is configured incorrectly\n");
1649 /* Half duplex is only available in the ST Micro version */
1650 if (pl022->vendor->extended_cr) {
1651 if ((chip_info->duplex !=
1652 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1653 && (chip_info->duplex !=
1654 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1655 dev_err(&pl022->adev->dev,
1656 "Microwire duplex mode is configured incorrectly\n");
1660 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1661 dev_err(&pl022->adev->dev,
1662 "Microwire half duplex mode requested,"
1663 " but this is only available in the"
1664 " ST version of PL022\n");
1672 * pl022_transfer - transfer function registered to SPI master framework
1673 * @spi: spi device which is requesting transfer
1674 * @msg: spi message which is to handled is queued to driver queue
1676 * This function is registered to the SPI framework for this SPI master
1677 * controller. It will queue the spi_message in the queue of driver if
1678 * the queue is not stopped and return.
1680 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1682 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1683 unsigned long flags;
1685 spin_lock_irqsave(&pl022->queue_lock, flags);
1687 if (pl022->run == QUEUE_STOPPED) {
1688 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1691 msg->actual_length = 0;
1692 msg->status = -EINPROGRESS;
1693 msg->state = STATE_START;
1695 list_add_tail(&msg->queue, &pl022->queue);
1696 if (pl022->run == QUEUE_RUNNING && !pl022->busy)
1697 queue_work(pl022->workqueue, &pl022->pump_messages);
1699 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1703 static int calculate_effective_freq(struct pl022 *pl022,
1705 struct ssp_clock_params *clk_freq)
1707 /* Lets calculate the frequency parameters */
1710 bool freq_found = false;
1715 rate = clk_get_rate(pl022->clk);
1716 /* cpsdvscr = 2 & scr 0 */
1717 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1718 /* cpsdvsr = 254 & scr = 255 */
1719 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1721 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1722 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1723 while (scr <= SCR_MAX && !freq_found) {
1725 (cpsdvsr * (1 + scr))) > freq)
1729 * This bool is made true when
1730 * effective frequency >=
1731 * target frequency is found
1735 (cpsdvsr * (1 + scr))) != freq) {
1736 if (scr == SCR_MIN) {
1750 dev_dbg(&pl022->adev->dev,
1751 "SSP Effective Frequency is %u\n",
1752 (rate / (cpsdvsr * (1 + scr))));
1753 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1754 clk_freq->scr = (u8) (scr & 0xFF);
1755 dev_dbg(&pl022->adev->dev,
1756 "SSP cpsdvsr = %d, scr = %d\n",
1757 clk_freq->cpsdvsr, clk_freq->scr);
1760 dev_err(&pl022->adev->dev,
1761 "controller data is incorrect: out of range frequency");
1769 * A piece of default chip info unless the platform
1772 static const struct pl022_config_chip pl022_default_chip_info = {
1773 .com_mode = POLLING_TRANSFER,
1774 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1775 .hierarchy = SSP_SLAVE,
1776 .slave_tx_disable = DO_NOT_DRIVE_TX,
1777 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1778 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1779 .ctrl_len = SSP_BITS_8,
1780 .wait_state = SSP_MWIRE_WAIT_ZERO,
1781 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1782 .cs_control = null_cs_control,
1787 * pl022_setup - setup function registered to SPI master framework
1788 * @spi: spi device which is requesting setup
1790 * This function is registered to the SPI framework for this SPI master
1791 * controller. If it is the first time when setup is called by this device,
1792 * this function will initialize the runtime state for this chip and save
1793 * the same in the device structure. Else it will update the runtime info
1794 * with the updated chip info. Nothing is really being written to the
1795 * controller hardware here, that is not done until the actual transfer
1798 static int pl022_setup(struct spi_device *spi)
1800 struct pl022_config_chip const *chip_info;
1801 struct chip_data *chip;
1802 struct ssp_clock_params clk_freq;
1804 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1805 unsigned int bits = spi->bits_per_word;
1808 if (!spi->max_speed_hz)
1811 /* Get controller_state if one is supplied */
1812 chip = spi_get_ctldata(spi);
1815 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1818 "cannot allocate controller state\n");
1822 "allocated memory for controller's runtime state\n");
1825 /* Get controller data if one is supplied */
1826 chip_info = spi->controller_data;
1828 if (chip_info == NULL) {
1829 chip_info = &pl022_default_chip_info;
1830 /* spi_board_info.controller_data not is supplied */
1832 "using default controller_data settings\n");
1835 "using user supplied controller_data settings\n");
1838 * We can override with custom divisors, else we use the board
1841 if ((0 == chip_info->clk_freq.cpsdvsr)
1842 && (0 == chip_info->clk_freq.scr)) {
1843 status = calculate_effective_freq(pl022,
1847 goto err_config_params;
1849 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1850 if ((clk_freq.cpsdvsr % 2) != 0)
1852 clk_freq.cpsdvsr - 1;
1854 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1855 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1857 "cpsdvsr is configured incorrectly\n");
1858 goto err_config_params;
1862 status = verify_controller_parameters(pl022, chip_info);
1864 dev_err(&spi->dev, "controller data is incorrect");
1865 goto err_config_params;
1868 /* Now set controller state based on controller data */
1869 chip->xfer_type = chip_info->com_mode;
1870 if (!chip_info->cs_control) {
1871 chip->cs_control = null_cs_control;
1873 "chip select function is NULL for this chip\n");
1875 chip->cs_control = chip_info->cs_control;
1878 /* PL022 doesn't support less than 4-bits */
1880 goto err_config_params;
1881 } else if (bits <= 8) {
1882 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1884 chip->read = READING_U8;
1885 chip->write = WRITING_U8;
1886 } else if (bits <= 16) {
1887 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1889 chip->read = READING_U16;
1890 chip->write = WRITING_U16;
1892 if (pl022->vendor->max_bpw >= 32) {
1893 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1895 chip->read = READING_U32;
1896 chip->write = WRITING_U32;
1899 "illegal data size for this controller!\n");
1901 "a standard pl022 can only handle "
1902 "1 <= n <= 16 bit words\n");
1904 goto err_config_params;
1908 /* Now Initialize all register settings required for this chip */
1913 if ((chip_info->com_mode == DMA_TRANSFER)
1914 && ((pl022->master_info)->enable_dma)) {
1915 chip->enable_dma = true;
1916 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1918 goto err_config_params;
1919 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1920 SSP_DMACR_MASK_RXDMAE, 0);
1921 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1922 SSP_DMACR_MASK_TXDMAE, 1);
1924 chip->enable_dma = false;
1925 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1926 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1927 SSP_DMACR_MASK_RXDMAE, 0);
1928 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1929 SSP_DMACR_MASK_TXDMAE, 1);
1932 chip->cpsr = clk_freq.cpsdvsr;
1934 /* Special setup for the ST micro extended control registers */
1935 if (pl022->vendor->extended_cr) {
1938 if (pl022->vendor->pl023) {
1939 /* These bits are only in the PL023 */
1940 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1941 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1943 /* These bits are in the PL022 but not PL023 */
1944 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1945 SSP_CR0_MASK_HALFDUP_ST, 5);
1946 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1947 SSP_CR0_MASK_CSS_ST, 16);
1948 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1949 SSP_CR0_MASK_FRF_ST, 21);
1950 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1951 SSP_CR1_MASK_MWAIT_ST, 6);
1953 SSP_WRITE_BITS(chip->cr0, bits - 1,
1954 SSP_CR0_MASK_DSS_ST, 0);
1956 if (spi->mode & SPI_LSB_FIRST) {
1963 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1964 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
1965 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1966 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1967 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1968 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1970 SSP_WRITE_BITS(chip->cr0, bits - 1,
1971 SSP_CR0_MASK_DSS, 0);
1972 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1973 SSP_CR0_MASK_FRF, 4);
1976 /* Stuff that is common for all versions */
1977 if (spi->mode & SPI_CPOL)
1978 tmp = SSP_CLK_POL_IDLE_HIGH;
1980 tmp = SSP_CLK_POL_IDLE_LOW;
1981 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1983 if (spi->mode & SPI_CPHA)
1984 tmp = SSP_CLK_SECOND_EDGE;
1986 tmp = SSP_CLK_FIRST_EDGE;
1987 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
1989 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1990 /* Loopback is available on all versions except PL023 */
1991 if (!pl022->vendor->pl023) {
1992 if (spi->mode & SPI_LOOP)
1993 tmp = LOOPBACK_ENABLED;
1995 tmp = LOOPBACK_DISABLED;
1996 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
1998 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
1999 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2000 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
2002 /* Save controller_state */
2003 spi_set_ctldata(spi, chip);
2006 spi_set_ctldata(spi, NULL);
2012 * pl022_cleanup - cleanup function registered to SPI master framework
2013 * @spi: spi device which is requesting cleanup
2015 * This function is registered to the SPI framework for this SPI master
2016 * controller. It will free the runtime state of chip.
2018 static void pl022_cleanup(struct spi_device *spi)
2020 struct chip_data *chip = spi_get_ctldata(spi);
2022 spi_set_ctldata(spi, NULL);
2027 static int __devinit
2028 pl022_probe(struct amba_device *adev, struct amba_id *id)
2030 struct device *dev = &adev->dev;
2031 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2032 struct spi_master *master;
2033 struct pl022 *pl022 = NULL; /*Data for this driver */
2036 dev_info(&adev->dev,
2037 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2038 if (platform_info == NULL) {
2039 dev_err(&adev->dev, "probe - no platform data supplied\n");
2044 /* Allocate master with space for data */
2045 master = spi_alloc_master(dev, sizeof(struct pl022));
2046 if (master == NULL) {
2047 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2052 pl022 = spi_master_get_devdata(master);
2053 pl022->master = master;
2054 pl022->master_info = platform_info;
2056 pl022->vendor = id->data;
2059 * Bus Number Which has been Assigned to this SSP controller
2062 master->bus_num = platform_info->bus_id;
2063 master->num_chipselect = platform_info->num_chipselect;
2064 master->cleanup = pl022_cleanup;
2065 master->setup = pl022_setup;
2066 master->transfer = pl022_transfer;
2069 * Supports mode 0-3, loopback, and active low CS. Transfers are
2070 * always MS bit first on the original pl022.
2072 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2073 if (pl022->vendor->extended_cr)
2074 master->mode_bits |= SPI_LSB_FIRST;
2076 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2078 status = amba_request_regions(adev, NULL);
2080 goto err_no_ioregion;
2082 pl022->phybase = adev->res.start;
2083 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2084 if (pl022->virtbase == NULL) {
2086 goto err_no_ioremap;
2088 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2089 adev->res.start, pl022->virtbase);
2091 pl022->clk = clk_get(&adev->dev, NULL);
2092 if (IS_ERR(pl022->clk)) {
2093 status = PTR_ERR(pl022->clk);
2094 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2099 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2100 SSP_CR1(pl022->virtbase));
2101 load_ssp_default_config(pl022);
2103 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2106 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2110 /* Get DMA channels */
2111 if (platform_info->enable_dma) {
2112 status = pl022_dma_probe(pl022);
2117 /* Initialize and start queue */
2118 status = init_queue(pl022);
2120 dev_err(&adev->dev, "probe - problem initializing queue\n");
2121 goto err_init_queue;
2123 status = start_queue(pl022);
2125 dev_err(&adev->dev, "probe - problem starting queue\n");
2126 goto err_start_queue;
2128 /* Register with the SPI framework */
2129 amba_set_drvdata(adev, pl022);
2130 status = spi_register_master(master);
2133 "probe - problem registering spi master\n");
2134 goto err_spi_register;
2136 dev_dbg(dev, "probe succeded\n");
2137 /* Disable the silicon block pclk and clock it when needed */
2138 amba_pclk_disable(adev);
2144 destroy_queue(pl022);
2145 pl022_dma_remove(pl022);
2147 free_irq(adev->irq[0], pl022);
2149 clk_put(pl022->clk);
2151 iounmap(pl022->virtbase);
2153 amba_release_regions(adev);
2155 spi_master_put(master);
2161 static int __devexit
2162 pl022_remove(struct amba_device *adev)
2164 struct pl022 *pl022 = amba_get_drvdata(adev);
2169 /* Remove the queue */
2170 status = destroy_queue(pl022);
2173 "queue remove failed (%d)\n", status);
2176 load_ssp_default_config(pl022);
2177 pl022_dma_remove(pl022);
2178 free_irq(adev->irq[0], pl022);
2179 clk_disable(pl022->clk);
2180 clk_put(pl022->clk);
2181 iounmap(pl022->virtbase);
2182 amba_release_regions(adev);
2183 tasklet_disable(&pl022->pump_transfers);
2184 spi_unregister_master(pl022->master);
2185 spi_master_put(pl022->master);
2186 amba_set_drvdata(adev, NULL);
2187 dev_dbg(&adev->dev, "remove succeded\n");
2192 static int pl022_suspend(struct amba_device *adev, pm_message_t state)
2194 struct pl022 *pl022 = amba_get_drvdata(adev);
2197 status = stop_queue(pl022);
2199 dev_warn(&adev->dev, "suspend cannot stop queue\n");
2203 amba_pclk_enable(adev);
2204 load_ssp_default_config(pl022);
2205 amba_pclk_disable(adev);
2206 dev_dbg(&adev->dev, "suspended\n");
2210 static int pl022_resume(struct amba_device *adev)
2212 struct pl022 *pl022 = amba_get_drvdata(adev);
2215 /* Start the queue running */
2216 status = start_queue(pl022);
2218 dev_err(&adev->dev, "problem starting queue (%d)\n", status);
2220 dev_dbg(&adev->dev, "resumed\n");
2225 #define pl022_suspend NULL
2226 #define pl022_resume NULL
2227 #endif /* CONFIG_PM */
2229 static struct vendor_data vendor_arm = {
2233 .extended_cr = false,
2238 static struct vendor_data vendor_st = {
2242 .extended_cr = true,
2246 static struct vendor_data vendor_st_pl023 = {
2250 .extended_cr = true,
2254 static struct amba_id pl022_ids[] = {
2257 * ARM PL022 variant, this has a 16bit wide
2258 * and 8 locations deep TX/RX FIFO
2262 .data = &vendor_arm,
2266 * ST Micro derivative, this has 32bit wide
2267 * and 32 locations deep TX/RX FIFO
2275 * ST-Ericsson derivative "PL023" (this is not
2276 * an official ARM number), this is a PL022 SSP block
2277 * stripped to SPI mode only, it has 32bit wide
2278 * and 32 locations deep TX/RX FIFO but no extended
2283 .data = &vendor_st_pl023,
2288 static struct amba_driver pl022_driver = {
2290 .name = "ssp-pl022",
2292 .id_table = pl022_ids,
2293 .probe = pl022_probe,
2294 .remove = __devexit_p(pl022_remove),
2295 .suspend = pl022_suspend,
2296 .resume = pl022_resume,
2300 static int __init pl022_init(void)
2302 return amba_driver_register(&pl022_driver);
2305 subsys_initcall(pl022_init);
2307 static void __exit pl022_exit(void)
2309 amba_driver_unregister(&pl022_driver);
2312 module_exit(pl022_exit);
2314 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2315 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2316 MODULE_LICENSE("GPL");