drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrjölä <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35
  36 #include <linux/spi/spi.h>
  37
  38 #include <plat/dma.h>
  39 #include <plat/clock.h>
  40
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43
  44 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
  45 #define OMAP2_MCSPI_MAX_CTRL            4
  46
  47 #define OMAP2_MCSPI_REVISION            0x00
  48 #define OMAP2_MCSPI_SYSCONFIG           0x10
  49 #define OMAP2_MCSPI_SYSSTATUS           0x14
  50 #define OMAP2_MCSPI_IRQSTATUS           0x18
  51 #define OMAP2_MCSPI_IRQENABLE           0x1c
  52 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  53 #define OMAP2_MCSPI_SYST                0x24
  54 #define OMAP2_MCSPI_MODULCTRL           0x28
  55
  56 /* per-channel banks, 0x14 bytes each, first is: */
  57 #define OMAP2_MCSPI_CHCONF0             0x2c
  58 #define OMAP2_MCSPI_CHSTAT0             0x30
  59 #define OMAP2_MCSPI_CHCTRL0             0x34
  60 #define OMAP2_MCSPI_TX0                 0x38
  61 #define OMAP2_MCSPI_RX0                 0x3c
  62
  63 /* per-register bitmasks: */
  64
  65 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
  66 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  67 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  BIT(0)
  68 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  69
  70 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  71
  72 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  73 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  74 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  75
  76 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  77 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  78 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  79 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  80 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  81 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  82 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  83 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  84 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  85 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  86 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  87 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  88 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  89 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  90 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  91
  92 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  93 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  94 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  95
  96 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  97
  98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  99
 100 /* We have 2 DMA channels per CS, one for RX and one for TX */
 101 struct omap2_mcspi_dma {
 102         int dma_tx_channel;
 103         int dma_rx_channel;
 104
 105         int dma_tx_sync_dev;
 106         int dma_rx_sync_dev;
 107
 108         struct completion dma_tx_completion;
 109         struct completion dma_rx_completion;
 110 };
 111
 112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 113  * cache operations; better heuristics consider wordsize and bitrate.
 114  */
 115 #define DMA_MIN_BYTES                   8
 116
 117
 118 struct omap2_mcspi {
 119         struct work_struct      work;
 120         /* lock protects queue and registers */
 121         spinlock_t              lock;
 122         struct list_head        msg_queue;
 123         struct spi_master       *master;
 124         struct clk              *ick;
 125         struct clk              *fck;
 126         /* Virtual base address of the controller */
 127         void __iomem            *base;
 128         unsigned long           phys;
 129         /* SPI1 has 4 channels, while SPI2 has 2 */
 130         struct omap2_mcspi_dma  *dma_channels;
 131 };
 132
 133 struct omap2_mcspi_cs {
 134         void __iomem            *base;
 135         unsigned long           phys;
 136         int                     word_len;
 137         struct list_head        node;
 138         /* Context save and restore shadow register */
 139         u32                     chconf0;
 140 };
 141
 142 /* used for context save and restore, structure members to be updated whenever
 143  * corresponding registers are modified.
 144  */
 145 struct omap2_mcspi_regs {
 146         u32 sysconfig;
 147         u32 modulctrl;
 148         u32 wakeupenable;
 149         struct list_head cs;
 150 };
 151
 152 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
 153
 154 static struct workqueue_struct *omap2_mcspi_wq;
 155
 156 #define MOD_REG_BIT(val, mask, set) do { \
 157         if (set) \
 158                 val |= mask; \
 159         else \
 160                 val &= ~mask; \
 161 } while (0)
 162
 163 static inline void mcspi_write_reg(struct spi_master *master,
 164                 int idx, u32 val)
 165 {
 166         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 167
 168         __raw_writel(val, mcspi->base + idx);
 169 }
 170
 171 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 172 {
 173         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 174
 175         return __raw_readl(mcspi->base + idx);
 176 }
 177
 178 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 179                 int idx, u32 val)
 180 {
 181         struct omap2_mcspi_cs   *cs = spi->controller_state;
 182
 183         __raw_writel(val, cs->base +  idx);
 184 }
 185
 186 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 187 {
 188         struct omap2_mcspi_cs   *cs = spi->controller_state;
 189
 190         return __raw_readl(cs->base + idx);
 191 }
 192
 193 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 194 {
 195         struct omap2_mcspi_cs *cs = spi->controller_state;
 196
 197         return cs->chconf0;
 198 }
 199
 200 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 201 {
 202         struct omap2_mcspi_cs *cs = spi->controller_state;
 203
 204         cs->chconf0 = val;
 205         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 206 }
 207
 208 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 209                 int is_read, int enable)
 210 {
 211         u32 l, rw;
 212
 213         l = mcspi_cached_chconf0(spi);
 214
 215         if (is_read) /* 1 is read, 0 write */
 216                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 217         else
 218                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 219
 220         MOD_REG_BIT(l, rw, enable);
 221         mcspi_write_chconf0(spi, l);
 222 }
 223
 224 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 225 {
 226         u32 l;
 227
 228         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 229         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 230 }
 231
 232 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 233 {
 234         u32 l;
 235
 236         l = mcspi_cached_chconf0(spi);
 237         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 238         mcspi_write_chconf0(spi, l);
 239 }
 240
 241 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 242 {
 243         u32 l;
 244
 245         /* setup when switching from (reset default) slave mode
 246          * to single-channel master mode
 247          */
 248         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 249         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 250         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 251         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 252         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 253
 254         omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
 255 }
 256
 257 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 258 {
 259         struct spi_master *spi_cntrl;
 260         struct omap2_mcspi_cs *cs;
 261         spi_cntrl = mcspi->master;
 262
 263         /* McSPI: context restore */
 264         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
 265                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
 266
 267         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
 268                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
 269
 270         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
 271                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
 272
 273         list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
 274                         node)
 275                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 276 }
 277 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
 278 {
 279         clk_disable(mcspi->ick);
 280         clk_disable(mcspi->fck);
 281 }
 282
 283 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
 284 {
 285         if (clk_enable(mcspi->ick))
 286                 return -ENODEV;
 287         if (clk_enable(mcspi->fck))
 288                 return -ENODEV;
 289
 290         omap2_mcspi_restore_ctx(mcspi);
 291
 292         return 0;
 293 }
 294
 295 static unsigned
 296 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 297 {
 298         struct omap2_mcspi      *mcspi;
 299         struct omap2_mcspi_cs   *cs = spi->controller_state;
 300         struct omap2_mcspi_dma  *mcspi_dma;
 301         unsigned int            count, c;
 302         unsigned long           base, tx_reg, rx_reg;
 303         int                     word_len, data_type, element_count;
 304         u8                      * rx;
 305         const u8                * tx;
 306
 307         mcspi = spi_master_get_devdata(spi->master);
 308         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 309
 310         count = xfer->len;
 311         c = count;
 312         word_len = cs->word_len;
 313
 314         base = cs->phys;
 315         tx_reg = base + OMAP2_MCSPI_TX0;
 316         rx_reg = base + OMAP2_MCSPI_RX0;
 317         rx = xfer->rx_buf;
 318         tx = xfer->tx_buf;
 319
 320         if (word_len <= 8) {
 321                 data_type = OMAP_DMA_DATA_TYPE_S8;
 322                 element_count = count;
 323         } else if (word_len <= 16) {
 324                 data_type = OMAP_DMA_DATA_TYPE_S16;
 325                 element_count = count >> 1;
 326         } else /* word_len <= 32 */ {
 327                 data_type = OMAP_DMA_DATA_TYPE_S32;
 328                 element_count = count >> 2;
 329         }
 330
 331         if (tx != NULL) {
 332                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 333                                 data_type, element_count, 1,
 334                                 OMAP_DMA_SYNC_ELEMENT,
 335                                 mcspi_dma->dma_tx_sync_dev, 0);
 336
 337                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 338                                 OMAP_DMA_AMODE_CONSTANT,
 339                                 tx_reg, 0, 0);
 340
 341                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 342                                 OMAP_DMA_AMODE_POST_INC,
 343                                 xfer->tx_dma, 0, 0);
 344         }
 345
 346         if (rx != NULL) {
 347                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 348                                 data_type, element_count - 1, 1,
 349                                 OMAP_DMA_SYNC_ELEMENT,
 350                                 mcspi_dma->dma_rx_sync_dev, 1);
 351
 352                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 353                                 OMAP_DMA_AMODE_CONSTANT,
 354                                 rx_reg, 0, 0);
 355
 356                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 357                                 OMAP_DMA_AMODE_POST_INC,
 358                                 xfer->rx_dma, 0, 0);
 359         }
 360
 361         if (tx != NULL) {
 362                 omap_start_dma(mcspi_dma->dma_tx_channel);
 363                 omap2_mcspi_set_dma_req(spi, 0, 1);
 364         }
 365
 366         if (rx != NULL) {
 367                 omap_start_dma(mcspi_dma->dma_rx_channel);
 368                 omap2_mcspi_set_dma_req(spi, 1, 1);
 369         }
 370
 371         if (tx != NULL) {
 372                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 373                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
 374         }
 375
 376         if (rx != NULL) {
 377                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 378                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
 379                 omap2_mcspi_set_enable(spi, 0);
 380                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 381                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 382                         u32 w;
 383
 384                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 385                         if (word_len <= 8)
 386                                 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
 387                         else if (word_len <= 16)
 388                                 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
 389                         else /* word_len <= 32 */
 390                                 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
 391                 } else {
 392                         dev_err(&spi->dev, "DMA RX last word empty");
 393                         count -= (word_len <= 8)  ? 1 :
 394                                  (word_len <= 16) ? 2 :
 395                                /* word_len <= 32 */ 4;
 396                 }
 397                 omap2_mcspi_set_enable(spi, 1);
 398         }
 399         return count;
 400 }
 401
 402 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 403 {
 404         unsigned long timeout;
 405
 406         timeout = jiffies + msecs_to_jiffies(1000);
 407         while (!(__raw_readl(reg) & bit)) {
 408                 if (time_after(jiffies, timeout))
 409                         return -1;
 410                 cpu_relax();
 411         }
 412         return 0;
 413 }
 414
 415 static unsigned
 416 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 417 {
 418         struct omap2_mcspi      *mcspi;
 419         struct omap2_mcspi_cs   *cs = spi->controller_state;
 420         unsigned int            count, c;
 421         u32                     l;
 422         void __iomem            *base = cs->base;
 423         void __iomem            *tx_reg;
 424         void __iomem            *rx_reg;
 425         void __iomem            *chstat_reg;
 426         int                     word_len;
 427
 428         mcspi = spi_master_get_devdata(spi->master);
 429         count = xfer->len;
 430         c = count;
 431         word_len = cs->word_len;
 432
 433         l = mcspi_cached_chconf0(spi);
 434         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 435
 436         /* We store the pre-calculated register addresses on stack to speed
 437          * up the transfer loop. */
 438         tx_reg          = base + OMAP2_MCSPI_TX0;
 439         rx_reg          = base + OMAP2_MCSPI_RX0;
 440         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 441
 442         if (word_len <= 8) {
 443                 u8              *rx;
 444                 const u8        *tx;
 445
 446                 rx = xfer->rx_buf;
 447                 tx = xfer->tx_buf;
 448
 449                 do {
 450                         c -= 1;
 451                         if (tx != NULL) {
 452                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 453                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 454                                         dev_err(&spi->dev, "TXS timed out\n");
 455                                         goto out;
 456                                 }
 457 #ifdef VERBOSE
 458                                 dev_dbg(&spi->dev, "write-%d %02x\n",
 459                                                 word_len, *tx);
 460 #endif
 461                                 __raw_writel(*tx++, tx_reg);
 462                         }
 463                         if (rx != NULL) {
 464                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 465                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 466                                         dev_err(&spi->dev, "RXS timed out\n");
 467                                         goto out;
 468                                 }
 469                                 /* prevent last RX_ONLY read from triggering
 470                                  * more word i/o: switch to rx+tx
 471                                  */
 472                                 if (c == 0 && tx == NULL)
 473                                         mcspi_write_chconf0(spi, l);
 474                                 *rx++ = __raw_readl(rx_reg);
 475 #ifdef VERBOSE
 476                                 dev_dbg(&spi->dev, "read-%d %02x\n",
 477                                                 word_len, *(rx - 1));
 478 #endif
 479                         }
 480                 } while (c);
 481         } else if (word_len <= 16) {
 482                 u16             *rx;
 483                 const u16       *tx;
 484
 485                 rx = xfer->rx_buf;
 486                 tx = xfer->tx_buf;
 487                 do {
 488                         c -= 2;
 489                         if (tx != NULL) {
 490                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 491                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 492                                         dev_err(&spi->dev, "TXS timed out\n");
 493                                         goto out;
 494                                 }
 495 #ifdef VERBOSE
 496                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 497                                                 word_len, *tx);
 498 #endif
 499                                 __raw_writel(*tx++, tx_reg);
 500                         }
 501                         if (rx != NULL) {
 502                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 503                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 504                                         dev_err(&spi->dev, "RXS timed out\n");
 505                                         goto out;
 506                                 }
 507                                 /* prevent last RX_ONLY read from triggering
 508                                  * more word i/o: switch to rx+tx
 509                                  */
 510                                 if (c == 0 && tx == NULL)
 511                                         mcspi_write_chconf0(spi, l);
 512                                 *rx++ = __raw_readl(rx_reg);
 513 #ifdef VERBOSE
 514                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 515                                                 word_len, *(rx - 1));
 516 #endif
 517                         }
 518                 } while (c);
 519         } else if (word_len <= 32) {
 520                 u32             *rx;
 521                 const u32       *tx;
 522
 523                 rx = xfer->rx_buf;
 524                 tx = xfer->tx_buf;
 525                 do {
 526                         c -= 4;
 527                         if (tx != NULL) {
 528                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 529                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 530                                         dev_err(&spi->dev, "TXS timed out\n");
 531                                         goto out;
 532                                 }
 533 #ifdef VERBOSE
 534                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 535                                                 word_len, *tx);
 536 #endif
 537                                 __raw_writel(*tx++, tx_reg);
 538                         }
 539                         if (rx != NULL) {
 540                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 541                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 542                                         dev_err(&spi->dev, "RXS timed out\n");
 543                                         goto out;
 544                                 }
 545                                 /* prevent last RX_ONLY read from triggering
 546                                  * more word i/o: switch to rx+tx
 547                                  */
 548                                 if (c == 0 && tx == NULL)
 549                                         mcspi_write_chconf0(spi, l);
 550                                 *rx++ = __raw_readl(rx_reg);
 551 #ifdef VERBOSE
 552                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 553                                                 word_len, *(rx - 1));
 554 #endif
 555                         }
 556                 } while (c);
 557         }
 558
 559         /* for TX_ONLY mode, be sure all words have shifted out */
 560         if (xfer->rx_buf == NULL) {
 561                 if (mcspi_wait_for_reg_bit(chstat_reg,
 562                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 563                         dev_err(&spi->dev, "TXS timed out\n");
 564                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 565                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 566                         dev_err(&spi->dev, "EOT timed out\n");
 567         }
 568 out:
 569         return count - c;
 570 }
 571
 572 /* called only when no transfer is active to this device */
 573 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 574                 struct spi_transfer *t)
 575 {
 576         struct omap2_mcspi_cs *cs = spi->controller_state;
 577         struct omap2_mcspi *mcspi;
 578         struct spi_master *spi_cntrl;
 579         u32 l = 0, div = 0;
 580         u8 word_len = spi->bits_per_word;
 581
 582         mcspi = spi_master_get_devdata(spi->master);
 583         spi_cntrl = mcspi->master;
 584
 585         if (t != NULL && t->bits_per_word)
 586                 word_len = t->bits_per_word;
 587
 588         cs->word_len = word_len;
 589
 590         if (spi->max_speed_hz) {
 591                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
 592                                         > spi->max_speed_hz)
 593                         div++;
 594         } else
 595                 div = 15;
 596
 597         l = mcspi_cached_chconf0(spi);
 598
 599         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 600          * REVISIT: this controller could support SPI_3WIRE mode.
 601          */
 602         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 603         l |= OMAP2_MCSPI_CHCONF_DPE0;
 604
 605         /* wordlength */
 606         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 607         l |= (word_len - 1) << 7;
 608
 609         /* set chipselect polarity; manage with FORCE */
 610         if (!(spi->mode & SPI_CS_HIGH))
 611                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 612         else
 613                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 614
 615         /* set clock divisor */
 616         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 617         l |= div << 2;
 618
 619         /* set SPI mode 0..3 */
 620         if (spi->mode & SPI_CPOL)
 621                 l |= OMAP2_MCSPI_CHCONF_POL;
 622         else
 623                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 624         if (spi->mode & SPI_CPHA)
 625                 l |= OMAP2_MCSPI_CHCONF_PHA;
 626         else
 627                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 628
 629         mcspi_write_chconf0(spi, l);
 630
 631         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 632                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 633                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 634                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 635
 636         return 0;
 637 }
 638
 639 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 640 {
 641         struct spi_device       *spi = data;
 642         struct omap2_mcspi      *mcspi;
 643         struct omap2_mcspi_dma  *mcspi_dma;
 644
 645         mcspi = spi_master_get_devdata(spi->master);
 646         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 647
 648         complete(&mcspi_dma->dma_rx_completion);
 649
 650         /* We must disable the DMA RX request */
 651         omap2_mcspi_set_dma_req(spi, 1, 0);
 652 }
 653
 654 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 655 {
 656         struct spi_device       *spi = data;
 657         struct omap2_mcspi      *mcspi;
 658         struct omap2_mcspi_dma  *mcspi_dma;
 659
 660         mcspi = spi_master_get_devdata(spi->master);
 661         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 662
 663         complete(&mcspi_dma->dma_tx_completion);
 664
 665         /* We must disable the DMA TX request */
 666         omap2_mcspi_set_dma_req(spi, 0, 0);
 667 }
 668
 669 static int omap2_mcspi_request_dma(struct spi_device *spi)
 670 {
 671         struct spi_master       *master = spi->master;
 672         struct omap2_mcspi      *mcspi;
 673         struct omap2_mcspi_dma  *mcspi_dma;
 674
 675         mcspi = spi_master_get_devdata(master);
 676         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 677
 678         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 679                         omap2_mcspi_dma_rx_callback, spi,
 680                         &mcspi_dma->dma_rx_channel)) {
 681                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 682                 return -EAGAIN;
 683         }
 684
 685         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 686                         omap2_mcspi_dma_tx_callback, spi,
 687                         &mcspi_dma->dma_tx_channel)) {
 688                 omap_free_dma(mcspi_dma->dma_rx_channel);
 689                 mcspi_dma->dma_rx_channel = -1;
 690                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 691                 return -EAGAIN;
 692         }
 693
 694         init_completion(&mcspi_dma->dma_rx_completion);
 695         init_completion(&mcspi_dma->dma_tx_completion);
 696
 697         return 0;
 698 }
 699
 700 static int omap2_mcspi_setup(struct spi_device *spi)
 701 {
 702         int                     ret;
 703         struct omap2_mcspi      *mcspi;
 704         struct omap2_mcspi_dma  *mcspi_dma;
 705         struct omap2_mcspi_cs   *cs = spi->controller_state;
 706
 707         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 708                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 709                         spi->bits_per_word);
 710                 return -EINVAL;
 711         }
 712
 713         mcspi = spi_master_get_devdata(spi->master);
 714         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 715
 716         if (!cs) {
 717                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 718                 if (!cs)
 719                         return -ENOMEM;
 720                 cs->base = mcspi->base + spi->chip_select * 0x14;
 721                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 722                 cs->chconf0 = 0;
 723                 spi->controller_state = cs;
 724                 /* Link this to context save list */
 725                 list_add_tail(&cs->node,
 726                         &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
 727         }
 728
 729         if (mcspi_dma->dma_rx_channel == -1
 730                         || mcspi_dma->dma_tx_channel == -1) {
 731                 ret = omap2_mcspi_request_dma(spi);
 732                 if (ret < 0)
 733                         return ret;
 734         }
 735
 736         if (omap2_mcspi_enable_clocks(mcspi))
 737                 return -ENODEV;
 738
 739         ret = omap2_mcspi_setup_transfer(spi, NULL);
 740         omap2_mcspi_disable_clocks(mcspi);
 741
 742         return ret;
 743 }
 744
 745 static void omap2_mcspi_cleanup(struct spi_device *spi)
 746 {
 747         struct omap2_mcspi      *mcspi;
 748         struct omap2_mcspi_dma  *mcspi_dma;
 749         struct omap2_mcspi_cs   *cs;
 750
 751         mcspi = spi_master_get_devdata(spi->master);
 752         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 753
 754         if (spi->controller_state) {
 755                 /* Unlink controller state from context save list */
 756                 cs = spi->controller_state;
 757                 list_del(&cs->node);
 758
 759                 kfree(spi->controller_state);
 760         }
 761
 762         if (mcspi_dma->dma_rx_channel != -1) {
 763                 omap_free_dma(mcspi_dma->dma_rx_channel);
 764                 mcspi_dma->dma_rx_channel = -1;
 765         }
 766         if (mcspi_dma->dma_tx_channel != -1) {
 767                 omap_free_dma(mcspi_dma->dma_tx_channel);
 768                 mcspi_dma->dma_tx_channel = -1;
 769         }
 770 }
 771
 772 static void omap2_mcspi_work(struct work_struct *work)
 773 {
 774         struct omap2_mcspi      *mcspi;
 775
 776         mcspi = container_of(work, struct omap2_mcspi, work);
 777         spin_lock_irq(&mcspi->lock);
 778
 779         if (omap2_mcspi_enable_clocks(mcspi))
 780                 goto out;
 781
 782         /* We only enable one channel at a time -- the one whose message is
 783          * at the head of the queue -- although this controller would gladly
 784          * arbitrate among multiple channels.  This corresponds to "single
 785          * channel" master mode.  As a side effect, we need to manage the
 786          * chipselect with the FORCE bit ... CS != channel enable.
 787          */
 788         while (!list_empty(&mcspi->msg_queue)) {
 789                 struct spi_message              *m;
 790                 struct spi_device               *spi;
 791                 struct spi_transfer             *t = NULL;
 792                 int                             cs_active = 0;
 793                 struct omap2_mcspi_cs           *cs;
 794                 int                             par_override = 0;
 795                 int                             status = 0;
 796                 u32                             chconf;
 797
 798                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 799                                  queue);
 800
 801                 list_del_init(&m->queue);
 802                 spin_unlock_irq(&mcspi->lock);
 803
 804                 spi = m->spi;
 805                 cs = spi->controller_state;
 806
 807                 omap2_mcspi_set_enable(spi, 1);
 808                 list_for_each_entry(t, &m->transfers, transfer_list) {
 809                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 810                                 status = -EINVAL;
 811                                 break;
 812                         }
 813                         if (par_override || t->speed_hz || t->bits_per_word) {
 814                                 par_override = 1;
 815                                 status = omap2_mcspi_setup_transfer(spi, t);
 816                                 if (status < 0)
 817                                         break;
 818                                 if (!t->speed_hz && !t->bits_per_word)
 819                                         par_override = 0;
 820                         }
 821
 822                         if (!cs_active) {
 823                                 omap2_mcspi_force_cs(spi, 1);
 824                                 cs_active = 1;
 825                         }
 826
 827                         chconf = mcspi_cached_chconf0(spi);
 828                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 829                         if (t->tx_buf == NULL)
 830                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 831                         else if (t->rx_buf == NULL)
 832                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 833                         mcspi_write_chconf0(spi, chconf);
 834
 835                         if (t->len) {
 836                                 unsigned        count;
 837
 838                                 /* RX_ONLY mode needs dummy data in TX reg */
 839                                 if (t->tx_buf == NULL)
 840                                         __raw_writel(0, cs->base
 841                                                         + OMAP2_MCSPI_TX0);
 842
 843                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 844                                         count = omap2_mcspi_txrx_dma(spi, t);
 845                                 else
 846                                         count = omap2_mcspi_txrx_pio(spi, t);
 847                                 m->actual_length += count;
 848
 849                                 if (count != t->len) {
 850                                         status = -EIO;
 851                                         break;
 852                                 }
 853                         }
 854
 855                         if (t->delay_usecs)
 856                                 udelay(t->delay_usecs);
 857
 858                         /* ignore the "leave it on after last xfer" hint */
 859                         if (t->cs_change) {
 860                                 omap2_mcspi_force_cs(spi, 0);
 861                                 cs_active = 0;
 862                         }
 863                 }
 864
 865                 /* Restore defaults if they were overriden */
 866                 if (par_override) {
 867                         par_override = 0;
 868                         status = omap2_mcspi_setup_transfer(spi, NULL);
 869                 }
 870
 871                 if (cs_active)
 872                         omap2_mcspi_force_cs(spi, 0);
 873
 874                 omap2_mcspi_set_enable(spi, 0);
 875
 876                 m->status = status;
 877                 m->complete(m->context);
 878
 879                 spin_lock_irq(&mcspi->lock);
 880         }
 881
 882         omap2_mcspi_disable_clocks(mcspi);
 883
 884 out:
 885         spin_unlock_irq(&mcspi->lock);
 886 }
 887
 888 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 889 {
 890         struct omap2_mcspi      *mcspi;
 891         unsigned long           flags;
 892         struct spi_transfer     *t;
 893
 894         m->actual_length = 0;
 895         m->status = 0;
 896
 897         /* reject invalid messages and transfers */
 898         if (list_empty(&m->transfers) || !m->complete)
 899                 return -EINVAL;
 900         list_for_each_entry(t, &m->transfers, transfer_list) {
 901                 const void      *tx_buf = t->tx_buf;
 902                 void            *rx_buf = t->rx_buf;
 903                 unsigned        len = t->len;
 904
 905                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 906                                 || (len && !(rx_buf || tx_buf))
 907                                 || (t->bits_per_word &&
 908                                         (  t->bits_per_word < 4
 909                                         || t->bits_per_word > 32))) {
 910                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 911                                         t->speed_hz,
 912                                         len,
 913                                         tx_buf ? "tx" : "",
 914                                         rx_buf ? "rx" : "",
 915                                         t->bits_per_word);
 916                         return -EINVAL;
 917                 }
 918                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
 919                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
 920                                         t->speed_hz,
 921                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
 922                         return -EINVAL;
 923                 }
 924
 925                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
 926                         continue;
 927
 928                 /* Do DMA mapping "early" for better error reporting and
 929                  * dcache use.  Note that if dma_unmap_single() ever starts
 930                  * to do real work on ARM, we'd need to clean up mappings
 931                  * for previous transfers on *ALL* exits of this loop...
 932                  */
 933                 if (tx_buf != NULL) {
 934                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
 935                                         len, DMA_TO_DEVICE);
 936                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 937                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 938                                                 'T', len);
 939                                 return -EINVAL;
 940                         }
 941                 }
 942                 if (rx_buf != NULL) {
 943                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
 944                                         DMA_FROM_DEVICE);
 945                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
 946                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 947                                                 'R', len);
 948                                 if (tx_buf != NULL)
 949                                         dma_unmap_single(NULL, t->tx_dma,
 950                                                         len, DMA_TO_DEVICE);
 951                                 return -EINVAL;
 952                         }
 953                 }
 954         }
 955
 956         mcspi = spi_master_get_devdata(spi->master);
 957
 958         spin_lock_irqsave(&mcspi->lock, flags);
 959         list_add_tail(&m->queue, &mcspi->msg_queue);
 960         queue_work(omap2_mcspi_wq, &mcspi->work);
 961         spin_unlock_irqrestore(&mcspi->lock, flags);
 962
 963         return 0;
 964 }
 965
 966 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
 967 {
 968         struct spi_master       *master = mcspi->master;
 969         u32                     tmp;
 970
 971         if (omap2_mcspi_enable_clocks(mcspi))
 972                 return -1;
 973
 974         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 975                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
 976         do {
 977                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
 978         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
 979
 980         tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
 981                 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
 982                 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
 983         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
 984         omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
 985
 986         tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
 987         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
 988         omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
 989
 990         omap2_mcspi_set_master_mode(master);
 991         omap2_mcspi_disable_clocks(mcspi);
 992         return 0;
 993 }
 994
 995 static u8 __initdata spi1_rxdma_id [] = {
 996         OMAP24XX_DMA_SPI1_RX0,
 997         OMAP24XX_DMA_SPI1_RX1,
 998         OMAP24XX_DMA_SPI1_RX2,
 999         OMAP24XX_DMA_SPI1_RX3,
1000 };
1001
1002 static u8 __initdata spi1_txdma_id [] = {
1003         OMAP24XX_DMA_SPI1_TX0,
1004         OMAP24XX_DMA_SPI1_TX1,
1005         OMAP24XX_DMA_SPI1_TX2,
1006         OMAP24XX_DMA_SPI1_TX3,
1007 };
1008
1009 static u8 __initdata spi2_rxdma_id[] = {
1010         OMAP24XX_DMA_SPI2_RX0,
1011         OMAP24XX_DMA_SPI2_RX1,
1012 };
1013
1014 static u8 __initdata spi2_txdma_id[] = {
1015         OMAP24XX_DMA_SPI2_TX0,
1016         OMAP24XX_DMA_SPI2_TX1,
1017 };
1018
1019 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1020         || defined(CONFIG_ARCH_OMAP4)
1021 static u8 __initdata spi3_rxdma_id[] = {
1022         OMAP24XX_DMA_SPI3_RX0,
1023         OMAP24XX_DMA_SPI3_RX1,
1024 };
1025
1026 static u8 __initdata spi3_txdma_id[] = {
1027         OMAP24XX_DMA_SPI3_TX0,
1028         OMAP24XX_DMA_SPI3_TX1,
1029 };
1030 #endif
1031
1032 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1033 static u8 __initdata spi4_rxdma_id[] = {
1034         OMAP34XX_DMA_SPI4_RX0,
1035 };
1036
1037 static u8 __initdata spi4_txdma_id[] = {
1038         OMAP34XX_DMA_SPI4_TX0,
1039 };
1040 #endif
1041
1042 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1043 {
1044         struct spi_master       *master;
1045         struct omap2_mcspi      *mcspi;
1046         struct resource         *r;
1047         int                     status = 0, i;
1048         const u8                *rxdma_id, *txdma_id;
1049         unsigned                num_chipselect;
1050
1051         switch (pdev->id) {
1052         case 1:
1053                 rxdma_id = spi1_rxdma_id;
1054                 txdma_id = spi1_txdma_id;
1055                 num_chipselect = 4;
1056                 break;
1057         case 2:
1058                 rxdma_id = spi2_rxdma_id;
1059                 txdma_id = spi2_txdma_id;
1060                 num_chipselect = 2;
1061                 break;
1062 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1063         || defined(CONFIG_ARCH_OMAP4)
1064         case 3:
1065                 rxdma_id = spi3_rxdma_id;
1066                 txdma_id = spi3_txdma_id;
1067                 num_chipselect = 2;
1068                 break;
1069 #endif
1070 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1071         case 4:
1072                 rxdma_id = spi4_rxdma_id;
1073                 txdma_id = spi4_txdma_id;
1074                 num_chipselect = 1;
1075                 break;
1076 #endif
1077         default:
1078                 return -EINVAL;
1079         }
1080
1081         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1082         if (master == NULL) {
1083                 dev_dbg(&pdev->dev, "master allocation failed\n");
1084                 return -ENOMEM;
1085         }
1086
1087         /* the spi->mode bits understood by this driver: */
1088         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1089
1090         if (pdev->id != -1)
1091                 master->bus_num = pdev->id;
1092
1093         master->setup = omap2_mcspi_setup;
1094         master->transfer = omap2_mcspi_transfer;
1095         master->cleanup = omap2_mcspi_cleanup;
1096         master->num_chipselect = num_chipselect;
1097
1098         dev_set_drvdata(&pdev->dev, master);
1099
1100         mcspi = spi_master_get_devdata(master);
1101         mcspi->master = master;
1102
1103         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1104         if (r == NULL) {
1105                 status = -ENODEV;
1106                 goto err1;
1107         }
1108         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1109                         dev_name(&pdev->dev))) {
1110                 status = -EBUSY;
1111                 goto err1;
1112         }
1113
1114         mcspi->phys = r->start;
1115         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1116         if (!mcspi->base) {
1117                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1118                 status = -ENOMEM;
1119                 goto err1aa;
1120         }
1121
1122         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1123
1124         spin_lock_init(&mcspi->lock);
1125         INIT_LIST_HEAD(&mcspi->msg_queue);
1126         INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1127
1128         mcspi->ick = clk_get(&pdev->dev, "ick");
1129         if (IS_ERR(mcspi->ick)) {
1130                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1131                 status = PTR_ERR(mcspi->ick);
1132                 goto err1a;
1133         }
1134         mcspi->fck = clk_get(&pdev->dev, "fck");
1135         if (IS_ERR(mcspi->fck)) {
1136                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1137                 status = PTR_ERR(mcspi->fck);
1138                 goto err2;
1139         }
1140
1141         mcspi->dma_channels = kcalloc(master->num_chipselect,
1142                         sizeof(struct omap2_mcspi_dma),
1143                         GFP_KERNEL);
1144
1145         if (mcspi->dma_channels == NULL)
1146                 goto err3;
1147
1148         for (i = 0; i < num_chipselect; i++) {
1149                 mcspi->dma_channels[i].dma_rx_channel = -1;
1150                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1151                 mcspi->dma_channels[i].dma_tx_channel = -1;
1152                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1153         }
1154
1155         if (omap2_mcspi_reset(mcspi) < 0)
1156                 goto err4;
1157
1158         status = spi_register_master(master);
1159         if (status < 0)
1160                 goto err4;
1161
1162         return status;
1163
1164 err4:
1165         kfree(mcspi->dma_channels);
1166 err3:
1167         clk_put(mcspi->fck);
1168 err2:
1169         clk_put(mcspi->ick);
1170 err1a:
1171         iounmap(mcspi->base);
1172 err1aa:
1173         release_mem_region(r->start, (r->end - r->start) + 1);
1174 err1:
1175         spi_master_put(master);
1176         return status;
1177 }
1178
1179 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1180 {
1181         struct spi_master       *master;
1182         struct omap2_mcspi      *mcspi;
1183         struct omap2_mcspi_dma  *dma_channels;
1184         struct resource         *r;
1185         void __iomem *base;
1186
1187         master = dev_get_drvdata(&pdev->dev);
1188         mcspi = spi_master_get_devdata(master);
1189         dma_channels = mcspi->dma_channels;
1190
1191         clk_put(mcspi->fck);
1192         clk_put(mcspi->ick);
1193
1194         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1195         release_mem_region(r->start, (r->end - r->start) + 1);
1196
1197         base = mcspi->base;
1198         spi_unregister_master(master);
1199         iounmap(base);
1200         kfree(dma_channels);
1201
1202         return 0;
1203 }
1204
1205 /* work with hotplug and coldplug */
1206 MODULE_ALIAS("platform:omap2_mcspi");
1207
1208 static struct platform_driver omap2_mcspi_driver = {
1209         .driver = {
1210                 .name =         "omap2_mcspi",
1211                 .owner =        THIS_MODULE,
1212         },
1213         .remove =       __exit_p(omap2_mcspi_remove),
1214 };
1215
1216
1217 static int __init omap2_mcspi_init(void)
1218 {
1219         omap2_mcspi_wq = create_singlethread_workqueue(
1220                                 omap2_mcspi_driver.driver.name);
1221         if (omap2_mcspi_wq == NULL)
1222                 return -1;
1223         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1224 }
1225 subsys_initcall(omap2_mcspi_init);
1226
1227 static void __exit omap2_mcspi_exit(void)
1228 {
1229         platform_driver_unregister(&omap2_mcspi_driver);
1230
1231         destroy_workqueue(omap2_mcspi_wq);
1232 }
1233 module_exit(omap2_mcspi_exit);
1234
1235 MODULE_LICENSE("GPL");