1 /*drivers/serial/rk2818_spim.c - driver for rk2818 spim device
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/dma-mapping.h>
16 #include <linux/interrupt.h>
17 #include <linux/highmem.h>
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/cpufreq.h>
23 #include <mach/gpio.h>
24 #include <linux/dma-mapping.h>
27 #include "rk2818_spim.h"
28 #include <linux/spi/spi.h>
29 #include <mach/board.h>
31 #ifdef CONFIG_DEBUG_FS
32 #include <linux/debugfs.h>
35 #define START_STATE ((void *)0)
36 #define RUNNING_STATE ((void *)1)
37 #define DONE_STATE ((void *)2)
38 #define ERROR_STATE ((void *)-1)
40 #define QUEUE_RUNNING 0
41 #define QUEUE_STOPPED 1
43 #define MRST_SPI_DEASSERT 0
44 #define MRST_SPI_ASSERT 1 ///CS0
45 #define MRST_SPI_ASSERT1 2 ///CS1
47 /* Slave spi_dev related */
50 u8 cs; /* chip select pin */
51 u8 n_bytes; /* current is a 1/2/4 byte op */
52 u8 tmode; /* TR/TO/RO/EEPROM */
53 u8 type; /* SPI/SSP/MicroWire */
55 u8 poll_mode; /* 1 means use poll mode */
62 u16 clk_div; /* baud rate divider */
63 u32 speed_hz; /* baud rate */
64 int (*write)(struct rk2818_spi *dws);
65 int (*read)(struct rk2818_spi *dws);
66 void (*cs_control)(struct rk2818_spi *dws, u32 cs);
69 #ifdef CONFIG_DEBUG_FS
70 static int spi_show_regs_open(struct inode *inode, struct file *file)
72 file->private_data = inode->i_private;
76 #define SPI_REGS_BUFSIZE 1024
77 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
78 size_t count, loff_t *ppos)
80 struct rk2818_spi *dws;
85 dws = file->private_data;
87 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
91 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
92 "MRST SPI0 registers:\n");
93 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
94 "=================================\n");
95 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
96 "CTRL0: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR0));
97 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
98 "CTRL1: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR1));
99 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
100 "SSIENR: \t0x%08x\n", rk2818_readl(dws, SPIM_SPIENR));
101 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
102 "SER: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SER));
103 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
104 "BAUDR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_BAUDR));
105 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
106 "TXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_TXFTLR));
107 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
108 "RXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_RXFTLR));
109 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
110 "TXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_TXFLR));
111 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
112 "RXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_RXFLR));
113 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
114 "SR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SR));
115 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
116 "IMR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_IMR));
117 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
118 "ISR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_ISR));
119 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
120 "DMACR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_DMACR));
121 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
122 "DMATDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMATDLR));
123 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
124 "DMARDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMARDLR));
125 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
126 "=================================\n");
128 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
133 static const struct file_operations mrst_spi_regs_ops = {
134 .owner = THIS_MODULE,
135 .open = spi_show_regs_open,
136 .read = spi_show_regs,
139 static int mrst_spi_debugfs_init(struct rk2818_spi *dws)
141 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
145 debugfs_create_file("registers", S_IFREG | S_IRUGO,
146 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
150 static void mrst_spi_debugfs_remove(struct rk2818_spi *dws)
153 debugfs_remove_recursive(dws->debugfs);
157 static inline int mrst_spi_debugfs_init(struct rk2818_spi *dws)
162 static inline void mrst_spi_debugfs_remove(struct rk2818_spi *dws)
165 #endif /* CONFIG_DEBUG_FS */
167 static void wait_till_not_busy(struct rk2818_spi *dws)
169 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
171 while (time_before(jiffies, end)) {
172 if (!(rk2818_readw(dws, SPIM_SR) & SR_BUSY))
175 dev_err(&dws->master->dev,
176 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
179 static void flush(struct rk2818_spi *dws)
181 while (rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
182 rk2818_readw(dws, SPIM_DR0);
184 wait_till_not_busy(dws);
187 static void spi_cs_control(struct rk2818_spi *dws, u32 cs)
189 struct rk2818_spi_platform_data *pdata = dws->master->dev.platform_data;
190 struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;
194 for (i=0; i<pdata->num_chipselect; i++)
195 gpio_direction_output(cs_gpios[i].cs_gpio, GPIO_HIGH);
197 gpio_direction_output(cs_gpios[cs-1].cs_gpio, GPIO_LOW);
200 static int null_writer(struct rk2818_spi *dws)
202 u8 n_bytes = dws->n_bytes;
204 if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
205 || (dws->tx == dws->tx_end))
207 rk2818_writew(dws, SPIM_DR0, 0);
210 wait_till_not_busy(dws);
214 static int null_reader(struct rk2818_spi *dws)
216 u8 n_bytes = dws->n_bytes;
217 while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
218 && (dws->rx < dws->rx_end)) {
219 rk2818_readw(dws, SPIM_DR0);
222 wait_till_not_busy(dws);
223 return dws->rx == dws->rx_end;
226 static int u8_writer(struct rk2818_spi *dws)
228 if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
229 || (dws->tx == dws->tx_end))
231 rk2818_writew(dws, SPIM_DR0, *(u8 *)(dws->tx));
234 wait_till_not_busy(dws);
238 static int u8_reader(struct rk2818_spi *dws)
240 while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
241 && (dws->rx < dws->rx_end)) {
242 *(u8 *)(dws->rx) = rk2818_readw(dws, SPIM_DR0);
246 wait_till_not_busy(dws);
247 return dws->rx == dws->rx_end;
250 static int u16_writer(struct rk2818_spi *dws)
252 if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
253 || (dws->tx == dws->tx_end))
256 rk2818_writew(dws, SPIM_DR0, *(u16 *)(dws->tx));
259 wait_till_not_busy(dws);
263 static int u16_reader(struct rk2818_spi *dws)
267 while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
268 && (dws->rx < dws->rx_end)) {
269 temp = rk2818_readw(dws, SPIM_DR0);
270 *(u16 *)(dws->rx) = temp;
274 wait_till_not_busy(dws);
275 return dws->rx == dws->rx_end;
278 static void *next_transfer(struct rk2818_spi *dws)
280 struct spi_message *msg = dws->cur_msg;
281 struct spi_transfer *trans = dws->cur_transfer;
283 /* Move to next transfer */
284 if (trans->transfer_list.next != &msg->transfers) {
286 list_entry(trans->transfer_list.next,
289 return RUNNING_STATE;
295 * Note: first step is the protocol driver prepares
296 * a dma-capable memory, and this func just need translate
297 * the virt addr to physical
299 static int map_dma_buffers(struct rk2818_spi *dws)
301 if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
302 || !dws->cur_chip->enable_dma)
305 if (dws->cur_transfer->tx_dma)
306 dws->tx_dma = dws->cur_transfer->tx_dma;
308 if (dws->cur_transfer->rx_dma)
309 dws->rx_dma = dws->cur_transfer->rx_dma;
314 /* Caller already set message->status; dma and pio irqs are blocked */
315 static void giveback(struct rk2818_spi *dws)
317 struct spi_transfer *last_transfer;
319 struct spi_message *msg;
321 spin_lock_irqsave(&dws->lock, flags);
324 dws->cur_transfer = NULL;
325 dws->prev_chip = dws->cur_chip;
326 dws->cur_chip = NULL;
328 queue_work(dws->workqueue, &dws->pump_messages);
329 spin_unlock_irqrestore(&dws->lock, flags);
331 last_transfer = list_entry(msg->transfers.prev,
335 if (!last_transfer->cs_change)
336 dws->cs_control(dws,MRST_SPI_DEASSERT);
340 msg->complete(msg->context);
343 static void int_error_stop(struct rk2818_spi *dws, const char *msg)
345 /* Stop and reset hw */
347 spi_enable_chip(dws, 0);
349 dev_err(&dws->master->dev, "%s\n", msg);
350 dws->cur_msg->state = ERROR_STATE;
351 tasklet_schedule(&dws->pump_transfers);
354 static void transfer_complete(struct rk2818_spi *dws)
356 /* Update total byte transfered return count actual bytes read */
357 dws->cur_msg->actual_length += dws->len;
359 /* Move to next transfer */
360 dws->cur_msg->state = next_transfer(dws);
362 /* Handle end of message */
363 if (dws->cur_msg->state == DONE_STATE) {
364 dws->cur_msg->status = 0;
367 tasklet_schedule(&dws->pump_transfers);
370 static irqreturn_t interrupt_transfer(struct rk2818_spi *dws)
372 u16 irq_status, irq_mask = 0x3f;
373 u32 int_level = dws->fifo_len / 2;
376 irq_status = rk2818_readw(dws, SPIM_ISR) & irq_mask;
378 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
379 rk2818_readw(dws, SPIM_TXOICR);
380 rk2818_readw(dws, SPIM_RXOICR);
381 rk2818_readw(dws, SPIM_RXUICR);
382 int_error_stop(dws, "interrupt_transfer: fifo overrun");
386 if (irq_status & SPI_INT_TXEI) {
387 spi_mask_intr(dws, SPI_INT_TXEI);
389 left = (dws->tx_end - dws->tx) / dws->n_bytes;
390 left = (left > int_level) ? int_level : left;
396 /* Re-enable the IRQ if there is still data left to tx */
397 if (dws->tx_end > dws->tx)
398 spi_umask_intr(dws, SPI_INT_TXEI);
400 transfer_complete(dws);
406 static irqreturn_t rk2818_spi_irq(int irq, void *dev_id)
408 struct rk2818_spi *dws = dev_id;
411 spi_mask_intr(dws, SPI_INT_TXEI);
416 return dws->transfer_handler(dws);
419 /* Must be called inside pump_transfers() */
420 static void poll_transfer(struct rk2818_spi *dws)
422 while (dws->write(dws))
425 transfer_complete(dws);
428 static void dma_transfer(struct rk2818_spi *dws, struct spi_transfer *xfer) //int cs_change)
433 static void spi_chip_sel(struct rk2818_spi *dws, u16 cs)
435 if(cs >= dws->master->num_chipselect)
438 if (dws->cs_control){
439 dws->cs_control(dws, cs+1);
441 //rk2818_writel(dws, SPIM_SER, 1 << cs);
442 rk2818_writel(dws, SPIM_SER, 1 << 0);
445 static void pump_transfers(unsigned long data)
447 struct rk2818_spi *dws = (struct rk2818_spi *)data;
448 struct spi_message *message = NULL;
449 struct spi_transfer *transfer = NULL;
450 struct spi_transfer *previous = NULL;
451 struct spi_device *spi = NULL;
452 struct chip_data *chip = NULL;
461 /* Get current state information */
462 message = dws->cur_msg;
463 transfer = dws->cur_transfer;
464 chip = dws->cur_chip;
466 if (unlikely(!chip->clk_div))
467 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
468 if (message->state == ERROR_STATE) {
469 message->status = -EIO;
473 /* Handle end of message */
474 if (message->state == DONE_STATE) {
479 /* Delay if requested at end of transfer*/
480 if (message->state == RUNNING_STATE) {
481 previous = list_entry(transfer->transfer_list.prev,
484 if (previous->delay_usecs)
485 udelay(previous->delay_usecs);
488 dws->n_bytes = chip->n_bytes;
489 dws->dma_width = chip->dma_width;
490 dws->cs_control = chip->cs_control;
492 dws->rx_dma = transfer->rx_dma;
493 dws->tx_dma = transfer->tx_dma;
494 dws->tx = (void *)transfer->tx_buf;
495 dws->tx_end = dws->tx + transfer->len;
496 dws->rx = transfer->rx_buf;
497 dws->rx_end = dws->rx + transfer->len;
498 dws->write = dws->tx ? chip->write : null_writer;
499 dws->read = dws->rx ? chip->read : null_reader;
500 dws->cs_change = transfer->cs_change;
501 dws->len = dws->cur_transfer->len;
502 if (chip != dws->prev_chip)
507 /* Handle per transfer options for bpw and speed */
508 if (transfer->speed_hz) {
509 speed = chip->speed_hz;
511 if (transfer->speed_hz != speed) {
512 speed = transfer->speed_hz;
513 if (speed > clk_get_rate(dws->clock_spim)) {
514 printk(KERN_ERR "MRST SPI0: unsupported"
515 "freq: %dHz\n", speed);
516 message->status = -EIO;
520 /* clk_div doesn't support odd number */
521 clk_div = clk_get_rate(dws->clock_spim) / speed;
522 clk_div = (clk_div + 1) & 0xfffe;
524 chip->speed_hz = speed;
525 chip->clk_div = clk_div;
528 if (transfer->bits_per_word) {
529 bits = transfer->bits_per_word;
535 dws->read = (dws->read != null_reader) ?
536 u8_reader : null_reader;
537 dws->write = (dws->write != null_writer) ?
538 u8_writer : null_writer;
543 dws->read = (dws->read != null_reader) ?
544 u16_reader : null_reader;
545 dws->write = (dws->write != null_writer) ?
546 u16_writer : null_writer;
549 printk(KERN_ERR "MRST SPI0: unsupported bits:"
551 message->status = -EIO;
556 | (chip->type << SPI_FRF_OFFSET)
557 | (spi->mode << SPI_MODE_OFFSET)
558 | (chip->tmode << SPI_TMOD_OFFSET);
560 message->state = RUNNING_STATE;
563 * Adjust transfer mode if necessary. Requires platform dependent
564 * chipselect mechanism.
566 if (dws->cs_control) {
567 if (dws->rx && dws->tx)
574 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
575 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
577 /* Check if current transfer is a DMA transaction */
578 dws->dma_mapped = map_dma_buffers(dws);
582 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
584 if (!dws->dma_mapped && !chip->poll_mode) {
585 int templen = dws->len / dws->n_bytes;
586 txint_level = dws->fifo_len / 2;
587 txint_level = (templen > txint_level) ? txint_level : templen;
589 imask |= SPI_INT_TXEI;
590 dws->transfer_handler = interrupt_transfer;
594 * Reprogram registers only if
595 * 1. chip select changes
596 * 2. clk_div is changed
597 * 3. control value changes
599 if (rk2818_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {
600 spi_enable_chip(dws, 0);
601 if (rk2818_readw(dws, SPIM_CTRLR0) != cr0)
602 rk2818_writew(dws, SPIM_CTRLR0, cr0);
604 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
605 spi_chip_sel(dws, spi->chip_select);
606 /* Set the interrupt mask, for poll mode just diable all int */
607 spi_mask_intr(dws, 0xff);
609 spi_umask_intr(dws, imask);
611 rk2818_writew(dws, SPIM_TXFTLR, txint_level);
613 spi_enable_chip(dws, 1);
615 dws->prev_chip = chip;
619 dma_transfer(dws, transfer); ///cs_change);
631 static void pump_messages(struct work_struct *work)
633 struct rk2818_spi *dws =
634 container_of(work, struct rk2818_spi, pump_messages);
637 /* Lock queue and check for queue work */
638 spin_lock_irqsave(&dws->lock, flags);
639 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
641 spin_unlock_irqrestore(&dws->lock, flags);
645 /* Make sure we are not already running a message */
647 spin_unlock_irqrestore(&dws->lock, flags);
651 /* Extract head of queue */
652 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
653 list_del_init(&dws->cur_msg->queue);
655 /* Initial message state*/
656 dws->cur_msg->state = START_STATE;
657 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
660 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
661 dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj
663 /* Mark as busy and launch transfers */
664 tasklet_schedule(&dws->pump_transfers);
667 spin_unlock_irqrestore(&dws->lock, flags);
670 /* spi_device use this to queue in their spi_msg */
671 static int rk2818_spi_transfer(struct spi_device *spi, struct spi_message *msg)
673 struct rk2818_spi *dws = spi_master_get_devdata(spi->master);
676 spin_lock_irqsave(&dws->lock, flags);
678 if (dws->run == QUEUE_STOPPED) {
679 spin_unlock_irqrestore(&dws->lock, flags);
683 msg->actual_length = 0;
684 msg->status = -EINPROGRESS;
685 msg->state = START_STATE;
687 list_add_tail(&msg->queue, &dws->queue);
689 if (dws->run == QUEUE_RUNNING && !dws->busy) {
691 if (dws->cur_transfer || dws->cur_msg)
692 queue_work(dws->workqueue,
693 &dws->pump_messages);
695 /* If no other data transaction in air, just go */
696 spin_unlock_irqrestore(&dws->lock, flags);
697 pump_messages(&dws->pump_messages);
702 spin_unlock_irqrestore(&dws->lock, flags);
707 /* This may be called twice for each spi dev */
708 static int rk2818_spi_setup(struct spi_device *spi)
710 struct rk2818_spi_chip *chip_info = NULL;
711 struct chip_data *chip;
713 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
716 /* Only alloc on first setup */
717 chip = spi_get_ctldata(spi);
719 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
723 chip->cs_control = spi_cs_control;
724 chip->enable_dma = 1; //0;
728 * Protocol drivers may change the chip settings, so...
729 * if chip_info exists, use it
731 chip_info = spi->controller_data;
733 /* chip_info doesn't always exist */
735 if (chip_info->cs_control)
736 chip->cs_control = chip_info->cs_control;
738 chip->poll_mode = chip_info->poll_mode;
739 chip->type = chip_info->type;
741 chip->rx_threshold = 0;
742 chip->tx_threshold = 0;
744 chip->enable_dma = chip_info->enable_dma;
747 if (spi->bits_per_word <= 8) {
750 chip->read = u8_reader;
751 chip->write = u8_writer;
752 } else if (spi->bits_per_word <= 16) {
755 chip->read = u16_reader;
756 chip->write = u16_writer;
758 /* Never take >16b case for MRST SPIC */
759 dev_err(&spi->dev, "invalid wordsize\n");
762 chip->bits_per_word = spi->bits_per_word;
764 if (!spi->max_speed_hz) {
765 dev_err(&spi->dev, "No max speed HZ parameter\n");
768 chip->speed_hz = spi->max_speed_hz;
770 chip->tmode = 0; /* Tx & Rx */
771 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
772 chip->cr0 = (chip->bits_per_word - 1)
773 | (chip->type << SPI_FRF_OFFSET)
774 | (spi->mode << SPI_MODE_OFFSET)
775 | (chip->tmode << SPI_TMOD_OFFSET);
777 spi_set_ctldata(spi, chip);
781 static void rk2818_spi_cleanup(struct spi_device *spi)
783 struct chip_data *chip = spi_get_ctldata(spi);
787 static int __devinit init_queue(struct rk2818_spi *dws)
789 INIT_LIST_HEAD(&dws->queue);
790 spin_lock_init(&dws->lock);
792 dws->run = QUEUE_STOPPED;
795 tasklet_init(&dws->pump_transfers,
796 pump_transfers, (unsigned long)dws);
798 INIT_WORK(&dws->pump_messages, pump_messages);
799 dws->workqueue = create_singlethread_workqueue(
800 dev_name(dws->master->dev.parent));
801 if (dws->workqueue == NULL)
807 static int start_queue(struct rk2818_spi *dws)
811 spin_lock_irqsave(&dws->lock, flags);
813 if (dws->run == QUEUE_RUNNING || dws->busy) {
814 spin_unlock_irqrestore(&dws->lock, flags);
818 dws->run = QUEUE_RUNNING;
820 dws->cur_transfer = NULL;
821 dws->cur_chip = NULL;
822 dws->prev_chip = NULL;
823 spin_unlock_irqrestore(&dws->lock, flags);
825 queue_work(dws->workqueue, &dws->pump_messages);
830 static int stop_queue(struct rk2818_spi *dws)
836 spin_lock_irqsave(&dws->lock, flags);
837 dws->run = QUEUE_STOPPED;
838 while (!list_empty(&dws->queue) && dws->busy && limit--) {
839 spin_unlock_irqrestore(&dws->lock, flags);
841 spin_lock_irqsave(&dws->lock, flags);
844 if (!list_empty(&dws->queue) || dws->busy)
846 spin_unlock_irqrestore(&dws->lock, flags);
851 static int destroy_queue(struct rk2818_spi *dws)
855 status = stop_queue(dws);
858 destroy_workqueue(dws->workqueue);
862 /* Restart the controller, disable all interrupts, clean rx fifo */
863 static void spi_hw_init(struct rk2818_spi *dws)
865 spi_enable_chip(dws, 0);
866 spi_mask_intr(dws, 0xff);
867 spi_enable_chip(dws, 1);
871 * Try to detect the FIFO depth if not set by interface driver,
872 * the depth could be from 2 to 32 from HW spec
874 if (!dws->fifo_len) {
876 for (fifo = 2; fifo <= 31; fifo++) {
877 rk2818_writew(dws, SPIM_TXFTLR, fifo);
878 if (fifo != rk2818_readw(dws, SPIM_TXFTLR))
882 dws->fifo_len = (fifo == 31) ? 0 : fifo;
883 rk2818_writew(dws, SPIM_TXFTLR, 0);
887 /* cpufreq driver support */
888 #ifdef CONFIG_CPU_FREQ
890 static int rk2818_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
892 struct rk2818_spi *info;
893 unsigned long newclk;
895 info = container_of(nb, struct rk2818_spi, freq_transition);
896 newclk = clk_get_rate(info->clock_spim);
901 static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info)
903 info->freq_transition.notifier_call = rk2818_spim_cpufreq_transition;
905 return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
908 static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info)
910 cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
914 static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info)
919 static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info)
923 static int __init rk2818_spim_probe(struct platform_device *pdev)
925 struct resource *regs;
926 struct rk2818_spi *dws;
927 struct spi_master *master;
930 struct rk2818_spi_platform_data *pdata = pdev->dev.platform_data;
931 struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;
933 if (pdata && pdata->io_init) {
938 for (i=0; i<pdata->num_chipselect; i++) {
939 ret = gpio_request(cs_gpios[i].cs_gpio, cs_gpios[i].name);
942 gpio_free(cs_gpios[j].cs_gpio);
943 printk("[fun:%s, line:%d], gpio request err\n", __func__, __LINE__);
944 if (pdata->io_deinit)
951 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
954 irq = platform_get_irq(pdev, 0);
957 /* setup spi core then atmel-specific driver state */
959 master = spi_alloc_master(&pdev->dev, sizeof *dws);
964 platform_set_drvdata(pdev, master);
965 dws = spi_master_get_devdata(master);
966 dws->clock_spim = clk_get(&pdev->dev, "spi");
967 clk_enable(dws->clock_spim);
968 if (IS_ERR(dws->clock_spim))
969 return PTR_ERR(dws->clock_spim);
970 dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
972 release_mem_region(regs->start, (regs->end - regs->start) + 1);
976 dws->master = master;
977 dws->type = SSI_MOTO_SPI;
978 dws->prev_chip = NULL;
979 dws->dma_inited = 1; ///0;
980 ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
981 ret = request_irq(dws->irq, rk2818_spi_irq, 0,
984 dev_err(&master->dev, "can not get IRQ\n");
985 goto err_free_master;
987 master->mode_bits = SPI_CPOL | SPI_CPHA;
988 master->bus_num = pdev->id;
989 master->num_chipselect = pdata->num_chipselect;
990 master->dev.platform_data = pdata;
991 master->cleanup = rk2818_spi_cleanup;
992 master->setup = rk2818_spi_setup;
993 master->transfer = rk2818_spi_transfer;
997 /* Initial and start queue */
998 ret = init_queue(dws);
1000 dev_err(&master->dev, "problem initializing queue\n");
1003 ret = start_queue(dws);
1005 dev_err(&master->dev, "problem starting queue\n");
1008 spi_master_set_devdata(master, dws);
1009 ret = spi_register_master(master);
1011 dev_err(&master->dev, "problem registering spi master\n");
1012 goto err_queue_alloc;
1015 ret =rk2818_spim_cpufreq_register(dws);
1017 printk(KERN_ERR"rk2818 spim failed to init cpufreq support\n");
1018 goto err_queue_alloc;
1020 printk(KERN_INFO "rk2818_spim: driver initialized\n");
1021 mrst_spi_debugfs_init(dws);
1027 spi_enable_chip(dws, 0);
1028 free_irq(dws->irq, dws);
1030 spi_master_put(master);
1036 static void __exit rk2818_spim_remove(struct platform_device *pdev)
1038 struct spi_master *master = platform_get_drvdata(pdev);
1039 struct rk2818_spi *dws = spi_master_get_devdata(master);
1044 rk2818_spim_cpufreq_deregister(dws);
1045 mrst_spi_debugfs_remove(dws);
1047 /* Remove the queue */
1048 status = destroy_queue(dws);
1050 dev_err(&dws->master->dev, "rk2818_spi_remove: workqueue will not "
1051 "complete, message memory not freed\n");
1052 clk_put(dws->clock_spim);
1053 clk_disable(dws->clock_spim);
1054 spi_enable_chip(dws, 0);
1056 spi_set_clk(dws, 0);
1057 free_irq(dws->irq, dws);
1059 /* Disconnect from the SPI framework */
1060 spi_unregister_master(dws->master);
1067 static int rk2818_spim_suspend(struct platform_device *pdev, pm_message_t mesg)
1069 struct spi_master *master = platform_get_drvdata(pdev);
1070 struct rk2818_spi *dws = spi_master_get_devdata(master);
1073 status = stop_queue(dws);
1076 clk_disable(dws->clock_spim);
1081 static int rk2818_spim_resume(struct platform_device *pdev)
1083 struct spi_master *master = platform_get_drvdata(pdev);
1084 struct rk2818_spi *dws = spi_master_get_devdata(master);
1087 clk_enable(dws->clock_spim);
1089 ret = start_queue(dws);
1091 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
1096 #define rk2818_spim_suspend NULL
1097 #define rk2818_spim_resume NULL
1100 static struct platform_driver rk2818_platform_spim_driver = {
1101 .remove = __exit_p(rk2818_spim_remove),
1103 .name = "rk2818_spim",
1104 .owner = THIS_MODULE,
1106 .suspend = rk2818_spim_suspend,
1107 .resume = rk2818_spim_resume,
1110 static int __init rk2818_spim_init(void)
1113 ret = platform_driver_probe(&rk2818_platform_spim_driver, rk2818_spim_probe);
1117 static void __exit rk2818_spim_exit(void)
1119 platform_driver_unregister(&rk2818_platform_spim_driver);
1122 subsys_initcall(rk2818_spim_init);
1123 module_exit(rk2818_spim_exit);
1125 MODULE_AUTHOR("lhh lhh@rock-chips.com");
1126 MODULE_DESCRIPTION("Rockchip RK2818 spim port driver");
1127 MODULE_LICENSE("GPL");;