drivers/spi/rk2818_spim.c

   1 /*drivers/serial/rk2818_spim.c - driver for rk2818 spim device
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/dma-mapping.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/highmem.h>
  18 #include <linux/delay.h>
  19 #include <linux/slab.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/cpufreq.h>
  23 #include <mach/gpio.h>
  24 #include <linux/dma-mapping.h>
  25 #include <asm/dma.h>
  26
  27 #include "rk2818_spim.h"
  28 #include <linux/spi/spi.h>
  29
  30 #ifdef CONFIG_DEBUG_FS
  31 #include <linux/debugfs.h>
  32 #endif
  33
  34 #define START_STATE     ((void *)0)
  35 #define RUNNING_STATE   ((void *)1)
  36 #define DONE_STATE      ((void *)2)
  37 #define ERROR_STATE     ((void *)-1)
  38
  39 #define QUEUE_RUNNING   0
  40 #define QUEUE_STOPPED   1
  41
  42 #define MRST_SPI_DEASSERT       0
  43 #define MRST_SPI_ASSERT         1  ///CS0
  44 #define MRST_SPI_ASSERT1        2  ///CS1
  45
  46 /* Slave spi_dev related */
  47 struct chip_data {
  48         u16 cr0;
  49         u8 cs;                  /* chip select pin */
  50         u8 n_bytes;             /* current is a 1/2/4 byte op */
  51         u8 tmode;               /* TR/TO/RO/EEPROM */
  52         u8 type;                /* SPI/SSP/MicroWire */
  53
  54         u8 poll_mode;           /* 1 means use poll mode */
  55
  56         u32 dma_width;
  57         u32 rx_threshold;
  58         u32 tx_threshold;
  59         u8 enable_dma;
  60         u8 bits_per_word;
  61         u16 clk_div;            /* baud rate divider */
  62         u32 speed_hz;           /* baud rate */
  63         int (*write)(struct rk2818_spi *dws);
  64         int (*read)(struct rk2818_spi *dws);
  65         void (*cs_control)(u32 command);
  66 };
  67
  68 #ifdef CONFIG_DEBUG_FS
  69 static int spi_show_regs_open(struct inode *inode, struct file *file)
  70 {
  71         file->private_data = inode->i_private;
  72         return 0;
  73 }
  74
  75 #define SPI_REGS_BUFSIZE        1024
  76 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  77                                 size_t count, loff_t *ppos)
  78 {
  79         struct rk2818_spi *dws;
  80         char *buf;
  81         u32 len = 0;
  82         ssize_t ret;
  83
  84         dws = file->private_data;
  85
  86         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  87         if (!buf)
  88                 return 0;
  89
  90         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "MRST SPI0 registers:\n");
  92         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "=================================\n");
  94         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "CTRL0: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR0));
  96         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "CTRL1: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR1));
  98         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "SSIENR: \t0x%08x\n", rk2818_readl(dws, SPIM_SPIENR));
 100         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "SER: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SER));
 102         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "BAUDR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_BAUDR));
 104         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "TXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_TXFTLR));
 106         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "RXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_RXFTLR));
 108         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "TXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_TXFLR));
 110         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "RXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_RXFLR));
 112         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "SR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SR));
 114         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 115                         "IMR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_IMR));
 116         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 117                         "ISR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_ISR));
 118         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 119                         "DMACR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_DMACR));
 120         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 121                         "DMATDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMATDLR));
 122         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 123                         "DMARDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMARDLR));
 124         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 125                         "=================================\n");
 126
 127         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 128         kfree(buf);
 129         return ret;
 130 }
 131
 132 static const struct file_operations mrst_spi_regs_ops = {
 133         .owner          = THIS_MODULE,
 134         .open           = spi_show_regs_open,
 135         .read           = spi_show_regs,
 136 };
 137
 138 static int mrst_spi_debugfs_init(struct rk2818_spi *dws)
 139 {
 140         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 141         if (!dws->debugfs)
 142                 return -ENOMEM;
 143
 144         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 145                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 146         return 0;
 147 }
 148
 149 static void mrst_spi_debugfs_remove(struct rk2818_spi *dws)
 150 {
 151         if (dws->debugfs)
 152                 debugfs_remove_recursive(dws->debugfs);
 153 }
 154
 155 #else
 156 static inline int mrst_spi_debugfs_init(struct rk2818_spi *dws)
 157 {
 158         return 0;
 159 }
 160
 161 static inline void mrst_spi_debugfs_remove(struct rk2818_spi *dws)
 162 {
 163 }
 164 #endif /* CONFIG_DEBUG_FS */
 165
 166 static void wait_till_not_busy(struct rk2818_spi *dws)
 167 {
 168         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
 169
 170         while (time_before(jiffies, end)) {
 171                 if (!(rk2818_readw(dws, SPIM_SR) & SR_BUSY))
 172                         return;
 173         }
 174         dev_err(&dws->master->dev,
 175                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
 176 }
 177
 178 static void flush(struct rk2818_spi *dws)
 179 {
 180         while (rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 181                 rk2818_readw(dws, SPIM_DR0);
 182
 183         wait_till_not_busy(dws);
 184 }
 185
 186 static void null_cs_control(u32 command)
 187 {
 188     //printk("null_cs_control [%d]\n", command);
 189         if(command == 2)
 190                 gpio_direction_output(RK2818_PIN_PB0,GPIO_LOW);
 191         else if(command == 1)
 192                 gpio_direction_output(RK2818_PIN_PB4,GPIO_LOW);
 193         else{
 194                 gpio_direction_output(RK2818_PIN_PB0,GPIO_HIGH);
 195                 gpio_direction_output(RK2818_PIN_PB4,GPIO_HIGH);
 196         }
 197 }
 198
 199 static int null_writer(struct rk2818_spi *dws)
 200 {
 201         u8 n_bytes = dws->n_bytes;
 202
 203         if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
 204                 || (dws->tx == dws->tx_end))
 205                 return 0;
 206         rk2818_writew(dws, SPIM_DR0, 0);
 207         dws->tx += n_bytes;
 208
 209         wait_till_not_busy(dws);
 210         return 1;
 211 }
 212
 213 static int null_reader(struct rk2818_spi *dws)
 214 {
 215         u8 n_bytes = dws->n_bytes;
 216         while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 217                 && (dws->rx < dws->rx_end)) {
 218                 rk2818_readw(dws, SPIM_DR0);
 219                 dws->rx += n_bytes;
 220         }
 221         wait_till_not_busy(dws);
 222         return dws->rx == dws->rx_end;
 223 }
 224
 225 static int u8_writer(struct rk2818_spi *dws)
 226 {
 227         if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
 228                 || (dws->tx == dws->tx_end))
 229                 return 0;
 230         rk2818_writew(dws, SPIM_DR0, *(u8 *)(dws->tx));
 231         ++dws->tx;
 232
 233         wait_till_not_busy(dws);
 234         return 1;
 235 }
 236
 237 static int u8_reader(struct rk2818_spi *dws)
 238 {
 239         while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 240                 && (dws->rx < dws->rx_end)) {
 241                 *(u8 *)(dws->rx) = rk2818_readw(dws, SPIM_DR0);
 242                 ++dws->rx;
 243         }
 244
 245         wait_till_not_busy(dws);
 246         return dws->rx == dws->rx_end;
 247 }
 248
 249 static int u16_writer(struct rk2818_spi *dws)
 250 {
 251         if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
 252                 || (dws->tx == dws->tx_end))
 253                 return 0;
 254
 255         rk2818_writew(dws, SPIM_DR0, *(u16 *)(dws->tx));
 256         dws->tx += 2;
 257
 258         wait_till_not_busy(dws);
 259         return 1;
 260 }
 261
 262 static int u16_reader(struct rk2818_spi *dws)
 263 {
 264         u16 temp;
 265
 266         while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 267                 && (dws->rx < dws->rx_end)) {
 268                 temp = rk2818_readw(dws, SPIM_DR0);
 269                 *(u16 *)(dws->rx) = temp;
 270                 dws->rx += 2;
 271         }
 272
 273         wait_till_not_busy(dws);
 274         return dws->rx == dws->rx_end;
 275 }
 276
 277 static void *next_transfer(struct rk2818_spi *dws)
 278 {
 279         struct spi_message *msg = dws->cur_msg;
 280         struct spi_transfer *trans = dws->cur_transfer;
 281
 282         /* Move to next transfer */
 283         if (trans->transfer_list.next != &msg->transfers) {
 284                 dws->cur_transfer =
 285                         list_entry(trans->transfer_list.next,
 286                                         struct spi_transfer,
 287                                         transfer_list);
 288                 return RUNNING_STATE;
 289         } else
 290                 return DONE_STATE;
 291 }
 292
 293 /*
 294  * Note: first step is the protocol driver prepares
 295  * a dma-capable memory, and this func just need translate
 296  * the virt addr to physical
 297  */
 298 static int map_dma_buffers(struct rk2818_spi *dws)
 299 {
 300         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
 301                 || !dws->cur_chip->enable_dma)
 302                 return 0;
 303
 304         if (dws->cur_transfer->tx_dma)
 305                 dws->tx_dma = dws->cur_transfer->tx_dma;
 306
 307         if (dws->cur_transfer->rx_dma)
 308                 dws->rx_dma = dws->cur_transfer->rx_dma;
 309
 310         return 1;
 311 }
 312
 313 /* Caller already set message->status; dma and pio irqs are blocked */
 314 static void giveback(struct rk2818_spi *dws)
 315 {
 316         struct spi_transfer *last_transfer;
 317         unsigned long flags;
 318         struct spi_message *msg;
 319
 320         spin_lock_irqsave(&dws->lock, flags);
 321         msg = dws->cur_msg;
 322         dws->cur_msg = NULL;
 323         dws->cur_transfer = NULL;
 324         dws->prev_chip = dws->cur_chip;
 325         dws->cur_chip = NULL;
 326         dws->dma_mapped = 0;
 327         queue_work(dws->workqueue, &dws->pump_messages);
 328         spin_unlock_irqrestore(&dws->lock, flags);
 329
 330         last_transfer = list_entry(msg->transfers.prev,
 331                                         struct spi_transfer,
 332                                         transfer_list);
 333
 334         if (!last_transfer->cs_change)
 335                 dws->cs_control(MRST_SPI_DEASSERT);
 336
 337         msg->state = NULL;
 338         if (msg->complete)
 339                 msg->complete(msg->context);
 340 }
 341
 342 static void int_error_stop(struct rk2818_spi *dws, const char *msg)
 343 {
 344         /* Stop and reset hw */
 345         flush(dws);
 346         spi_enable_chip(dws, 0);
 347
 348         dev_err(&dws->master->dev, "%s\n", msg);
 349         dws->cur_msg->state = ERROR_STATE;
 350         tasklet_schedule(&dws->pump_transfers);
 351 }
 352
 353 static void transfer_complete(struct rk2818_spi *dws)
 354 {
 355         /* Update total byte transfered return count actual bytes read */
 356         dws->cur_msg->actual_length += dws->len;
 357
 358         /* Move to next transfer */
 359         dws->cur_msg->state = next_transfer(dws);
 360
 361         /* Handle end of message */
 362         if (dws->cur_msg->state == DONE_STATE) {
 363                 dws->cur_msg->status = 0;
 364                 giveback(dws);
 365         } else
 366                 tasklet_schedule(&dws->pump_transfers);
 367 }
 368
 369 static irqreturn_t interrupt_transfer(struct rk2818_spi *dws)
 370 {
 371         u16 irq_status, irq_mask = 0x3f;
 372         u32 int_level = dws->fifo_len / 2;
 373         u32 left;
 374
 375         irq_status = rk2818_readw(dws, SPIM_ISR) & irq_mask;
 376         /* Error handling */
 377         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 378                 rk2818_readw(dws, SPIM_TXOICR);
 379                 rk2818_readw(dws, SPIM_RXOICR);
 380                 rk2818_readw(dws, SPIM_RXUICR);
 381                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 382                 return IRQ_HANDLED;
 383         }
 384
 385         if (irq_status & SPI_INT_TXEI) {
 386                 spi_mask_intr(dws, SPI_INT_TXEI);
 387
 388                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 389                 left = (left > int_level) ? int_level : left;
 390
 391                 while (left--)
 392                         dws->write(dws);
 393                 dws->read(dws);
 394
 395                 /* Re-enable the IRQ if there is still data left to tx */
 396                 if (dws->tx_end > dws->tx)
 397                         spi_umask_intr(dws, SPI_INT_TXEI);
 398                 else
 399                         transfer_complete(dws);
 400         }
 401
 402         return IRQ_HANDLED;
 403 }
 404
 405 static irqreturn_t rk2818_spi_irq(int irq, void *dev_id)
 406 {
 407         struct rk2818_spi *dws = dev_id;
 408
 409         if (!dws->cur_msg) {
 410                 spi_mask_intr(dws, SPI_INT_TXEI);
 411                 /* Never fail */
 412                 return IRQ_HANDLED;
 413         }
 414
 415         return dws->transfer_handler(dws);
 416 }
 417
 418 /* Must be called inside pump_transfers() */
 419 static void poll_transfer(struct rk2818_spi *dws)
 420 {
 421         while (dws->write(dws))
 422                 dws->read(dws);
 423
 424         transfer_complete(dws);
 425 }
 426
 427 static void dma_transfer(struct rk2818_spi *dws, struct spi_transfer *xfer) //int cs_change)
 428 {
 429
 430 }
 431
 432 static void spi_chip_sel(struct rk2818_spi *dws, u16 cs)
 433 {
 434     if(cs >= dws->master->num_chipselect)
 435                 return;
 436
 437         if (dws->cs_control){
 438             dws->cs_control(cs+1);
 439         }
 440         //rk2818_writel(dws, SPIM_SER, 1 << cs);
 441         rk2818_writel(dws, SPIM_SER, 1 << 0);
 442 }
 443
 444 static void pump_transfers(unsigned long data)
 445 {
 446         struct rk2818_spi *dws = (struct rk2818_spi *)data;
 447         struct spi_message *message = NULL;
 448         struct spi_transfer *transfer = NULL;
 449         struct spi_transfer *previous = NULL;
 450         struct spi_device *spi = NULL;
 451         struct chip_data *chip = NULL;
 452         u8 bits = 0;
 453         u8 imask = 0;
 454         u8 cs_change = 0;
 455         u16 txint_level = 0;
 456         u16 clk_div = 0;
 457         u32 speed = 0;
 458         u32 cr0 = 0;
 459
 460         /* Get current state information */
 461         message = dws->cur_msg;
 462         transfer = dws->cur_transfer;
 463         chip = dws->cur_chip;
 464         spi = message->spi;
 465         if (unlikely(!chip->clk_div))
 466                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
 467         if (message->state == ERROR_STATE) {
 468                 message->status = -EIO;
 469                 goto early_exit;
 470         }
 471
 472         /* Handle end of message */
 473         if (message->state == DONE_STATE) {
 474                 message->status = 0;
 475                 goto early_exit;
 476         }
 477
 478         /* Delay if requested at end of transfer*/
 479         if (message->state == RUNNING_STATE) {
 480                 previous = list_entry(transfer->transfer_list.prev,
 481                                         struct spi_transfer,
 482                                         transfer_list);
 483                 if (previous->delay_usecs)
 484                         udelay(previous->delay_usecs);
 485         }
 486
 487         dws->n_bytes = chip->n_bytes;
 488         dws->dma_width = chip->dma_width;
 489         dws->cs_control = chip->cs_control;
 490
 491         dws->rx_dma = transfer->rx_dma;
 492         dws->tx_dma = transfer->tx_dma;
 493         dws->tx = (void *)transfer->tx_buf;
 494         dws->tx_end = dws->tx + transfer->len;
 495         dws->rx = transfer->rx_buf;
 496         dws->rx_end = dws->rx + transfer->len;
 497         dws->write = dws->tx ? chip->write : null_writer;
 498         dws->read = dws->rx ? chip->read : null_reader;
 499         dws->cs_change = transfer->cs_change;
 500         dws->len = dws->cur_transfer->len;
 501         if (chip != dws->prev_chip)
 502                 cs_change = 1;
 503
 504         cr0 = chip->cr0;
 505
 506         /* Handle per transfer options for bpw and speed */
 507         if (transfer->speed_hz) {
 508                 speed = chip->speed_hz;
 509
 510                 if (transfer->speed_hz != speed) {
 511                         speed = transfer->speed_hz;
 512                         if (speed > clk_get_rate(dws->clock_spim)) {
 513                                 printk(KERN_ERR "MRST SPI0: unsupported"
 514                                         "freq: %dHz\n", speed);
 515                                 message->status = -EIO;
 516                                 goto early_exit;
 517                         }
 518
 519                         /* clk_div doesn't support odd number */
 520                         clk_div = clk_get_rate(dws->clock_spim) / speed;
 521                         clk_div = (clk_div + 1) & 0xfffe;
 522
 523                         chip->speed_hz = speed;
 524                         chip->clk_div = clk_div;
 525                 }
 526         }
 527         if (transfer->bits_per_word) {
 528                 bits = transfer->bits_per_word;
 529
 530                 switch (bits) {
 531                 case 8:
 532                         dws->n_bytes = 1;
 533                         dws->dma_width = 1;
 534                         dws->read = (dws->read != null_reader) ?
 535                                         u8_reader : null_reader;
 536                         dws->write = (dws->write != null_writer) ?
 537                                         u8_writer : null_writer;
 538                         break;
 539                 case 16:
 540                         dws->n_bytes = 2;
 541                         dws->dma_width = 2;
 542                         dws->read = (dws->read != null_reader) ?
 543                                         u16_reader : null_reader;
 544                         dws->write = (dws->write != null_writer) ?
 545                                         u16_writer : null_writer;
 546                         break;
 547                 default:
 548                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 549                                 "%db\n", bits);
 550                         message->status = -EIO;
 551                         goto early_exit;
 552                 }
 553
 554                 cr0 = (bits - 1)
 555                         | (chip->type << SPI_FRF_OFFSET)
 556                         | (spi->mode << SPI_MODE_OFFSET)
 557                         | (chip->tmode << SPI_TMOD_OFFSET);
 558         }
 559         message->state = RUNNING_STATE;
 560
 561         /*
 562          * Adjust transfer mode if necessary. Requires platform dependent
 563          * chipselect mechanism.
 564          */
 565         if (dws->cs_control) {
 566                 if (dws->rx && dws->tx)
 567                         chip->tmode = 0x00;
 568                 else if (dws->rx)
 569                         chip->tmode = 0x02;
 570                 else
 571                         chip->tmode = 0x01;
 572
 573                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
 574                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 575         }
 576         /* Check if current transfer is a DMA transaction */
 577         dws->dma_mapped = map_dma_buffers(dws);
 578
 579         /*
 580          * Interrupt mode
 581          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 582          */
 583         if (!dws->dma_mapped && !chip->poll_mode) {
 584                 int templen = dws->len / dws->n_bytes;
 585                 txint_level = dws->fifo_len / 2;
 586                 txint_level = (templen > txint_level) ? txint_level : templen;
 587
 588                 imask |= SPI_INT_TXEI;
 589                 dws->transfer_handler = interrupt_transfer;
 590         }
 591
 592         /*
 593          * Reprogram registers only if
 594          *      1. chip select changes
 595          *      2. clk_div is changed
 596          *      3. control value changes
 597          */
 598         if (rk2818_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {
 599                 spi_enable_chip(dws, 0);
 600                 if (rk2818_readw(dws, SPIM_CTRLR0) != cr0)
 601                         rk2818_writew(dws, SPIM_CTRLR0, cr0);
 602
 603                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 604                 spi_chip_sel(dws, spi->chip_select);
 605                 /* Set the interrupt mask, for poll mode just diable all int */
 606                 spi_mask_intr(dws, 0xff);
 607                 if (imask)
 608                         spi_umask_intr(dws, imask);
 609                 if (txint_level)
 610                         rk2818_writew(dws, SPIM_TXFTLR, txint_level);
 611
 612                 spi_enable_chip(dws, 1);
 613                 if (cs_change)
 614                         dws->prev_chip = chip;
 615         }
 616
 617         if (dws->dma_mapped)
 618                 dma_transfer(dws, transfer); ///cs_change);
 619
 620         if (chip->poll_mode)
 621                 poll_transfer(dws);
 622
 623         return;
 624
 625 early_exit:
 626         giveback(dws);
 627         return;
 628 }
 629
 630 static void pump_messages(struct work_struct *work)
 631 {
 632         struct rk2818_spi *dws =
 633                 container_of(work, struct rk2818_spi, pump_messages);
 634         unsigned long flags;
 635
 636         /* Lock queue and check for queue work */
 637         spin_lock_irqsave(&dws->lock, flags);
 638         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 639                 dws->busy = 0;
 640                 spin_unlock_irqrestore(&dws->lock, flags);
 641                 return;
 642         }
 643
 644         /* Make sure we are not already running a message */
 645         if (dws->cur_msg) {
 646                 spin_unlock_irqrestore(&dws->lock, flags);
 647                 return;
 648         }
 649
 650         /* Extract head of queue */
 651         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 652         list_del_init(&dws->cur_msg->queue);
 653
 654         /* Initial message state*/
 655         dws->cur_msg->state = START_STATE;
 656         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 657                                                 struct spi_transfer,
 658                                                 transfer_list);
 659         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 660     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj
 661
 662         /* Mark as busy and launch transfers */
 663         tasklet_schedule(&dws->pump_transfers);
 664
 665         dws->busy = 1;
 666         spin_unlock_irqrestore(&dws->lock, flags);
 667 }
 668
 669 /* spi_device use this to queue in their spi_msg */
 670 static int rk2818_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 671 {
 672         struct rk2818_spi *dws = spi_master_get_devdata(spi->master);
 673         unsigned long flags;
 674
 675         spin_lock_irqsave(&dws->lock, flags);
 676
 677         if (dws->run == QUEUE_STOPPED) {
 678                 spin_unlock_irqrestore(&dws->lock, flags);
 679                 return -ESHUTDOWN;
 680         }
 681
 682         msg->actual_length = 0;
 683         msg->status = -EINPROGRESS;
 684         msg->state = START_STATE;
 685
 686         list_add_tail(&msg->queue, &dws->queue);
 687
 688         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 689
 690                 if (dws->cur_transfer || dws->cur_msg)
 691                         queue_work(dws->workqueue,
 692                                         &dws->pump_messages);
 693                 else {
 694                         /* If no other data transaction in air, just go */
 695                         spin_unlock_irqrestore(&dws->lock, flags);
 696                         pump_messages(&dws->pump_messages);
 697                         return 0;
 698                 }
 699         }
 700
 701         spin_unlock_irqrestore(&dws->lock, flags);
 702
 703         return 0;
 704 }
 705
 706 /* This may be called twice for each spi dev */
 707 static int rk2818_spi_setup(struct spi_device *spi)
 708 {
 709         struct rk2818_spi_chip *chip_info = NULL;
 710         struct chip_data *chip;
 711
 712         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 713                 return -EINVAL;
 714
 715         /* Only alloc on first setup */
 716         chip = spi_get_ctldata(spi);
 717         if (!chip) {
 718                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 719                 if (!chip)
 720                         return -ENOMEM;
 721
 722                 chip->cs_control = null_cs_control;
 723                 chip->enable_dma = 1;  //0;
 724         }
 725
 726         /*
 727          * Protocol drivers may change the chip settings, so...
 728          * if chip_info exists, use it
 729          */
 730         chip_info = spi->controller_data;
 731
 732         /* chip_info doesn't always exist */
 733         if (chip_info) {
 734                 if (chip_info->cs_control)
 735                         chip->cs_control = chip_info->cs_control;
 736
 737                 chip->poll_mode = chip_info->poll_mode;
 738                 chip->type = chip_info->type;
 739
 740                 chip->rx_threshold = 0;
 741                 chip->tx_threshold = 0;
 742
 743                 chip->enable_dma = chip_info->enable_dma;
 744         }
 745
 746         if (spi->bits_per_word <= 8) {
 747                 chip->n_bytes = 1;
 748                 chip->dma_width = 1;
 749                 chip->read = u8_reader;
 750                 chip->write = u8_writer;
 751         } else if (spi->bits_per_word <= 16) {
 752                 chip->n_bytes = 2;
 753                 chip->dma_width = 2;
 754                 chip->read = u16_reader;
 755                 chip->write = u16_writer;
 756         } else {
 757                 /* Never take >16b case for MRST SPIC */
 758                 dev_err(&spi->dev, "invalid wordsize\n");
 759                 return -EINVAL;
 760         }
 761         chip->bits_per_word = spi->bits_per_word;
 762
 763         if (!spi->max_speed_hz) {
 764                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 765                 return -EINVAL;
 766         }
 767         chip->speed_hz = spi->max_speed_hz;
 768
 769         chip->tmode = 0; /* Tx & Rx */
 770         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 771         chip->cr0 = (chip->bits_per_word - 1)
 772                         | (chip->type << SPI_FRF_OFFSET)
 773                         | (spi->mode  << SPI_MODE_OFFSET)
 774                         | (chip->tmode << SPI_TMOD_OFFSET);
 775
 776         spi_set_ctldata(spi, chip);
 777         return 0;
 778 }
 779
 780 static void rk2818_spi_cleanup(struct spi_device *spi)
 781 {
 782         struct chip_data *chip = spi_get_ctldata(spi);
 783         kfree(chip);
 784 }
 785
 786 static int __devinit init_queue(struct rk2818_spi *dws)
 787 {
 788         INIT_LIST_HEAD(&dws->queue);
 789         spin_lock_init(&dws->lock);
 790
 791         dws->run = QUEUE_STOPPED;
 792         dws->busy = 0;
 793
 794         tasklet_init(&dws->pump_transfers,
 795                         pump_transfers, (unsigned long)dws);
 796
 797         INIT_WORK(&dws->pump_messages, pump_messages);
 798         dws->workqueue = create_singlethread_workqueue(
 799                                         dev_name(dws->master->dev.parent));
 800         if (dws->workqueue == NULL)
 801                 return -EBUSY;
 802
 803         return 0;
 804 }
 805
 806 static int start_queue(struct rk2818_spi *dws)
 807 {
 808         unsigned long flags;
 809
 810         spin_lock_irqsave(&dws->lock, flags);
 811
 812         if (dws->run == QUEUE_RUNNING || dws->busy) {
 813                 spin_unlock_irqrestore(&dws->lock, flags);
 814                 return -EBUSY;
 815         }
 816
 817         dws->run = QUEUE_RUNNING;
 818         dws->cur_msg = NULL;
 819         dws->cur_transfer = NULL;
 820         dws->cur_chip = NULL;
 821         dws->prev_chip = NULL;
 822         spin_unlock_irqrestore(&dws->lock, flags);
 823
 824         queue_work(dws->workqueue, &dws->pump_messages);
 825
 826         return 0;
 827 }
 828
 829 static int stop_queue(struct rk2818_spi *dws)
 830 {
 831         unsigned long flags;
 832         unsigned limit = 50;
 833         int status = 0;
 834
 835         spin_lock_irqsave(&dws->lock, flags);
 836         dws->run = QUEUE_STOPPED;
 837         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 838                 spin_unlock_irqrestore(&dws->lock, flags);
 839                 msleep(10);
 840                 spin_lock_irqsave(&dws->lock, flags);
 841         }
 842
 843         if (!list_empty(&dws->queue) || dws->busy)
 844                 status = -EBUSY;
 845         spin_unlock_irqrestore(&dws->lock, flags);
 846
 847         return status;
 848 }
 849
 850 static int destroy_queue(struct rk2818_spi *dws)
 851 {
 852         int status;
 853
 854         status = stop_queue(dws);
 855         if (status != 0)
 856                 return status;
 857         destroy_workqueue(dws->workqueue);
 858         return 0;
 859 }
 860
 861 /* Restart the controller, disable all interrupts, clean rx fifo */
 862 static void spi_hw_init(struct rk2818_spi *dws)
 863 {
 864         spi_enable_chip(dws, 0);
 865         spi_mask_intr(dws, 0xff);
 866         spi_enable_chip(dws, 1);
 867         flush(dws);
 868
 869         /*
 870          * Try to detect the FIFO depth if not set by interface driver,
 871          * the depth could be from 2 to 32 from HW spec
 872          */
 873         if (!dws->fifo_len) {
 874                 u32 fifo;
 875                 for (fifo = 2; fifo <= 31; fifo++) {
 876                         rk2818_writew(dws, SPIM_TXFTLR, fifo);
 877                         if (fifo != rk2818_readw(dws, SPIM_TXFTLR))
 878                                 break;
 879                 }
 880
 881                 dws->fifo_len = (fifo == 31) ? 0 : fifo;
 882                 rk2818_writew(dws, SPIM_TXFTLR, 0);
 883         }
 884 }
 885
 886 /* cpufreq driver support */
 887 #ifdef CONFIG_CPU_FREQ
 888
 889 static int rk2818_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
 890 {
 891         struct rk2818_spi *info;
 892         unsigned long newclk;
 893
 894         info = container_of(nb, struct rk2818_spi, freq_transition);
 895         newclk = clk_get_rate(info->clock_spim);
 896
 897         return 0;
 898 }
 899
 900 static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info)
 901 {
 902         info->freq_transition.notifier_call = rk2818_spim_cpufreq_transition;
 903
 904         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 905 }
 906
 907 static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info)
 908 {
 909         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 910 }
 911
 912 #else
 913 static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info)
 914 {
 915         return 0;
 916 }
 917
 918 static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info)
 919 {
 920 }
 921 #endif
 922 static int __init rk2818_spim_probe(struct platform_device *pdev)
 923 {
 924         struct resource         *regs;
 925         struct rk2818_spi   *dws;
 926         struct spi_master   *master;
 927         int                     irq;
 928         int         ret;
 929
 930         gpio_request(RK2818_PIN_PB0, "rk2818_spim");
 931         gpio_request(RK2818_PIN_PB4, "rk2818_spim");
 932         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 933         if (!regs)
 934                 return -ENXIO;
 935         irq = platform_get_irq(pdev, 0);
 936         if (irq < 0)
 937                 return irq;
 938         /* setup spi core then atmel-specific driver state */
 939         ret = -ENOMEM;
 940         master = spi_alloc_master(&pdev->dev, sizeof *dws);
 941         if (!master) {
 942                 ret = -ENOMEM;
 943                 goto exit;
 944         }
 945         platform_set_drvdata(pdev, master);
 946         dws = spi_master_get_devdata(master);
 947         dws->clock_spim = clk_get(&pdev->dev, "spi");
 948         clk_enable(dws->clock_spim);
 949         if (IS_ERR(dws->clock_spim))
 950                 return PTR_ERR(dws->clock_spim);
 951         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 952         if (!dws->regs){
 953         release_mem_region(regs->start, (regs->end - regs->start) + 1);
 954                 return -EBUSY;
 955         }
 956     dws->irq = irq;
 957         dws->master = master;
 958         dws->type = SSI_MOTO_SPI;
 959         dws->prev_chip = NULL;
 960         dws->dma_inited = 1;  ///0;
 961         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 962         ret = request_irq(dws->irq, rk2818_spi_irq, 0,
 963                         "rk2818_spim", dws);
 964         if (ret < 0) {
 965                 dev_err(&master->dev, "can not get IRQ\n");
 966                 goto err_free_master;
 967         }
 968         master->mode_bits = SPI_CPOL | SPI_CPHA;
 969         master->bus_num = pdev->id;
 970 #if defined(CONFIG_MACH_RAHO)
 971         master->num_chipselect = 3; //raho ´ó°åÐèÒªÖ§³Ö3¸öÆ¬Ñ¡ dxj
 972 #else
 973     master->num_chipselect = 2;
 974 #endif
 975         master->cleanup = rk2818_spi_cleanup;
 976         master->setup = rk2818_spi_setup;
 977         master->transfer = rk2818_spi_transfer;
 978         dws->pdev = pdev;
 979         /* Basic HW init */
 980         spi_hw_init(dws);
 981         /* Initial and start queue */
 982         ret = init_queue(dws);
 983         if (ret) {
 984                 dev_err(&master->dev, "problem initializing queue\n");
 985                 goto err_diable_hw;
 986         }
 987         ret = start_queue(dws);
 988         if (ret) {
 989                 dev_err(&master->dev, "problem starting queue\n");
 990                 goto err_diable_hw;
 991         }
 992         spi_master_set_devdata(master, dws);
 993         ret = spi_register_master(master);
 994         if (ret) {
 995                 dev_err(&master->dev, "problem registering spi master\n");
 996                 goto err_queue_alloc;
 997         }
 998
 999         ret =rk2818_spim_cpufreq_register(dws);
1000         if (ret < 0) {
1001                 printk(KERN_ERR"rk2818 spim failed to init cpufreq support\n");
1002                 goto err_queue_alloc;
1003         }
1004         printk(KERN_INFO "rk2818_spim: driver initialized\n");
1005         mrst_spi_debugfs_init(dws);
1006         return 0;
1007
1008 err_queue_alloc:
1009         destroy_queue(dws);
1010 err_diable_hw:
1011         spi_enable_chip(dws, 0);
1012         free_irq(dws->irq, dws);
1013 err_free_master:
1014         spi_master_put(master);
1015         iounmap(dws->regs);
1016 exit:
1017         return ret;
1018 }
1019
1020 static void __exit rk2818_spim_remove(struct platform_device *pdev)
1021 {
1022         struct spi_master *master = platform_get_drvdata(pdev);
1023         struct rk2818_spi *dws = spi_master_get_devdata(master);
1024         int status = 0;
1025
1026         if (!dws)
1027                 return;
1028         rk2818_spim_cpufreq_deregister(dws);
1029         mrst_spi_debugfs_remove(dws);
1030
1031         /* Remove the queue */
1032         status = destroy_queue(dws);
1033         if (status != 0)
1034                 dev_err(&dws->master->dev, "rk2818_spi_remove: workqueue will not "
1035                         "complete, message memory not freed\n");
1036         clk_put(dws->clock_spim);
1037         clk_disable(dws->clock_spim);
1038         spi_enable_chip(dws, 0);
1039         /* Disable clk */
1040         spi_set_clk(dws, 0);
1041         free_irq(dws->irq, dws);
1042
1043         /* Disconnect from the SPI framework */
1044         spi_unregister_master(dws->master);
1045         iounmap(dws->regs);
1046 }
1047
1048
1049 #ifdef  CONFIG_PM
1050
1051 static int rk2818_spim_suspend(struct platform_device *pdev, pm_message_t mesg)
1052 {
1053         struct spi_master *master = platform_get_drvdata(pdev);
1054         struct rk2818_spi *dws = spi_master_get_devdata(master);
1055         int status;
1056
1057         status = stop_queue(dws);
1058         if (status != 0)
1059                 return status;
1060         clk_disable(dws->clock_spim);
1061
1062         return 0;
1063 }
1064
1065 static int rk2818_spim_resume(struct platform_device *pdev)
1066 {
1067         struct spi_master *master = platform_get_drvdata(pdev);
1068         struct rk2818_spi *dws = spi_master_get_devdata(master);
1069         int ret;
1070
1071         clk_enable(dws->clock_spim);
1072         spi_hw_init(dws);
1073         ret = start_queue(dws);
1074         if (ret)
1075                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
1076         return ret;
1077 }
1078
1079 #else
1080 #define rk2818_spim_suspend     NULL
1081 #define rk2818_spim_resume      NULL
1082 #endif
1083
1084 static struct platform_driver rk2818_platform_spim_driver = {
1085         .remove         = __exit_p(rk2818_spim_remove),
1086         .driver         = {
1087                 .name   = "rk2818_spim",
1088                 .owner  = THIS_MODULE,
1089         },
1090         .suspend        = rk2818_spim_suspend,
1091         .resume         = rk2818_spim_resume,
1092 };
1093
1094 static int __init rk2818_spim_init(void)
1095 {
1096         int ret;
1097         ret = platform_driver_probe(&rk2818_platform_spim_driver, rk2818_spim_probe);
1098         return ret;
1099 }
1100
1101 static void __exit rk2818_spim_exit(void)
1102 {
1103         platform_driver_unregister(&rk2818_platform_spim_driver);
1104 }
1105
1106 subsys_initcall(rk2818_spim_init);
1107 module_exit(rk2818_spim_exit);
1108
1109 MODULE_AUTHOR("lhh lhh@rock-chips.com");
1110 MODULE_DESCRIPTION("Rockchip RK2818 spim port driver");
1111 MODULE_LICENSE("GPL");;