drivers/spi/rk2818_spim.c

   1 /*drivers/serial/rk2818_spim.c - driver for rk2818 spim device
   2  *
   3  * Copyright (C) 2010 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/dma-mapping.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/highmem.h>
  18 #include <linux/delay.h>
  19 #include <linux/slab.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/cpufreq.h>
  23 #include <mach/gpio.h>
  24 #include <linux/dma-mapping.h>
  25 #include <asm/dma.h>
  26
  27 #include "rk2818_spim.h"
  28 #include <linux/spi/spi.h>
  29 #include <mach/board.h>
  30
  31 #ifdef CONFIG_DEBUG_FS
  32 #include <linux/debugfs.h>
  33 #endif
  34
  35 #define START_STATE     ((void *)0)
  36 #define RUNNING_STATE   ((void *)1)
  37 #define DONE_STATE      ((void *)2)
  38 #define ERROR_STATE     ((void *)-1)
  39
  40 #define QUEUE_RUNNING   0
  41 #define QUEUE_STOPPED   1
  42
  43 #define MRST_SPI_DEASSERT       0
  44 #define MRST_SPI_ASSERT         1  ///CS0
  45 #define MRST_SPI_ASSERT1        2  ///CS1
  46
  47 /* Slave spi_dev related */
  48 struct chip_data {
  49         u16 cr0;
  50         u8 cs;                  /* chip select pin */
  51         u8 n_bytes;             /* current is a 1/2/4 byte op */
  52         u8 tmode;               /* TR/TO/RO/EEPROM */
  53         u8 type;                /* SPI/SSP/MicroWire */
  54
  55         u8 poll_mode;           /* 1 means use poll mode */
  56
  57         u32 dma_width;
  58         u32 rx_threshold;
  59         u32 tx_threshold;
  60         u8 enable_dma;
  61         u8 bits_per_word;
  62         u16 clk_div;            /* baud rate divider */
  63         u32 speed_hz;           /* baud rate */
  64         int (*write)(struct rk2818_spi *dws);
  65         int (*read)(struct rk2818_spi *dws);
  66         void (*cs_control)(struct rk2818_spi *dws, u32 cs);
  67 };
  68
  69 #ifdef CONFIG_DEBUG_FS
  70 static int spi_show_regs_open(struct inode *inode, struct file *file)
  71 {
  72         file->private_data = inode->i_private;
  73         return 0;
  74 }
  75
  76 #define SPI_REGS_BUFSIZE        1024
  77 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  78                                 size_t count, loff_t *ppos)
  79 {
  80         struct rk2818_spi *dws;
  81         char *buf;
  82         u32 len = 0;
  83         ssize_t ret;
  84
  85         dws = file->private_data;
  86
  87         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  88         if (!buf)
  89                 return 0;
  90
  91         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  92                         "MRST SPI0 registers:\n");
  93         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  94                         "=================================\n");
  95         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  96                         "CTRL0: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR0));
  97         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
  98                         "CTRL1: \t\t0x%08x\n", rk2818_readl(dws, SPIM_CTRLR1));
  99         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 100                         "SSIENR: \t0x%08x\n", rk2818_readl(dws, SPIM_SPIENR));
 101         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 102                         "SER: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SER));
 103         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 104                         "BAUDR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_BAUDR));
 105         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 106                         "TXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_TXFTLR));
 107         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 108                         "RXFTLR: \t0x%08x\n", rk2818_readl(dws, SPIM_RXFTLR));
 109         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 110                         "TXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_TXFLR));
 111         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 112                         "RXFLR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_RXFLR));
 113         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 114                         "SR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_SR));
 115         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 116                         "IMR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_IMR));
 117         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 118                         "ISR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_ISR));
 119         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 120                         "DMACR: \t\t0x%08x\n", rk2818_readl(dws, SPIM_DMACR));
 121         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 122                         "DMATDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMATDLR));
 123         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 124                         "DMARDLR: \t0x%08x\n", rk2818_readl(dws, SPIM_DMARDLR));
 125         len += printk(buf + len, SPI_REGS_BUFSIZE - len,
 126                         "=================================\n");
 127
 128         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 129         kfree(buf);
 130         return ret;
 131 }
 132
 133 static const struct file_operations mrst_spi_regs_ops = {
 134         .owner          = THIS_MODULE,
 135         .open           = spi_show_regs_open,
 136         .read           = spi_show_regs,
 137 };
 138
 139 static int mrst_spi_debugfs_init(struct rk2818_spi *dws)
 140 {
 141         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 142         if (!dws->debugfs)
 143                 return -ENOMEM;
 144
 145         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 146                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 147         return 0;
 148 }
 149
 150 static void mrst_spi_debugfs_remove(struct rk2818_spi *dws)
 151 {
 152         if (dws->debugfs)
 153                 debugfs_remove_recursive(dws->debugfs);
 154 }
 155
 156 #else
 157 static inline int mrst_spi_debugfs_init(struct rk2818_spi *dws)
 158 {
 159         return 0;
 160 }
 161
 162 static inline void mrst_spi_debugfs_remove(struct rk2818_spi *dws)
 163 {
 164 }
 165 #endif /* CONFIG_DEBUG_FS */
 166
 167 static void wait_till_not_busy(struct rk2818_spi *dws)
 168 {
 169         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
 170
 171         while (time_before(jiffies, end)) {
 172                 if (!(rk2818_readw(dws, SPIM_SR) & SR_BUSY))
 173                         return;
 174         }
 175         dev_err(&dws->master->dev,
 176                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
 177 }
 178
 179 static void flush(struct rk2818_spi *dws)
 180 {
 181         while (rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 182                 rk2818_readw(dws, SPIM_DR0);
 183
 184         wait_till_not_busy(dws);
 185 }
 186
 187 static void spi_cs_control(struct rk2818_spi *dws, u32 cs)
 188 {
 189         struct rk2818_spi_platform_data *pdata = dws->master->dev.platform_data;
 190         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;
 191         int i;
 192
 193         if (cs == 0)
 194                 for (i=0; i<pdata->num_chipselect; i++)
 195                         gpio_direction_output(cs_gpios[i].cs_gpio, GPIO_HIGH);
 196         else
 197                 gpio_direction_output(cs_gpios[cs-1].cs_gpio, GPIO_LOW);
 198 }
 199
 200 static int null_writer(struct rk2818_spi *dws)
 201 {
 202         u8 n_bytes = dws->n_bytes;
 203
 204         if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
 205                 || (dws->tx == dws->tx_end))
 206                 return 0;
 207         rk2818_writew(dws, SPIM_DR0, 0);
 208         dws->tx += n_bytes;
 209
 210         wait_till_not_busy(dws);
 211         return 1;
 212 }
 213
 214 static int null_reader(struct rk2818_spi *dws)
 215 {
 216         u8 n_bytes = dws->n_bytes;
 217         while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 218                 && (dws->rx < dws->rx_end)) {
 219                 rk2818_readw(dws, SPIM_DR0);
 220                 dws->rx += n_bytes;
 221         }
 222         wait_till_not_busy(dws);
 223         return dws->rx == dws->rx_end;
 224 }
 225
 226 static int u8_writer(struct rk2818_spi *dws)
 227 {
 228         if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
 229                 || (dws->tx == dws->tx_end))
 230                 return 0;
 231         rk2818_writew(dws, SPIM_DR0, *(u8 *)(dws->tx));
 232         ++dws->tx;
 233
 234         wait_till_not_busy(dws);
 235         return 1;
 236 }
 237
 238 static int u8_reader(struct rk2818_spi *dws)
 239 {
 240         while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 241                 && (dws->rx < dws->rx_end)) {
 242                 *(u8 *)(dws->rx) = rk2818_readw(dws, SPIM_DR0);
 243                 ++dws->rx;
 244         }
 245
 246         wait_till_not_busy(dws);
 247         return dws->rx == dws->rx_end;
 248 }
 249
 250 static int u16_writer(struct rk2818_spi *dws)
 251 {
 252         if (!(rk2818_readw(dws, SPIM_SR) & SR_TF_NOT_FULL)
 253                 || (dws->tx == dws->tx_end))
 254                 return 0;
 255
 256         rk2818_writew(dws, SPIM_DR0, *(u16 *)(dws->tx));
 257         dws->tx += 2;
 258
 259         wait_till_not_busy(dws);
 260         return 1;
 261 }
 262
 263 static int u16_reader(struct rk2818_spi *dws)
 264 {
 265         u16 temp;
 266
 267         while ((rk2818_readw(dws, SPIM_SR) & SR_RF_NOT_EMPT)
 268                 && (dws->rx < dws->rx_end)) {
 269                 temp = rk2818_readw(dws, SPIM_DR0);
 270                 *(u16 *)(dws->rx) = temp;
 271                 dws->rx += 2;
 272         }
 273
 274         wait_till_not_busy(dws);
 275         return dws->rx == dws->rx_end;
 276 }
 277
 278 static void *next_transfer(struct rk2818_spi *dws)
 279 {
 280         struct spi_message *msg = dws->cur_msg;
 281         struct spi_transfer *trans = dws->cur_transfer;
 282
 283         /* Move to next transfer */
 284         if (trans->transfer_list.next != &msg->transfers) {
 285                 dws->cur_transfer =
 286                         list_entry(trans->transfer_list.next,
 287                                         struct spi_transfer,
 288                                         transfer_list);
 289                 return RUNNING_STATE;
 290         } else
 291                 return DONE_STATE;
 292 }
 293
 294 /*
 295  * Note: first step is the protocol driver prepares
 296  * a dma-capable memory, and this func just need translate
 297  * the virt addr to physical
 298  */
 299 static int map_dma_buffers(struct rk2818_spi *dws)
 300 {
 301         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
 302                 || !dws->cur_chip->enable_dma)
 303                 return 0;
 304
 305         if (dws->cur_transfer->tx_dma)
 306                 dws->tx_dma = dws->cur_transfer->tx_dma;
 307
 308         if (dws->cur_transfer->rx_dma)
 309                 dws->rx_dma = dws->cur_transfer->rx_dma;
 310
 311         return 1;
 312 }
 313
 314 /* Caller already set message->status; dma and pio irqs are blocked */
 315 static void giveback(struct rk2818_spi *dws)
 316 {
 317         struct spi_transfer *last_transfer;
 318         unsigned long flags;
 319         struct spi_message *msg;
 320
 321         spin_lock_irqsave(&dws->lock, flags);
 322         msg = dws->cur_msg;
 323         dws->cur_msg = NULL;
 324         dws->cur_transfer = NULL;
 325         dws->prev_chip = dws->cur_chip;
 326         dws->cur_chip = NULL;
 327         dws->dma_mapped = 0;
 328         queue_work(dws->workqueue, &dws->pump_messages);
 329         spin_unlock_irqrestore(&dws->lock, flags);
 330
 331         last_transfer = list_entry(msg->transfers.prev,
 332                                         struct spi_transfer,
 333                                         transfer_list);
 334
 335         if (!last_transfer->cs_change)
 336                 dws->cs_control(dws,MRST_SPI_DEASSERT);
 337
 338         msg->state = NULL;
 339         if (msg->complete)
 340                 msg->complete(msg->context);
 341 }
 342
 343 static void int_error_stop(struct rk2818_spi *dws, const char *msg)
 344 {
 345         /* Stop and reset hw */
 346         flush(dws);
 347         spi_enable_chip(dws, 0);
 348
 349         dev_err(&dws->master->dev, "%s\n", msg);
 350         dws->cur_msg->state = ERROR_STATE;
 351         tasklet_schedule(&dws->pump_transfers);
 352 }
 353
 354 static void transfer_complete(struct rk2818_spi *dws)
 355 {
 356         /* Update total byte transfered return count actual bytes read */
 357         dws->cur_msg->actual_length += dws->len;
 358
 359         /* Move to next transfer */
 360         dws->cur_msg->state = next_transfer(dws);
 361
 362         /* Handle end of message */
 363         if (dws->cur_msg->state == DONE_STATE) {
 364                 dws->cur_msg->status = 0;
 365                 giveback(dws);
 366         } else
 367                 tasklet_schedule(&dws->pump_transfers);
 368 }
 369
 370 static irqreturn_t interrupt_transfer(struct rk2818_spi *dws)
 371 {
 372         u16 irq_status, irq_mask = 0x3f;
 373         u32 int_level = dws->fifo_len / 2;
 374         u32 left;
 375
 376         irq_status = rk2818_readw(dws, SPIM_ISR) & irq_mask;
 377         /* Error handling */
 378         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 379                 rk2818_readw(dws, SPIM_TXOICR);
 380                 rk2818_readw(dws, SPIM_RXOICR);
 381                 rk2818_readw(dws, SPIM_RXUICR);
 382                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 383                 return IRQ_HANDLED;
 384         }
 385
 386         if (irq_status & SPI_INT_TXEI) {
 387                 spi_mask_intr(dws, SPI_INT_TXEI);
 388
 389                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 390                 left = (left > int_level) ? int_level : left;
 391
 392                 while (left--)
 393                         dws->write(dws);
 394                 dws->read(dws);
 395
 396                 /* Re-enable the IRQ if there is still data left to tx */
 397                 if (dws->tx_end > dws->tx)
 398                         spi_umask_intr(dws, SPI_INT_TXEI);
 399                 else
 400                         transfer_complete(dws);
 401         }
 402
 403         return IRQ_HANDLED;
 404 }
 405
 406 static irqreturn_t rk2818_spi_irq(int irq, void *dev_id)
 407 {
 408         struct rk2818_spi *dws = dev_id;
 409
 410         if (!dws->cur_msg) {
 411                 spi_mask_intr(dws, SPI_INT_TXEI);
 412                 /* Never fail */
 413                 return IRQ_HANDLED;
 414         }
 415
 416         return dws->transfer_handler(dws);
 417 }
 418
 419 /* Must be called inside pump_transfers() */
 420 static void poll_transfer(struct rk2818_spi *dws)
 421 {
 422         while (dws->write(dws))
 423                 dws->read(dws);
 424
 425         transfer_complete(dws);
 426 }
 427
 428 static void dma_transfer(struct rk2818_spi *dws, struct spi_transfer *xfer) //int cs_change)
 429 {
 430
 431 }
 432
 433 static void spi_chip_sel(struct rk2818_spi *dws, u16 cs)
 434 {
 435     if(cs >= dws->master->num_chipselect)
 436                 return;
 437
 438         if (dws->cs_control){
 439             dws->cs_control(dws, cs+1);
 440         }
 441         //rk2818_writel(dws, SPIM_SER, 1 << cs);
 442         rk2818_writel(dws, SPIM_SER, 1 << 0);
 443 }
 444
 445 static void pump_transfers(unsigned long data)
 446 {
 447         struct rk2818_spi *dws = (struct rk2818_spi *)data;
 448         struct spi_message *message = NULL;
 449         struct spi_transfer *transfer = NULL;
 450         struct spi_transfer *previous = NULL;
 451         struct spi_device *spi = NULL;
 452         struct chip_data *chip = NULL;
 453         u8 bits = 0;
 454         u8 imask = 0;
 455         u8 cs_change = 0;
 456         u16 txint_level = 0;
 457         u16 clk_div = 0;
 458         u32 speed = 0;
 459         u32 cr0 = 0;
 460
 461         /* Get current state information */
 462         message = dws->cur_msg;
 463         transfer = dws->cur_transfer;
 464         chip = dws->cur_chip;
 465         spi = message->spi;
 466         if (unlikely(!chip->clk_div))
 467                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
 468         if (message->state == ERROR_STATE) {
 469                 message->status = -EIO;
 470                 goto early_exit;
 471         }
 472
 473         /* Handle end of message */
 474         if (message->state == DONE_STATE) {
 475                 message->status = 0;
 476                 goto early_exit;
 477         }
 478
 479         /* Delay if requested at end of transfer*/
 480         if (message->state == RUNNING_STATE) {
 481                 previous = list_entry(transfer->transfer_list.prev,
 482                                         struct spi_transfer,
 483                                         transfer_list);
 484                 if (previous->delay_usecs)
 485                         udelay(previous->delay_usecs);
 486         }
 487
 488         dws->n_bytes = chip->n_bytes;
 489         dws->dma_width = chip->dma_width;
 490         dws->cs_control = chip->cs_control;
 491
 492         dws->rx_dma = transfer->rx_dma;
 493         dws->tx_dma = transfer->tx_dma;
 494         dws->tx = (void *)transfer->tx_buf;
 495         dws->tx_end = dws->tx + transfer->len;
 496         dws->rx = transfer->rx_buf;
 497         dws->rx_end = dws->rx + transfer->len;
 498         dws->write = dws->tx ? chip->write : null_writer;
 499         dws->read = dws->rx ? chip->read : null_reader;
 500         dws->cs_change = transfer->cs_change;
 501         dws->len = dws->cur_transfer->len;
 502         if (chip != dws->prev_chip)
 503                 cs_change = 1;
 504
 505         cr0 = chip->cr0;
 506
 507         /* Handle per transfer options for bpw and speed */
 508         if (transfer->speed_hz) {
 509                 speed = chip->speed_hz;
 510
 511                 if (transfer->speed_hz != speed) {
 512                         speed = transfer->speed_hz;
 513                         if (speed > clk_get_rate(dws->clock_spim)) {
 514                                 printk(KERN_ERR "MRST SPI0: unsupported"
 515                                         "freq: %dHz\n", speed);
 516                                 message->status = -EIO;
 517                                 goto early_exit;
 518                         }
 519
 520                         /* clk_div doesn't support odd number */
 521                         clk_div = clk_get_rate(dws->clock_spim) / speed;
 522                         clk_div = (clk_div + 1) & 0xfffe;
 523
 524                         chip->speed_hz = speed;
 525                         chip->clk_div = clk_div;
 526                 }
 527         }
 528         if (transfer->bits_per_word) {
 529                 bits = transfer->bits_per_word;
 530
 531                 switch (bits) {
 532                 case 8:
 533                         dws->n_bytes = 1;
 534                         dws->dma_width = 1;
 535                         dws->read = (dws->read != null_reader) ?
 536                                         u8_reader : null_reader;
 537                         dws->write = (dws->write != null_writer) ?
 538                                         u8_writer : null_writer;
 539                         break;
 540                 case 16:
 541                         dws->n_bytes = 2;
 542                         dws->dma_width = 2;
 543                         dws->read = (dws->read != null_reader) ?
 544                                         u16_reader : null_reader;
 545                         dws->write = (dws->write != null_writer) ?
 546                                         u16_writer : null_writer;
 547                         break;
 548                 default:
 549                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 550                                 "%db\n", bits);
 551                         message->status = -EIO;
 552                         goto early_exit;
 553                 }
 554
 555                 cr0 = (bits - 1)
 556                         | (chip->type << SPI_FRF_OFFSET)
 557                         | (spi->mode << SPI_MODE_OFFSET)
 558                         | (chip->tmode << SPI_TMOD_OFFSET);
 559         }
 560         message->state = RUNNING_STATE;
 561
 562         /*
 563          * Adjust transfer mode if necessary. Requires platform dependent
 564          * chipselect mechanism.
 565          */
 566         if (dws->cs_control) {
 567                 if (dws->rx && dws->tx)
 568                         chip->tmode = 0x00;
 569                 else if (dws->rx)
 570                         chip->tmode = 0x02;
 571                 else
 572                         chip->tmode = 0x01;
 573
 574                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
 575                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 576         }
 577         /* Check if current transfer is a DMA transaction */
 578         dws->dma_mapped = map_dma_buffers(dws);
 579
 580         /*
 581          * Interrupt mode
 582          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 583          */
 584         if (!dws->dma_mapped && !chip->poll_mode) {
 585                 int templen = dws->len / dws->n_bytes;
 586                 txint_level = dws->fifo_len / 2;
 587                 txint_level = (templen > txint_level) ? txint_level : templen;
 588
 589                 imask |= SPI_INT_TXEI;
 590                 dws->transfer_handler = interrupt_transfer;
 591         }
 592
 593         /*
 594          * Reprogram registers only if
 595          *      1. chip select changes
 596          *      2. clk_div is changed
 597          *      3. control value changes
 598          */
 599         if (rk2818_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {
 600                 spi_enable_chip(dws, 0);
 601                 if (rk2818_readw(dws, SPIM_CTRLR0) != cr0)
 602                         rk2818_writew(dws, SPIM_CTRLR0, cr0);
 603
 604                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 605                 spi_chip_sel(dws, spi->chip_select);
 606                 /* Set the interrupt mask, for poll mode just diable all int */
 607                 spi_mask_intr(dws, 0xff);
 608                 if (imask)
 609                         spi_umask_intr(dws, imask);
 610                 if (txint_level)
 611                         rk2818_writew(dws, SPIM_TXFTLR, txint_level);
 612
 613                 spi_enable_chip(dws, 1);
 614                 if (cs_change)
 615                         dws->prev_chip = chip;
 616         }
 617
 618         if (dws->dma_mapped)
 619                 dma_transfer(dws, transfer); ///cs_change);
 620
 621         if (chip->poll_mode)
 622                 poll_transfer(dws);
 623
 624         return;
 625
 626 early_exit:
 627         giveback(dws);
 628         return;
 629 }
 630
 631 static void pump_messages(struct work_struct *work)
 632 {
 633         struct rk2818_spi *dws =
 634                 container_of(work, struct rk2818_spi, pump_messages);
 635         unsigned long flags;
 636
 637         /* Lock queue and check for queue work */
 638         spin_lock_irqsave(&dws->lock, flags);
 639         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 640                 dws->busy = 0;
 641                 spin_unlock_irqrestore(&dws->lock, flags);
 642                 return;
 643         }
 644
 645         /* Make sure we are not already running a message */
 646         if (dws->cur_msg) {
 647                 spin_unlock_irqrestore(&dws->lock, flags);
 648                 return;
 649         }
 650
 651         /* Extract head of queue */
 652         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 653         list_del_init(&dws->cur_msg->queue);
 654
 655         /* Initial message state*/
 656         dws->cur_msg->state = START_STATE;
 657         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 658                                                 struct spi_transfer,
 659                                                 transfer_list);
 660         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 661     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj
 662
 663         /* Mark as busy and launch transfers */
 664         tasklet_schedule(&dws->pump_transfers);
 665
 666         dws->busy = 1;
 667         spin_unlock_irqrestore(&dws->lock, flags);
 668 }
 669
 670 /* spi_device use this to queue in their spi_msg */
 671 static int rk2818_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 672 {
 673         struct rk2818_spi *dws = spi_master_get_devdata(spi->master);
 674         unsigned long flags;
 675
 676         spin_lock_irqsave(&dws->lock, flags);
 677
 678         if (dws->run == QUEUE_STOPPED) {
 679                 spin_unlock_irqrestore(&dws->lock, flags);
 680                 return -ESHUTDOWN;
 681         }
 682
 683         msg->actual_length = 0;
 684         msg->status = -EINPROGRESS;
 685         msg->state = START_STATE;
 686
 687         list_add_tail(&msg->queue, &dws->queue);
 688
 689         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 690
 691                 if (dws->cur_transfer || dws->cur_msg)
 692                         queue_work(dws->workqueue,
 693                                         &dws->pump_messages);
 694                 else {
 695                         /* If no other data transaction in air, just go */
 696                         spin_unlock_irqrestore(&dws->lock, flags);
 697                         pump_messages(&dws->pump_messages);
 698                         return 0;
 699                 }
 700         }
 701
 702         spin_unlock_irqrestore(&dws->lock, flags);
 703
 704         return 0;
 705 }
 706
 707 /* This may be called twice for each spi dev */
 708 static int rk2818_spi_setup(struct spi_device *spi)
 709 {
 710         struct rk2818_spi_chip *chip_info = NULL;
 711         struct chip_data *chip;
 712
 713         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 714                 return -EINVAL;
 715
 716         /* Only alloc on first setup */
 717         chip = spi_get_ctldata(spi);
 718         if (!chip) {
 719                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 720                 if (!chip)
 721                         return -ENOMEM;
 722
 723                 chip->cs_control = spi_cs_control;
 724                 chip->enable_dma = 1;  //0;
 725         }
 726
 727         /*
 728          * Protocol drivers may change the chip settings, so...
 729          * if chip_info exists, use it
 730          */
 731         chip_info = spi->controller_data;
 732
 733         /* chip_info doesn't always exist */
 734         if (chip_info) {
 735                 if (chip_info->cs_control)
 736                         chip->cs_control = chip_info->cs_control;
 737
 738                 chip->poll_mode = chip_info->poll_mode;
 739                 chip->type = chip_info->type;
 740
 741                 chip->rx_threshold = 0;
 742                 chip->tx_threshold = 0;
 743
 744                 chip->enable_dma = chip_info->enable_dma;
 745         }
 746
 747         if (spi->bits_per_word <= 8) {
 748                 chip->n_bytes = 1;
 749                 chip->dma_width = 1;
 750                 chip->read = u8_reader;
 751                 chip->write = u8_writer;
 752         } else if (spi->bits_per_word <= 16) {
 753                 chip->n_bytes = 2;
 754                 chip->dma_width = 2;
 755                 chip->read = u16_reader;
 756                 chip->write = u16_writer;
 757         } else {
 758                 /* Never take >16b case for MRST SPIC */
 759                 dev_err(&spi->dev, "invalid wordsize\n");
 760                 return -EINVAL;
 761         }
 762         chip->bits_per_word = spi->bits_per_word;
 763
 764         if (!spi->max_speed_hz) {
 765                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 766                 return -EINVAL;
 767         }
 768         chip->speed_hz = spi->max_speed_hz;
 769
 770         chip->tmode = 0; /* Tx & Rx */
 771         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 772         chip->cr0 = (chip->bits_per_word - 1)
 773                         | (chip->type << SPI_FRF_OFFSET)
 774                         | (spi->mode  << SPI_MODE_OFFSET)
 775                         | (chip->tmode << SPI_TMOD_OFFSET);
 776
 777         spi_set_ctldata(spi, chip);
 778         return 0;
 779 }
 780
 781 static void rk2818_spi_cleanup(struct spi_device *spi)
 782 {
 783         struct chip_data *chip = spi_get_ctldata(spi);
 784         kfree(chip);
 785 }
 786
 787 static int __devinit init_queue(struct rk2818_spi *dws)
 788 {
 789         INIT_LIST_HEAD(&dws->queue);
 790         spin_lock_init(&dws->lock);
 791
 792         dws->run = QUEUE_STOPPED;
 793         dws->busy = 0;
 794
 795         tasklet_init(&dws->pump_transfers,
 796                         pump_transfers, (unsigned long)dws);
 797
 798         INIT_WORK(&dws->pump_messages, pump_messages);
 799         dws->workqueue = create_singlethread_workqueue(
 800                                         dev_name(dws->master->dev.parent));
 801         if (dws->workqueue == NULL)
 802                 return -EBUSY;
 803
 804         return 0;
 805 }
 806
 807 static int start_queue(struct rk2818_spi *dws)
 808 {
 809         unsigned long flags;
 810
 811         spin_lock_irqsave(&dws->lock, flags);
 812
 813         if (dws->run == QUEUE_RUNNING || dws->busy) {
 814                 spin_unlock_irqrestore(&dws->lock, flags);
 815                 return -EBUSY;
 816         }
 817
 818         dws->run = QUEUE_RUNNING;
 819         dws->cur_msg = NULL;
 820         dws->cur_transfer = NULL;
 821         dws->cur_chip = NULL;
 822         dws->prev_chip = NULL;
 823         spin_unlock_irqrestore(&dws->lock, flags);
 824
 825         queue_work(dws->workqueue, &dws->pump_messages);
 826
 827         return 0;
 828 }
 829
 830 static int stop_queue(struct rk2818_spi *dws)
 831 {
 832         unsigned long flags;
 833         unsigned limit = 50;
 834         int status = 0;
 835
 836         spin_lock_irqsave(&dws->lock, flags);
 837         dws->run = QUEUE_STOPPED;
 838         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 839                 spin_unlock_irqrestore(&dws->lock, flags);
 840                 msleep(10);
 841                 spin_lock_irqsave(&dws->lock, flags);
 842         }
 843
 844         if (!list_empty(&dws->queue) || dws->busy)
 845                 status = -EBUSY;
 846         spin_unlock_irqrestore(&dws->lock, flags);
 847
 848         return status;
 849 }
 850
 851 static int destroy_queue(struct rk2818_spi *dws)
 852 {
 853         int status;
 854
 855         status = stop_queue(dws);
 856         if (status != 0)
 857                 return status;
 858         destroy_workqueue(dws->workqueue);
 859         return 0;
 860 }
 861
 862 /* Restart the controller, disable all interrupts, clean rx fifo */
 863 static void spi_hw_init(struct rk2818_spi *dws)
 864 {
 865         spi_enable_chip(dws, 0);
 866         spi_mask_intr(dws, 0xff);
 867         spi_enable_chip(dws, 1);
 868         flush(dws);
 869
 870         /*
 871          * Try to detect the FIFO depth if not set by interface driver,
 872          * the depth could be from 2 to 32 from HW spec
 873          */
 874         if (!dws->fifo_len) {
 875                 u32 fifo;
 876                 for (fifo = 2; fifo <= 31; fifo++) {
 877                         rk2818_writew(dws, SPIM_TXFTLR, fifo);
 878                         if (fifo != rk2818_readw(dws, SPIM_TXFTLR))
 879                                 break;
 880                 }
 881
 882                 dws->fifo_len = (fifo == 31) ? 0 : fifo;
 883                 rk2818_writew(dws, SPIM_TXFTLR, 0);
 884         }
 885 }
 886
 887 /* cpufreq driver support */
 888 #ifdef CONFIG_CPU_FREQ
 889
 890 static int rk2818_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
 891 {
 892         struct rk2818_spi *info;
 893         unsigned long newclk;
 894
 895         info = container_of(nb, struct rk2818_spi, freq_transition);
 896         newclk = clk_get_rate(info->clock_spim);
 897
 898         return 0;
 899 }
 900
 901 static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info)
 902 {
 903         info->freq_transition.notifier_call = rk2818_spim_cpufreq_transition;
 904
 905         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 906 }
 907
 908 static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info)
 909 {
 910         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
 911 }
 912
 913 #else
 914 static inline int rk2818_spim_cpufreq_register(struct rk2818_spi *info)
 915 {
 916         return 0;
 917 }
 918
 919 static inline void rk2818_spim_cpufreq_deregister(struct rk2818_spi *info)
 920 {
 921 }
 922 #endif
 923 static int __init rk2818_spim_probe(struct platform_device *pdev)
 924 {
 925         struct resource         *regs;
 926         struct rk2818_spi   *dws;
 927         struct spi_master   *master;
 928         int                     irq;
 929         int         ret,i,j;
 930         struct rk2818_spi_platform_data *pdata = pdev->dev.platform_data;
 931
 932         if (pdata && pdata->io_init) {
 933                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);
 934                 if (ret) {
 935                         return -ENXIO;
 936                 }
 937         }
 938
 939         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 940         if (!regs)
 941                 return -ENXIO;
 942         irq = platform_get_irq(pdev, 0);
 943         if (irq < 0)
 944                 return irq;
 945         /* setup spi core then atmel-specific driver state */
 946         ret = -ENOMEM;
 947         master = spi_alloc_master(&pdev->dev, sizeof *dws);
 948         if (!master) {
 949                 ret = -ENOMEM;
 950                 goto exit;
 951         }
 952         platform_set_drvdata(pdev, master);
 953         dws = spi_master_get_devdata(master);
 954         dws->clock_spim = clk_get(&pdev->dev, "spi");
 955         clk_enable(dws->clock_spim);
 956         if (IS_ERR(dws->clock_spim))
 957                 return PTR_ERR(dws->clock_spim);
 958         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
 959         if (!dws->regs){
 960         release_mem_region(regs->start, (regs->end - regs->start) + 1);
 961                 return -EBUSY;
 962         }
 963     dws->irq = irq;
 964         dws->master = master;
 965         dws->type = SSI_MOTO_SPI;
 966         dws->prev_chip = NULL;
 967         dws->dma_inited = 1;  ///0;
 968         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 969         ret = request_irq(dws->irq, rk2818_spi_irq, 0,
 970                         "rk2818_spim", dws);
 971         if (ret < 0) {
 972                 dev_err(&master->dev, "can not get IRQ\n");
 973                 goto err_free_master;
 974         }
 975         master->mode_bits = SPI_CPOL | SPI_CPHA;
 976         master->bus_num = pdev->id;
 977         master->num_chipselect = pdata->num_chipselect;
 978         master->dev.platform_data = pdata;
 979         master->cleanup = rk2818_spi_cleanup;
 980         master->setup = rk2818_spi_setup;
 981         master->transfer = rk2818_spi_transfer;
 982         dws->pdev = pdev;
 983         /* Basic HW init */
 984         spi_hw_init(dws);
 985         /* Initial and start queue */
 986         ret = init_queue(dws);
 987         if (ret) {
 988                 dev_err(&master->dev, "problem initializing queue\n");
 989                 goto err_diable_hw;
 990         }
 991         ret = start_queue(dws);
 992         if (ret) {
 993                 dev_err(&master->dev, "problem starting queue\n");
 994                 goto err_diable_hw;
 995         }
 996         spi_master_set_devdata(master, dws);
 997         ret = spi_register_master(master);
 998         if (ret) {
 999                 dev_err(&master->dev, "problem registering spi master\n");
1000                 goto err_queue_alloc;
1001         }
1002
1003         ret =rk2818_spim_cpufreq_register(dws);
1004         if (ret < 0) {
1005                 printk(KERN_ERR"rk2818 spim failed to init cpufreq support\n");
1006                 goto err_queue_alloc;
1007         }
1008         printk(KERN_INFO "rk2818_spim: driver initialized\n");
1009         mrst_spi_debugfs_init(dws);
1010         return 0;
1011
1012 err_queue_alloc:
1013         destroy_queue(dws);
1014 err_diable_hw:
1015         spi_enable_chip(dws, 0);
1016         free_irq(dws->irq, dws);
1017 err_free_master:
1018         spi_master_put(master);
1019         iounmap(dws->regs);
1020 exit:
1021         return ret;
1022 }
1023
1024 static void __exit rk2818_spim_remove(struct platform_device *pdev)
1025 {
1026         struct spi_master *master = platform_get_drvdata(pdev);
1027         struct rk2818_spi *dws = spi_master_get_devdata(master);
1028         int status = 0;
1029
1030         if (!dws)
1031                 return;
1032         rk2818_spim_cpufreq_deregister(dws);
1033         mrst_spi_debugfs_remove(dws);
1034
1035         /* Remove the queue */
1036         status = destroy_queue(dws);
1037         if (status != 0)
1038                 dev_err(&dws->master->dev, "rk2818_spi_remove: workqueue will not "
1039                         "complete, message memory not freed\n");
1040         clk_put(dws->clock_spim);
1041         clk_disable(dws->clock_spim);
1042         spi_enable_chip(dws, 0);
1043         /* Disable clk */
1044         spi_set_clk(dws, 0);
1045         free_irq(dws->irq, dws);
1046
1047         /* Disconnect from the SPI framework */
1048         spi_unregister_master(dws->master);
1049         iounmap(dws->regs);
1050 }
1051
1052
1053 #ifdef  CONFIG_PM
1054
1055 static int rk2818_spim_suspend(struct platform_device *pdev, pm_message_t mesg)
1056 {
1057         struct spi_master *master = platform_get_drvdata(pdev);
1058         struct rk2818_spi *dws = spi_master_get_devdata(master);
1059         int status;
1060
1061         status = stop_queue(dws);
1062         if (status != 0)
1063                 return status;
1064         clk_disable(dws->clock_spim);
1065
1066         return 0;
1067 }
1068
1069 static int rk2818_spim_resume(struct platform_device *pdev)
1070 {
1071         struct spi_master *master = platform_get_drvdata(pdev);
1072         struct rk2818_spi *dws = spi_master_get_devdata(master);
1073         int ret;
1074
1075         clk_enable(dws->clock_spim);
1076         spi_hw_init(dws);
1077         ret = start_queue(dws);
1078         if (ret)
1079                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
1080         return ret;
1081 }
1082
1083 #else
1084 #define rk2818_spim_suspend     NULL
1085 #define rk2818_spim_resume      NULL
1086 #endif
1087
1088 static struct platform_driver rk2818_platform_spim_driver = {
1089         .remove         = __exit_p(rk2818_spim_remove),
1090         .driver         = {
1091                 .name   = "rk2818_spim",
1092                 .owner  = THIS_MODULE,
1093         },
1094         .suspend        = rk2818_spim_suspend,
1095         .resume         = rk2818_spim_resume,
1096 };
1097
1098 static int __init rk2818_spim_init(void)
1099 {
1100         int ret;
1101         ret = platform_driver_probe(&rk2818_platform_spim_driver, rk2818_spim_probe);
1102         return ret;
1103 }
1104
1105 static void __exit rk2818_spim_exit(void)
1106 {
1107         platform_driver_unregister(&rk2818_platform_spim_driver);
1108 }
1109
1110 subsys_initcall(rk2818_spim_init);
1111 module_exit(rk2818_spim_exit);
1112
1113 MODULE_AUTHOR("lhh lhh@rock-chips.com");
1114 MODULE_DESCRIPTION("Rockchip RK2818 spim port driver");
1115 MODULE_LICENSE("GPL");;