1 /* drivers/spi/rk2818_spim.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #ifndef __DRIVERS_SPIM_RK2818_HEADER_H
15 #define __DRIVERS_SPIM_RK2818_HEADER_H
18 /* Bit fields in CTRLR0 */
19 #define SPI_DFS_OFFSET 0
21 #define SPI_FRF_OFFSET 4
22 #define SPI_FRF_SPI 0x0
23 #define SPI_FRF_SSP 0x1
24 #define SPI_FRF_MICROWIRE 0x2
25 #define SPI_FRF_RESV 0x3
27 #define SPI_MODE_OFFSET 6
28 #define SPI_SCPH_OFFSET 6
29 #define SPI_SCOL_OFFSET 7
30 #define SPI_TMOD_OFFSET 8
31 #define SPI_TMOD_TR 0x0 /* xmit & recv */
32 #define SPI_TMOD_TO 0x1 /* xmit only */
33 #define SPI_TMOD_RO 0x2 /* recv only */
34 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
36 #define SPI_SLVOE_OFFSET 10
37 #define SPI_SRL_OFFSET 11
38 #define SPI_CFS_OFFSET 12
40 /* Bit fields in SR, 7 bits */
41 #define SR_MASK 0x7f /* cover 7 bits */
42 #define SR_BUSY (1 << 0)
43 #define SR_TF_NOT_FULL (1 << 1)
44 #define SR_TF_EMPT (1 << 2)
45 #define SR_RF_NOT_EMPT (1 << 3)
46 #define SR_RF_FULL (1 << 4)
47 #define SR_TX_ERR (1 << 5)
48 #define SR_DCOL (1 << 6)
50 /* Bit fields in ISR, IMR, RISR, 7 bits */
51 #define SPI_INT_TXEI (1 << 0)
52 #define SPI_INT_TXOI (1 << 1)
53 #define SPI_INT_RXUI (1 << 2)
54 #define SPI_INT_RXOI (1 << 3)
55 #define SPI_INT_RXFI (1 << 4)
56 #define SPI_INT_MSTI (1 << 5)
58 /* TX RX interrupt level threshhold, max can be 256 */
59 #define SPI_INT_THRESHOLD 32
61 #define SPIM_CTRLR0 0x0000
62 #define SPIM_CTRLR1 0x0004
63 #define SPIM_SPIENR 0x0008
64 #define SPIM_MWCR 0x000c
65 #define SPIM_SER 0x0010
66 #define SPIM_BAUDR 0x0014
67 #define SPIM_TXFTLR 0x0018
68 #define SPIM_RXFTLR 0x001c
69 #define SPIM_TXFLR 0x0020
70 #define SPIM_RXFLR 0x0024
71 #define SPIM_SR 0x0028
72 #define SPIM_IMR 0x002c
73 #define SPIM_ISR 0x0030
74 #define SPIM_RISR 0x0034
75 #define SPIM_TXOICR 0x0038
76 #define SPIM_RXOICR 0x003c
77 #define SPIM_RXUICR 0x0040
78 #define SPIM_MSTICR 0x0044
79 #define SPIM_ICR 0x0048
80 #define SPIM_DMACR 0x004c
81 #define SPIM_DMATDLR 0x0050
82 #define SPIM_DMARDLR 0x0054
83 #define SPIM_IDR0 0x0058
84 #define SPIM_COMP_VERSION 0x005c
85 #define SPIM_DR0 0x0060
87 enum rk2818_ssi_type {
94 struct spi_master *master;
95 struct spi_device *cur_dev;
96 enum rk2818_ssi_type type;
102 u32 fifo_len; /* depth of the FIFO buffer */
103 struct clk *clock_spim; /* clk apb */
104 struct platform_device *pdev;
106 /* Driver message queue */
107 struct workqueue_struct *workqueue;
108 struct work_struct pump_messages;
110 struct list_head queue;
114 /* Message Transfer pump */
115 struct tasklet_struct pump_transfers;
117 /* Current message transfer state info */
118 struct spi_message *cur_msg;
119 struct spi_transfer *cur_transfer;
120 struct chip_data *cur_chip;
121 struct chip_data *prev_chip;
132 u8 n_bytes; /* current is a 1/2 bytes op */
133 u8 max_bits_per_word; /* maxim is 16b */
136 int (*write)(struct rk2818_spi *dws);
137 int (*read)(struct rk2818_spi *dws);
138 irqreturn_t (*transfer_handler)(struct rk2818_spi *dws);
139 void (*cs_control)(struct rk2818_spi *dws, u32 cs);
143 struct dma_chan *txchan;
144 struct dma_chan *rxchan;
149 struct device *dma_dev;
152 /* Bus interface info */
154 #ifdef CONFIG_DEBUG_FS
155 struct dentry *debugfs;
157 #ifdef CONFIG_CPU_FREQ
158 struct notifier_block freq_transition;
162 #define rk2818_readl(dw, off) \
163 __raw_readl(dw->regs + off)
164 #define rk2818_writel(dw,off,val) \
165 __raw_writel(val, dw->regs + off)
166 #define rk2818_readw(dw, off) \
167 __raw_readw(dw->regs + off)
168 #define rk2818_writew(dw,off,val) \
169 __raw_writel(val, dw->regs + off)
171 static inline void spi_enable_chip(struct rk2818_spi *dws, int enable)
173 rk2818_writel(dws, SPIM_SPIENR, (enable ? 1 : 0));
176 static inline void spi_set_clk(struct rk2818_spi *dws, u16 div)
178 rk2818_writel(dws, SPIM_BAUDR, div);
181 /* Disable IRQ bits */
182 static inline void spi_mask_intr(struct rk2818_spi *dws, u32 mask)
186 new_mask = rk2818_readl(dws, SPIM_IMR) & ~mask;
187 rk2818_writel(dws, SPIM_IMR, new_mask);
190 /* Enable IRQ bits */
191 static inline void spi_umask_intr(struct rk2818_spi *dws, u32 mask)
195 new_mask = rk2818_readl(dws, SPIM_IMR) | mask;
196 rk2818_writel(dws, SPIM_IMR, new_mask);
200 * Each SPI slave device to work with rk2818_api controller should
201 * has such a structure claiming its working mode (PIO/DMA etc),
202 * which can be save in the "controller_data" member of the
205 struct rk2818_spi_chip {
206 u8 poll_mode; /* 0 for contoller polling mode */
207 u8 type; /* SPI/SSP/Micrwire */
209 void (*cs_control)(struct rk2818_spi *dws, u32 cs);
212 #endif /* __DRIVERS_SPIM_RK2818_HEADER_H */