1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device
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3 * Copyright (C) 2010 ROCKCHIP, Inc.
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5 * This software is licensed under the terms of the GNU General Public
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6 * License version 2, as published by the Free Software Foundation, and
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7 * may be copied, distributed, and modified under those terms.
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9 * This program is distributed in the hope that it will be useful,
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 * GNU General Public License for more details.
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15 #include <linux/dma-mapping.h>
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16 #include <linux/interrupt.h>
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17 #include <linux/highmem.h>
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18 #include <linux/delay.h>
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19 #include <linux/slab.h>
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20 #include <linux/platform_device.h>
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21 #include <linux/clk.h>
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22 #include <linux/cpufreq.h>
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23 #include <mach/gpio.h>
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24 #include <mach/irqs.h>
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25 #include <linux/dma-mapping.h>
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26 #include <asm/dma.h>
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27 #include <linux/preempt.h>
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28 #include "rk29_spim.h"
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29 #include <linux/spi/spi.h>
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30 #include <mach/board.h>
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32 #ifdef CONFIG_DEBUG_FS
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33 #include <linux/debugfs.h>
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36 /*ÔÓеÄspiÇý¶¯Ð§ÂʱȽϵͣ¬
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37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Ê䣻
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38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Ê䣬ͬʱ¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬
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42 //#define QUICK_TRANSFER
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50 #define DMA_BUFFER_SIZE PAGE_SIZE
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51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO
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54 #define START_STATE ((void *)0)
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55 #define RUNNING_STATE ((void *)1)
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56 #define DONE_STATE ((void *)2)
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57 #define ERROR_STATE ((void *)-1)
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59 #define QUEUE_RUNNING 0
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60 #define QUEUE_STOPPED 1
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62 #define MRST_SPI_DEASSERT 0
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63 #define MRST_SPI_ASSERT 1 ///CS0
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64 #define MRST_SPI_ASSERT1 2 ///CS1
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66 /* Slave spi_dev related */
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69 u8 cs; /* chip select pin */
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70 u8 n_bytes; /* current is a 1/2/4 byte op */
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71 u8 tmode; /* TR/TO/RO/EEPROM */
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72 u8 type; /* SPI/SSP/MicroWire */
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74 u8 poll_mode; /* 1 means use poll mode */
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81 u16 clk_div; /* baud rate divider */
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82 u32 speed_hz; /* baud rate */
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83 int (*write)(struct rk29xx_spi *dws);
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84 int (*read)(struct rk29xx_spi *dws);
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85 void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);
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88 #define SUSPND (1<<0)
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89 #define SPIBUSY (1<<1)
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90 #define RXBUSY (1<<2)
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91 #define TXBUSY (1<<3)
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94 #ifdef CONFIG_LCD_USE_SPIM_CONTROL
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95 void rk29_lcd_spim_spin_lock(void)
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97 #ifdef CONFIG_LCD_USE_SPI0
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98 disable_irq(IRQ_SPI0);
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101 #ifdef CONFIG_LCD_USE_SPI1
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102 disable_irq(IRQ_SPI1);
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108 void rk29_lcd_spim_spin_unlock(void)
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112 #ifdef CONFIG_LCD_USE_SPI0
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113 enable_irq(IRQ_SPI0);
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116 #ifdef CONFIG_LCD_USE_SPI1
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117 enable_irq(IRQ_SPI1);
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121 void rk29_lcd_spim_spin_lock(void)
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126 void rk29_lcd_spim_spin_unlock(void)
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133 static void spi_dump_regs(struct rk29xx_spi *dws) {
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134 DBG("MRST SPI0 registers:\n");
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135 DBG("=================================\n");
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136 DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));
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137 DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));
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138 DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));
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139 DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));
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140 DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));
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141 DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));
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142 DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));
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143 DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));
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144 DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));
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145 DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));
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146 DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));
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147 DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));
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148 DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));
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149 DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));
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150 DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));
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151 DBG("=================================\n");
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155 #ifdef CONFIG_DEBUG_FS
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156 static int spi_show_regs_open(struct inode *inode, struct file *file)
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158 file->private_data = inode->i_private;
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162 #define SPI_REGS_BUFSIZE 1024
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163 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
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164 size_t count, loff_t *ppos)
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166 struct rk29xx_spi *dws;
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171 dws = file->private_data;
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173 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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177 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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178 "MRST SPI0 registers:\n");
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179 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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180 "=================================\n");
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181 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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182 "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));
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183 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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184 "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));
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185 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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186 "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));
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187 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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188 "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));
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189 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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190 "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));
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191 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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192 "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));
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193 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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194 "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));
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195 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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196 "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));
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197 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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198 "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));
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199 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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200 "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));
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201 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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202 "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));
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203 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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204 "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));
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205 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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206 "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));
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207 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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208 "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));
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209 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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210 "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));
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211 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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212 "=================================\n");
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214 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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219 static const struct file_operations mrst_spi_regs_ops = {
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220 .owner = THIS_MODULE,
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221 .open = spi_show_regs_open,
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222 .read = spi_show_regs,
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225 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)
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227 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
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231 debugfs_create_file("registers", S_IFREG | S_IRUGO,
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232 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
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236 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)
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239 debugfs_remove_recursive(dws->debugfs);
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243 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)
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248 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)
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251 #endif /* CONFIG_DEBUG_FS */
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253 static void dma_transfer(struct rk29xx_spi *dws) ;
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254 static void transfer_complete(struct rk29xx_spi *dws);
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256 static void wait_till_not_busy(struct rk29xx_spi *dws)
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258 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
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260 while (time_before(jiffies, end)) {
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261 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))
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264 dev_err(&dws->master->dev,
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265 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
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268 #if defined(QUICK_TRANSFER)
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269 static void wait_till_tf_empty(struct rk29xx_spi *dws)
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271 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
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273 while (time_before(jiffies, end)) {
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274 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)
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277 dev_err(&dws->master->dev,
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278 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
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282 static void flush(struct rk29xx_spi *dws)
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284 while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))
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285 rk29xx_readw(dws, SPIM_RXDR);
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287 wait_till_not_busy(dws);
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290 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)
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294 rk29xx_writel(dws, SPIM_SER, 1 << cs);
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296 rk29xx_writel(dws, SPIM_SER, 0);
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299 struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;
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300 struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;
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303 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);
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306 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);
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311 static int null_writer(struct rk29xx_spi *dws)
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313 u8 n_bytes = dws->n_bytes;
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315 if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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316 || (dws->tx == dws->tx_end))
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318 rk29xx_writew(dws, SPIM_TXDR, 0);
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319 dws->tx += n_bytes;
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320 //wait_till_not_busy(dws);
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325 static int null_reader(struct rk29xx_spi *dws)
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327 u8 n_bytes = dws->n_bytes;
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328 DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);
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329 while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))
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330 && (dws->rx < dws->rx_end)) {
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331 rk29xx_readw(dws, SPIM_RXDR);
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332 dws->rx += n_bytes;
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334 wait_till_not_busy(dws);
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335 return dws->rx == dws->rx_end;
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338 static int u8_writer(struct rk29xx_spi *dws)
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340 spi_dump_regs(dws);
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341 DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));
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342 if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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343 || (dws->tx == dws->tx_end))
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345 rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));
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347 //wait_till_not_busy(dws);
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352 static int u8_reader(struct rk29xx_spi *dws)
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354 spi_dump_regs(dws);
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355 while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)
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356 && (dws->rx < dws->rx_end)) {
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357 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;
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358 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));
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362 wait_till_not_busy(dws);
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363 return dws->rx == dws->rx_end;
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366 static int u16_writer(struct rk29xx_spi *dws)
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368 if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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369 || (dws->tx == dws->tx_end))
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372 rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));
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374 //wait_till_not_busy(dws);
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379 static int u16_reader(struct rk29xx_spi *dws)
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383 while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)
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384 && (dws->rx < dws->rx_end)) {
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385 temp = rk29xx_readw(dws, SPIM_RXDR);
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386 *(u16 *)(dws->rx) = temp;
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387 //DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));
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391 wait_till_not_busy(dws);
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392 return dws->rx == dws->rx_end;
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395 static void *next_transfer(struct rk29xx_spi *dws)
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397 struct spi_message *msg = dws->cur_msg;
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398 struct spi_transfer *trans = dws->cur_transfer;
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400 /* Move to next transfer */
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401 if (trans->transfer_list.next != &msg->transfers) {
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402 dws->cur_transfer =
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403 list_entry(trans->transfer_list.next,
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404 struct spi_transfer,
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406 return RUNNING_STATE;
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411 static void rk29_spi_dma_rxcb(void *buf_id,
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412 int size, enum rk29_dma_buffresult res)
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414 struct rk29xx_spi *dws = buf_id;
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415 unsigned long flags;
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417 DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);
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419 spin_lock_irqsave(&dws->lock, flags);
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421 if (res == RK29_RES_OK)
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422 dws->state &= ~RXBUSY;
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424 dev_err(&dws->master->dev, "DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);
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426 /* If the other done */
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427 //if (!(dws->state & TXBUSY))
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428 // complete(&dws->rx_completion);
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430 spin_unlock_irqrestore(&dws->lock, flags);
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432 //DMA could not lose intterupt
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433 transfer_complete(dws);
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437 static void rk29_spi_dma_txcb(void *buf_id,
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438 int size, enum rk29_dma_buffresult res)
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440 struct rk29xx_spi *dws = buf_id;
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441 unsigned long flags;
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443 DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);
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445 spin_lock_irqsave(&dws->lock, flags);
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447 if (res == RK29_RES_OK)
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448 dws->state &= ~TXBUSY;
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450 dev_err(&dws->master->dev, "DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);
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452 /* If the other done */
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453 //if (!(dws->state & RXBUSY))
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454 // complete(&dws->tx_completion);
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456 spin_unlock_irqrestore(&dws->lock, flags);
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458 //DMA could not lose intterupt
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459 transfer_complete(dws);
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464 static struct rk29_dma_client rk29_spi_dma_client = {
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465 .name = "rk29xx-spi-dma",
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468 static int acquire_dma(struct rk29xx_spi *dws)
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470 if (dws->dma_inited) {
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474 dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);
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475 if (!dws->buffer_tx_dma)
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477 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");
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481 dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);
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482 if (!dws->buffer_rx_dma)
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484 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");
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488 if(rk29_dma_request(dws->rx_dmach,
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489 &rk29_spi_dma_client, NULL) < 0) {
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490 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);
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494 if (rk29_dma_request(dws->tx_dmach,
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495 &rk29_spi_dma_client, NULL) < 0) {
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496 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);
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497 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);
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502 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {
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503 dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");
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506 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,
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507 dws->sfr_start + SPIM_TXDR)) {
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508 dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");
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514 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {
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515 dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");
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518 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,
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519 dws->sfr_start + SPIM_RXDR)) {
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520 dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");
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525 dws->dma_inited = 1;
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529 static void release_dma(struct rk29xx_spi *dws)
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531 if(!dws && dws->dma_inited) {
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532 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);
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533 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);
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538 * Note: first step is the protocol driver prepares
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539 * a dma-capable memory, and this func just need translate
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540 * the virt addr to physical
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542 static int map_dma_buffers(struct rk29xx_spi *dws)
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544 if (!dws->dma_inited || !dws->cur_chip->enable_dma)
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546 printk("%s:error\n",__func__);
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550 if(dws->cur_transfer->tx_buf)
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552 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);
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553 dws->cur_transfer->tx_buf = dws->buffer_tx_dma;
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556 if(dws->cur_transfer->rx_buf)
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558 //memcpy(dws->buffer_rx_dma,dws->cur_transfer->rx_buf,dws->cur_transfer->len);
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559 dws->cur_transfer->rx_buf = dws->buffer_rx_dma;
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562 dws->cur_transfer->tx_dma = dws->tx_dma;
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563 dws->cur_transfer->rx_dma = dws->rx_dma;
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568 /* Caller already set message->status; dma and pio irqs are blocked */
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569 static void giveback(struct rk29xx_spi *dws)
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571 struct spi_transfer *last_transfer;
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572 unsigned long flags;
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573 struct spi_message *msg;
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575 spin_lock_irqsave(&dws->lock, flags);
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576 msg = dws->cur_msg;
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577 dws->cur_msg = NULL;
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578 dws->cur_transfer = NULL;
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579 dws->prev_chip = dws->cur_chip;
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580 dws->cur_chip = NULL;
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581 dws->dma_mapped = 0;
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583 /*it is important to close intterrupt*/
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584 spi_umask_intr(dws, 0);
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585 rk29xx_writew(dws, SPIM_DMACR, 0);
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587 queue_work(dws->workqueue, &dws->pump_messages);
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588 spin_unlock_irqrestore(&dws->lock, flags);
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590 last_transfer = list_entry(msg->transfers.prev,
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591 struct spi_transfer,
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594 if (!last_transfer->cs_change && dws->cs_control)
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595 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);
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599 msg->complete(msg->context);
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603 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)
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605 /* Stop and reset hw */
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607 spi_enable_chip(dws, 0);
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609 dev_err(&dws->master->dev, "%s\n", msg);
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610 dws->cur_msg->state = ERROR_STATE;
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611 tasklet_schedule(&dws->pump_transfers);
\r
614 static void transfer_complete(struct rk29xx_spi *dws)
\r
616 /* Update total byte transfered return count actual bytes read */
\r
617 dws->cur_msg->actual_length += dws->len;
\r
619 /* Move to next transfer */
\r
620 dws->cur_msg->state = next_transfer(dws);
\r
622 /* Handle end of message */
\r
623 if (dws->cur_msg->state == DONE_STATE) {
\r
624 dws->cur_msg->status = 0;
\r
627 tasklet_schedule(&dws->pump_transfers);
\r
630 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)
\r
632 u16 irq_status, irq_mask = 0x1f;
\r
633 u32 int_level = dws->fifo_len / 2;
\r
636 irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;
\r
637 /* Error handling */
\r
638 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
\r
639 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);
\r
640 int_error_stop(dws, "interrupt_transfer: fifo overrun");
\r
641 mutex_unlock(&dws->dma_lock);
\r
642 return IRQ_HANDLED;
\r
645 if (irq_status & SPI_INT_TXEI) {
\r
646 spi_mask_intr(dws, SPI_INT_TXEI);
\r
648 left = (dws->tx_end - dws->tx) / dws->n_bytes;
\r
649 left = (left > int_level) ? int_level : left;
\r
653 wait_till_not_busy(dws);
\r
659 /* Re-enable the IRQ if there is still data left to tx */
\r
660 if (dws->tx_end > dws->tx)
\r
661 spi_umask_intr(dws, SPI_INT_TXEI);
\r
663 transfer_complete(dws);
\r
666 if (irq_status & SPI_INT_RXFI) {
\r
667 spi_mask_intr(dws, SPI_INT_RXFI);
\r
671 /* Re-enable the IRQ if there is still data left to rx */
\r
672 if (dws->rx_end > dws->rx) {
\r
673 left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;
\r
674 left = (left > int_level) ? int_level : left;
\r
676 rk29xx_writew(dws, SPIM_RXFTLR, left);
\r
677 spi_umask_intr(dws, SPI_INT_RXFI);
\r
680 transfer_complete(dws);
\r
685 return IRQ_HANDLED;
\r
688 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)
\r
690 struct rk29xx_spi *dws = dev_id;
\r
692 if (!dws->cur_msg) {
\r
693 spi_mask_intr(dws, SPI_INT_TXEI);
\r
695 return IRQ_HANDLED;
\r
698 return dws->transfer_handler(dws);
\r
701 /* Must be called inside pump_transfers() */
\r
702 static void poll_transfer(struct rk29xx_spi *dws)
\r
704 DBG("%s\n",__func__);
\r
705 while (dws->write(dws)) {
\r
706 wait_till_not_busy(dws);
\r
709 transfer_complete(dws);
\r
711 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)
\r
713 if(cs >= dws->master->num_chipselect)
\r
716 if (dws->cs_control){
\r
717 dws->cs_control(dws, cs, MRST_SPI_ASSERT);
\r
719 rk29xx_writel(dws, SPIM_SER, 1 << cs);
\r
722 static void pump_transfers(unsigned long data)
\r
724 struct rk29xx_spi *dws = (struct rk29xx_spi *)data;
\r
725 struct spi_message *message = NULL;
\r
726 struct spi_transfer *transfer = NULL;
\r
727 struct spi_transfer *previous = NULL;
\r
728 struct spi_device *spi = NULL;
\r
729 struct chip_data *chip = NULL;
\r
734 u16 txint_level = 0;
\r
735 u16 rxint_level = 0;
\r
740 if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){
\r
745 DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);
\r
747 /* Get current state information */
\r
748 message = dws->cur_msg;
\r
749 transfer = dws->cur_transfer;
\r
750 chip = dws->cur_chip;
\r
751 spi = message->spi;
\r
752 if (unlikely(!chip->clk_div))
\r
753 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
\r
754 if (message->state == ERROR_STATE) {
\r
755 message->status = -EIO;
\r
759 /* Handle end of message */
\r
760 if (message->state == DONE_STATE) {
\r
761 message->status = 0;
\r
765 /* Delay if requested at end of transfer*/
\r
766 if (message->state == RUNNING_STATE) {
\r
767 previous = list_entry(transfer->transfer_list.prev,
\r
768 struct spi_transfer,
\r
770 if (previous->delay_usecs)
\r
771 udelay(previous->delay_usecs);
\r
774 dws->n_bytes = chip->n_bytes;
\r
775 dws->dma_width = chip->dma_width;
\r
776 dws->cs_control = chip->cs_control;
\r
778 //dws->rx_dma = transfer->rx_dma;
\r
779 //dws->tx_dma = transfer->tx_dma;
\r
780 dws->tx = (void *)transfer->tx_buf;
\r
781 dws->tx_end = dws->tx + transfer->len;
\r
782 dws->rx = (void *)transfer->rx_buf;
\r
783 dws->rx_end = dws->rx + transfer->len;
\r
784 dws->write = dws->tx ? chip->write : null_writer;
\r
785 dws->read = dws->rx ? chip->read : null_reader;
\r
786 dws->cs_change = transfer->cs_change;
\r
787 dws->len = dws->cur_transfer->len;
\r
788 if (chip != dws->prev_chip)
\r
793 /* Handle per transfer options for bpw and speed */
\r
794 if (transfer->speed_hz) {
\r
795 speed = chip->speed_hz;
\r
797 if (transfer->speed_hz != speed) {
\r
798 speed = transfer->speed_hz;
\r
799 if (speed > clk_get_rate(dws->clock_spim)) {
\r
800 dev_err(&dws->master->dev, "MRST SPI0: unsupported"
\r
801 "freq: %dHz\n", speed);
\r
802 message->status = -EIO;
\r
806 /* clk_div doesn't support odd number */
\r
807 clk_div = clk_get_rate(dws->clock_spim) / speed;
\r
808 clk_div = (clk_div + 1) & 0xfffe;
\r
810 chip->speed_hz = speed;
\r
811 chip->clk_div = clk_div;
\r
815 if (transfer->bits_per_word) {
\r
816 bits = transfer->bits_per_word;
\r
821 dws->dma_width = 1;
\r
822 dws->read = (dws->read != null_reader) ?
\r
823 u8_reader : null_reader;
\r
824 dws->write = (dws->write != null_writer) ?
\r
825 u8_writer : null_writer;
\r
826 spi_dfs = SPI_DFS_8BIT;
\r
830 dws->dma_width = 2;
\r
831 dws->read = (dws->read != null_reader) ?
\r
832 u16_reader : null_reader;
\r
833 dws->write = (dws->write != null_writer) ?
\r
834 u16_writer : null_writer;
\r
835 spi_dfs = SPI_DFS_16BIT;
\r
838 dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
\r
840 message->status = -EIO;
\r
844 cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
845 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
\r
846 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
\r
847 | (chip->type << SPI_FRF_OFFSET)
\r
848 | (spi->mode << SPI_MODE_OFFSET)
\r
849 | (chip->tmode << SPI_TMOD_OFFSET);
\r
851 message->state = RUNNING_STATE;
\r
854 * Adjust transfer mode if necessary. Requires platform dependent
\r
855 * chipselect mechanism.
\r
857 if (dws->cs_control) {
\r
858 if (dws->rx && dws->tx)
\r
859 chip->tmode = SPI_TMOD_TR;
\r
861 chip->tmode = SPI_TMOD_RO;
\r
863 chip->tmode = SPI_TMOD_TO;
\r
865 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
\r
866 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
\r
871 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
\r
873 if (!dws->dma_mapped && !chip->poll_mode) {
\r
876 if (chip->tmode == SPI_TMOD_RO) {
\r
877 templen = dws->len / dws->n_bytes - 1;
\r
878 rxint_level = dws->fifo_len / 2;
\r
879 rxint_level = (templen > rxint_level) ? rxint_level : templen;
\r
880 imask |= SPI_INT_RXFI;
\r
883 templen = dws->len / dws->n_bytes;
\r
884 txint_level = dws->fifo_len / 2;
\r
885 txint_level = (templen > txint_level) ? txint_level : templen;
\r
886 imask |= SPI_INT_TXEI;
\r
888 dws->transfer_handler = interrupt_transfer;
\r
892 * Reprogram registers only if
\r
893 * 1. chip select changes
\r
894 * 2. clk_div is changed
\r
895 * 3. control value changes
\r
897 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {
\r
898 spi_enable_chip(dws, 0);
\r
899 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)
\r
900 rk29xx_writew(dws, SPIM_CTRLR0, cr0);
\r
902 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
\r
903 spi_chip_sel(dws, spi->chip_select);
\r
905 rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);
\r
906 spi_enable_chip(dws, 1);
\r
909 rk29xx_writew(dws, SPIM_TXFTLR, txint_level);
\r
911 rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);
\r
912 /* Set the interrupt mask, for poll mode just diable all int */
\r
913 spi_mask_intr(dws, 0xff);
\r
915 spi_umask_intr(dws, imask);
\r
918 dws->prev_chip = chip;
\r
921 if (chip->poll_mode)
\r
922 poll_transfer(dws);
\r
931 static void dma_transfer(struct rk29xx_spi *dws)
\r
933 struct spi_message *message = NULL;
\r
934 struct spi_transfer *transfer = NULL;
\r
935 struct spi_transfer *previous = NULL;
\r
936 struct spi_device *spi = NULL;
\r
937 struct chip_data *chip = NULL;
\r
938 //unsigned long val;
\r
939 //unsigned long flags;
\r
951 DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);
\r
953 if (acquire_dma(dws)) {
\r
954 dev_err(&dws->master->dev, "acquire dma failed\n");
\r
958 if (map_dma_buffers(dws)) {
\r
959 dev_err(&dws->master->dev, "acquire dma failed\n");
\r
963 /* Get current state information */
\r
964 message = dws->cur_msg;
\r
965 transfer = dws->cur_transfer;
\r
966 chip = dws->cur_chip;
\r
967 spi = message->spi;
\r
968 if (unlikely(!chip->clk_div))
\r
969 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
\r
970 if (message->state == ERROR_STATE) {
\r
971 message->status = -EIO;
\r
975 /* Handle end of message */
\r
976 if (message->state == DONE_STATE) {
\r
977 message->status = 0;
\r
981 /* Delay if requested at end of transfer*/
\r
982 if (message->state == RUNNING_STATE) {
\r
983 previous = list_entry(transfer->transfer_list.prev,
\r
984 struct spi_transfer,
\r
986 if (previous->delay_usecs)
\r
987 udelay(previous->delay_usecs);
\r
990 dws->n_bytes = chip->n_bytes;
\r
991 dws->dma_width = chip->dma_width;
\r
992 dws->cs_control = chip->cs_control;
\r
994 //dws->rx_dma = transfer->rx_dma;
\r
995 //dws->tx_dma = transfer->tx_dma;
\r
996 dws->tx = (void *)transfer->tx_buf;
\r
997 dws->tx_end = dws->tx + transfer->len;
\r
998 dws->rx = (void *)transfer->rx_buf;
\r
999 dws->rx_end = dws->rx + transfer->len;
\r
1000 dws->write = dws->tx ? chip->write : null_writer;
\r
1001 dws->read = dws->rx ? chip->read : null_reader;
\r
1002 dws->cs_change = transfer->cs_change;
\r
1003 dws->len = dws->cur_transfer->len;
\r
1004 if (chip != dws->prev_chip)
\r
1009 /* Handle per transfer options for bpw and speed */
\r
1010 if (transfer->speed_hz) {
\r
1011 speed = chip->speed_hz;
\r
1012 if (transfer->speed_hz != speed) {
\r
1013 speed = transfer->speed_hz;
\r
1014 if (speed > clk_get_rate(dws->clock_spim)) {
\r
1015 dev_err(&dws->master->dev, "MRST SPI0: unsupported"
\r
1016 "freq: %dHz\n", speed);
\r
1017 message->status = -EIO;
\r
1021 /* clk_div doesn't support odd number */
\r
1022 clk_div = clk_get_rate(dws->clock_spim) / speed;
\r
1023 clk_div = (clk_div + 1) & 0xfffe;
\r
1025 chip->speed_hz = speed;
\r
1026 chip->clk_div = clk_div;
\r
1031 if (transfer->bits_per_word) {
\r
1032 bits = transfer->bits_per_word;
\r
1037 dws->dma_width = 1;
\r
1038 spi_dfs = SPI_DFS_8BIT;
\r
1042 dws->dma_width = 2;
\r
1043 spi_dfs = SPI_DFS_16BIT;
\r
1046 dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
\r
1048 message->status = -EIO;
\r
1052 cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
1053 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
\r
1054 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
\r
1055 | (chip->type << SPI_FRF_OFFSET)
\r
1056 | (spi->mode << SPI_MODE_OFFSET)
\r
1057 | (chip->tmode << SPI_TMOD_OFFSET);
\r
1059 message->state = RUNNING_STATE;
\r
1062 * Adjust transfer mode if necessary. Requires platform dependent
\r
1063 * chipselect mechanism.
\r
1065 if (dws->cs_control) {
\r
1066 if (dws->rx && dws->tx)
\r
1067 chip->tmode = SPI_TMOD_TR;
\r
1069 chip->tmode = SPI_TMOD_RO;
\r
1071 chip->tmode = SPI_TMOD_TO;
\r
1073 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
\r
1074 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
\r
1078 * Reprogram registers only if
\r
1079 * 1. chip select changes
\r
1080 * 2. clk_div is changed
\r
1081 * 3. control value changes
\r
1083 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div) {
\r
1084 spi_enable_chip(dws, 0);
\r
1085 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0) {
\r
1086 rk29xx_writew(dws, SPIM_CTRLR0, cr0);
\r
1089 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
\r
1090 spi_chip_sel(dws, spi->chip_select);
\r
1091 /* Set the interrupt mask, for poll mode just diable all int */
\r
1092 spi_mask_intr(dws, 0xff);
\r
1094 if (transfer->tx_buf != NULL) {
\r
1095 dmacr |= SPI_DMACR_TX_ENABLE;
\r
1096 rk29xx_writew(dws, SPIM_DMATDLR, 0);
\r
1098 if (transfer->rx_buf != NULL) {
\r
1099 dmacr |= SPI_DMACR_RX_ENABLE;
\r
1100 rk29xx_writew(dws, SPIM_DMARDLR, 0);
\r
1101 rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);
\r
1103 rk29xx_writew(dws, SPIM_DMACR, dmacr);
\r
1104 spi_enable_chip(dws, 1);
\r
1106 dws->prev_chip = chip;
\r
1109 //INIT_COMPLETION(dws->xfer_completion);
\r
1111 spi_dump_regs(dws);
\r
1112 DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, transfer->tx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)transfer->tx_dma);
\r
1113 if (transfer->tx_buf != NULL) {
\r
1114 dws->state |= TXBUSY;
\r
1115 /*if (transfer->len & 0x3) {
\r
1121 if (rk29_dma_config(dws->tx_dmach, burst)) {*/
\r
1122 if (rk29_dma_config(dws->tx_dmach, 1, 1)) {//there is not dma burst but bitwide, set it 1 alwayss
\r
1123 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1127 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH);
\r
1129 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,
\r
1130 transfer->tx_dma, transfer->len);
\r
1132 dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet,
\r
1133 dws->tx_dmach, (unsigned int)transfer->tx_dma);
\r
1137 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {
\r
1138 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1143 //wait_till_not_busy(dws);
\r
1145 if (transfer->rx_buf != NULL) {
\r
1146 dws->state |= RXBUSY;
\r
1147 if (rk29_dma_config(dws->rx_dmach, 1, 1)) {
\r
1148 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1152 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH);
\r
1154 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,
\r
1155 transfer->rx_dma, transfer->len);
\r
1157 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1161 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {
\r
1162 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1175 static void pump_messages(struct work_struct *work)
\r
1177 struct rk29xx_spi *dws =
\r
1178 container_of(work, struct rk29xx_spi, pump_messages);
\r
1179 unsigned long flags;
\r
1181 DBG(KERN_INFO "pump_messages\n");
\r
1183 /* Lock queue and check for queue work */
\r
1184 spin_lock_irqsave(&dws->lock, flags);
\r
1185 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
\r
1187 spin_unlock_irqrestore(&dws->lock, flags);
\r
1188 mutex_unlock(&dws->dma_lock);
\r
1192 /* Make sure we are not already running a message */
\r
1193 if (dws->cur_msg) {
\r
1194 spin_unlock_irqrestore(&dws->lock, flags);
\r
1195 mutex_unlock(&dws->dma_lock);
\r
1199 /* Extract head of queue */
\r
1200 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
\r
1201 list_del_init(&dws->cur_msg->queue);
\r
1203 /* Initial message state*/
\r
1204 dws->cur_msg->state = START_STATE;
\r
1205 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
\r
1206 struct spi_transfer,
\r
1208 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
\r
1209 dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj
\r
1211 /* Mark as busy and launch transfers */
\r
1212 tasklet_schedule(&dws->pump_transfers);
\r
1214 spin_unlock_irqrestore(&dws->lock, flags);
\r
1218 #if defined(QUICK_TRANSFER)
\r
1219 static void do_read(struct rk29xx_spi *dws)
\r
1223 spi_enable_chip(dws, 0);
\r
1224 rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);
\r
1225 spi_enable_chip(dws, 1);
\r
1226 rk29xx_writew(dws, SPIM_TXDR, 0);
\r
1228 if (dws->read(dws))
\r
1230 if (count++ == 0x20) {
\r
1231 dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");
\r
1238 static void do_write(struct rk29xx_spi *dws)
\r
1240 while (dws->tx<dws->tx_end) {
\r
1245 /* Caller already set message->status; dma and pio irqs are blocked */
\r
1246 static void msg_giveback(struct rk29xx_spi *dws)
\r
1248 struct spi_transfer *last_transfer;
\r
1249 struct spi_message *msg;
\r
1251 DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1253 msg = dws->cur_msg;
\r
1254 dws->cur_msg = NULL;
\r
1255 dws->cur_transfer = NULL;
\r
1256 dws->prev_chip = dws->cur_chip;
\r
1257 dws->cur_chip = NULL;
\r
1258 dws->dma_mapped = 0;
\r
1261 last_transfer = list_entry(msg->transfers.prev,
\r
1262 struct spi_transfer,
\r
1265 if (!last_transfer->cs_change && dws->cs_control)
\r
1266 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);
\r
1268 msg->state = NULL;
\r
1271 /* Must be called inside pump_transfers() */
\r
1272 static int do_full_transfer(struct rk29xx_spi *dws)
\r
1274 if ((dws->read(dws))) {
\r
1278 while (dws->tx<dws->tx_end){
\r
1283 if (dws->rx < dws->rx_end) {
\r
1289 dws->cur_msg->actual_length += dws->len;
\r
1291 /* Move to next transfer */
\r
1292 dws->cur_msg->state = next_transfer(dws);
\r
1294 if (dws->cur_msg->state == DONE_STATE) {
\r
1295 dws->cur_msg->status = 0;
\r
1296 //msg_giveback(dws);
\r
1306 /* Must be called inside pump_transfers() */
\r
1307 static int do_half_transfer(struct rk29xx_spi *dws)
\r
1313 wait_till_tf_empty(dws);
\r
1314 wait_till_not_busy(dws);
\r
1319 wait_till_tf_empty(dws);
\r
1320 wait_till_not_busy(dws);
\r
1323 dws->cur_msg->actual_length += dws->len;
\r
1325 /* Move to next transfer */
\r
1326 dws->cur_msg->state = next_transfer(dws);
\r
1328 if (dws->cur_msg->state == DONE_STATE) {
\r
1329 dws->cur_msg->status = 0;
\r
1330 //msg_giveback(dws);
\r
1339 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)
\r
1341 struct spi_message *message = NULL;
\r
1342 struct spi_transfer *transfer = NULL;
\r
1343 struct spi_transfer *previous = NULL;
\r
1344 struct spi_device *spi = NULL;
\r
1345 struct chip_data *chip = NULL;
\r
1354 DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1356 /* Get current state information */
\r
1357 message = dws->cur_msg;
\r
1358 transfer = dws->cur_transfer;
\r
1359 chip = dws->cur_chip;
\r
1360 spi = message->spi;
\r
1362 if (unlikely(!chip->clk_div))
\r
1363 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
\r
1364 if (message->state == ERROR_STATE) {
\r
1365 message->status = -EIO;
\r
1369 /* Handle end of message */
\r
1370 if (message->state == DONE_STATE) {
\r
1371 message->status = 0;
\r
1375 /* Delay if requested at end of transfer*/
\r
1376 if (message->state == RUNNING_STATE) {
\r
1377 previous = list_entry(transfer->transfer_list.prev,
\r
1378 struct spi_transfer,
\r
1380 if (previous->delay_usecs)
\r
1381 udelay(previous->delay_usecs);
\r
1384 dws->n_bytes = chip->n_bytes;
\r
1385 dws->dma_width = chip->dma_width;
\r
1386 dws->cs_control = chip->cs_control;
\r
1388 dws->rx_dma = transfer->rx_dma;
\r
1389 dws->tx_dma = transfer->tx_dma;
\r
1390 dws->tx = (void *)transfer->tx_buf;
\r
1391 dws->tx_end = dws->tx + transfer->len;
\r
1392 dws->rx = transfer->rx_buf;
\r
1393 dws->rx_end = dws->rx + transfer->len;
\r
1394 dws->write = dws->tx ? chip->write : null_writer;
\r
1395 dws->read = dws->rx ? chip->read : null_reader;
\r
1396 if (dws->rx && dws->tx) {
\r
1397 int temp_len = transfer->len;
\r
1399 unsigned char *tx_buf;
\r
1400 for (len=0; *tx_buf++ != 0; len++);
\r
1401 dws->tx_end = dws->tx + len;
\r
1402 dws->rx_end = dws->rx + temp_len - len;
\r
1404 dws->cs_change = transfer->cs_change;
\r
1405 dws->len = dws->cur_transfer->len;
\r
1406 if (chip != dws->prev_chip)
\r
1411 /* Handle per transfer options for bpw and speed */
\r
1412 if (transfer->speed_hz) {
\r
1413 speed = chip->speed_hz;
\r
1415 if (transfer->speed_hz != speed) {
\r
1416 speed = transfer->speed_hz;
\r
1417 if (speed > clk_get_rate(dws->clock_spim)) {
\r
1418 dev_err(&dws->master->dev, "MRST SPI0: unsupported"
\r
1419 "freq: %dHz\n", speed);
\r
1420 message->status = -EIO;
\r
1424 /* clk_div doesn't support odd number */
\r
1425 clk_div = clk_get_rate(dws->clock_spim) / speed;
\r
1426 clk_div = (clk_div + 1) & 0xfffe;
\r
1428 chip->speed_hz = speed;
\r
1429 chip->clk_div = clk_div;
\r
1432 if (transfer->bits_per_word) {
\r
1433 bits = transfer->bits_per_word;
\r
1438 dws->dma_width = 1;
\r
1439 dws->read = (dws->read != null_reader) ?
\r
1440 u8_reader : null_reader;
\r
1441 dws->write = (dws->write != null_writer) ?
\r
1442 u8_writer : null_writer;
\r
1443 spi_dfs = SPI_DFS_8BIT;
\r
1447 dws->dma_width = 2;
\r
1448 dws->read = (dws->read != null_reader) ?
\r
1449 u16_reader : null_reader;
\r
1450 dws->write = (dws->write != null_writer) ?
\r
1451 u16_writer : null_writer;
\r
1452 spi_dfs = SPI_DFS_16BIT;
\r
1455 dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
\r
1457 message->status = -EIO;
\r
1461 cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
1462 | (chip->type << SPI_FRF_OFFSET)
\r
1463 | (spi->mode << SPI_MODE_OFFSET)
\r
1464 | (chip->tmode << SPI_TMOD_OFFSET);
\r
1466 message->state = RUNNING_STATE;
\r
1469 * Adjust transfer mode if necessary. Requires platform dependent
\r
1470 * chipselect mechanism.
\r
1472 if (dws->cs_control) {
\r
1473 if (dws->rx && dws->tx)
\r
1474 chip->tmode = SPI_TMOD_TR;
\r
1476 chip->tmode = SPI_TMOD_RO;
\r
1478 chip->tmode = SPI_TMOD_TO;
\r
1480 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
\r
1481 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
\r
1484 /* Check if current transfer is a DMA transaction */
\r
1485 dws->dma_mapped = map_dma_buffers(dws);
\r
1488 * Reprogram registers only if
\r
1489 * 1. chip select changes
\r
1490 * 2. clk_div is changed
\r
1491 * 3. control value changes
\r
1493 spi_enable_chip(dws, 0);
\r
1494 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)
\r
1495 rk29xx_writew(dws, SPIM_CTRLR0, cr0);
\r
1497 DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);
\r
1498 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
\r
1499 spi_chip_sel(dws, spi->chip_select);
\r
1500 rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx
\r
1501 if(dws->dma_mapped ) {
\r
1502 dmacr = rk29xx_readw(dws, SPIM_DMACR);
\r
1503 dmacr = dmacr | SPI_DMACR_TX_ENABLE;
\r
1505 dmacr = dmacr | SPI_DMACR_RX_ENABLE;
\r
1506 rk29xx_writew(dws, SPIM_DMACR, dmacr);
\r
1508 spi_enable_chip(dws, 1);
\r
1510 dws->prev_chip = chip;
\r
1513 return do_full_transfer(dws);
\r
1515 return do_half_transfer(dws);
\r
1519 //msg_giveback(dws);
\r
1524 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)
\r
1526 DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1528 while (!acquire_dma(dws))
\r
1531 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
\r
1536 /* Make sure we are not already running a message */
\r
1537 if (dws->cur_msg) {
\r
1541 /* Extract head of queue */
\r
1542 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
\r
1543 list_del_init(&dws->cur_msg->queue);
\r
1545 /* Initial message state*/
\r
1546 dws->cur_msg->state = START_STATE;
\r
1547 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
\r
1548 struct spi_transfer,
\r
1550 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
\r
1551 dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj
\r
1553 /* Mark as busy and launch transfers */
\r
1556 while (rk29xx_pump_transfers(dws, mode)) ;
\r
1559 /* spi_device use this to queue in their spi_msg */
\r
1560 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)
\r
1562 struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);
\r
1563 unsigned long flags;
\r
1564 struct rk29xx_spi_chip *chip_info = spi->controller_data;
\r
1565 struct spi_message *mmsg;
\r
1567 DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1569 spin_lock_irqsave(&dws->lock, flags);
\r
1571 if (dws->run == QUEUE_STOPPED) {
\r
1572 spin_unlock_irqrestore(&dws->lock, flags);
\r
1573 return -ESHUTDOWN;
\r
1576 msg->actual_length = 0;
\r
1577 msg->status = -EINPROGRESS;
\r
1578 msg->state = START_STATE;
\r
1580 list_add_tail(&msg->queue, &dws->queue);
\r
1582 if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {
\r
1583 rk29xx_pump_messages(dws,1);
\r
1586 rk29xx_pump_messages(dws,0);
\r
1589 mmsg = dws->cur_msg;
\r
1590 msg_giveback(dws);
\r
1592 spin_unlock_irqrestore(&dws->lock, flags);
\r
1594 if (mmsg->complete)
\r
1595 mmsg->complete(mmsg->context);
\r
1602 /* spi_device use this to queue in their spi_msg */
\r
1603 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
\r
1605 struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);
\r
1606 unsigned long flags;
\r
1608 spin_lock_irqsave(&dws->lock, flags);
\r
1610 if (dws->run == QUEUE_STOPPED) {
\r
1611 spin_unlock_irqrestore(&dws->lock, flags);
\r
1612 return -ESHUTDOWN;
\r
1615 msg->actual_length = 0;
\r
1616 msg->status = -EINPROGRESS;
\r
1617 msg->state = START_STATE;
\r
1619 list_add_tail(&msg->queue, &dws->queue);
\r
1621 if (dws->run == QUEUE_RUNNING && !dws->busy) {
\r
1623 if (dws->cur_transfer || dws->cur_msg)
\r
1624 queue_work(dws->workqueue,
\r
1625 &dws->pump_messages);
\r
1627 /* If no other data transaction in air, just go */
\r
1628 spin_unlock_irqrestore(&dws->lock, flags);
\r
1629 pump_messages(&dws->pump_messages);
\r
1634 spin_unlock_irqrestore(&dws->lock, flags);
\r
1641 /* This may be called twice for each spi dev */
\r
1642 static int rk29xx_spi_setup(struct spi_device *spi)
\r
1644 struct rk29xx_spi_chip *chip_info = NULL;
\r
1645 struct chip_data *chip;
\r
1648 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
\r
1651 /* Only alloc on first setup */
\r
1652 chip = spi_get_ctldata(spi);
\r
1654 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
\r
1658 chip->cs_control = spi_cs_control;
\r
1659 chip->enable_dma = 0; //0;
\r
1663 * Protocol drivers may change the chip settings, so...
\r
1664 * if chip_info exists, use it
\r
1666 chip_info = spi->controller_data;
\r
1668 /* chip_info doesn't always exist */
\r
1670 if (chip_info->cs_control)
\r
1671 chip->cs_control = chip_info->cs_control;
\r
1673 chip->poll_mode = chip_info->poll_mode;
\r
1674 chip->type = chip_info->type;
\r
1676 chip->rx_threshold = 0;
\r
1677 chip->tx_threshold = 0;
\r
1679 chip->enable_dma = chip_info->enable_dma;
\r
1682 if (spi->bits_per_word == 8) {
\r
1683 chip->n_bytes = 1;
\r
1684 chip->dma_width = 1;
\r
1685 chip->read = u8_reader;
\r
1686 chip->write = u8_writer;
\r
1687 spi_dfs = SPI_DFS_8BIT;
\r
1688 } else if (spi->bits_per_word == 16) {
\r
1689 chip->n_bytes = 2;
\r
1690 chip->dma_width = 2;
\r
1691 chip->read = u16_reader;
\r
1692 chip->write = u16_writer;
\r
1693 spi_dfs = SPI_DFS_16BIT;
\r
1695 /* Never take >16b case for MRST SPIC */
\r
1696 dev_err(&spi->dev, "invalid wordsize\n");
\r
1699 chip->bits_per_word = spi->bits_per_word;
\r
1701 if (!spi->max_speed_hz) {
\r
1702 dev_err(&spi->dev, "No max speed HZ parameter\n");
\r
1705 chip->speed_hz = spi->max_speed_hz;
\r
1707 chip->tmode = 0; /* Tx & Rx */
\r
1708 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
\r
1709 chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
1710 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
\r
1711 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
\r
1712 | (chip->type << SPI_FRF_OFFSET)
\r
1713 | (spi->mode << SPI_MODE_OFFSET)
\r
1714 | (chip->tmode << SPI_TMOD_OFFSET);
\r
1716 spi_set_ctldata(spi, chip);
\r
1720 static void rk29xx_spi_cleanup(struct spi_device *spi)
\r
1722 struct chip_data *chip = spi_get_ctldata(spi);
\r
1726 static int __devinit init_queue(struct rk29xx_spi *dws)
\r
1728 INIT_LIST_HEAD(&dws->queue);
\r
1729 spin_lock_init(&dws->lock);
\r
1731 dws->run = QUEUE_STOPPED;
\r
1734 init_completion(&dws->xfer_completion);
\r
1736 tasklet_init(&dws->pump_transfers,
\r
1737 pump_transfers, (unsigned long)dws);
\r
1739 INIT_WORK(&dws->pump_messages, pump_messages);
\r
1740 dws->workqueue = create_singlethread_workqueue(
\r
1741 dev_name(dws->master->dev.parent));
\r
1742 if (dws->workqueue == NULL)
\r
1749 static int start_queue(struct rk29xx_spi *dws)
\r
1751 unsigned long flags;
\r
1753 spin_lock_irqsave(&dws->lock, flags);
\r
1755 if (dws->run == QUEUE_RUNNING || dws->busy) {
\r
1756 spin_unlock_irqrestore(&dws->lock, flags);
\r
1760 dws->run = QUEUE_RUNNING;
\r
1761 dws->cur_msg = NULL;
\r
1762 dws->cur_transfer = NULL;
\r
1763 dws->cur_chip = NULL;
\r
1764 dws->prev_chip = NULL;
\r
1765 spin_unlock_irqrestore(&dws->lock, flags);
\r
1767 queue_work(dws->workqueue, &dws->pump_messages);
\r
1772 static int stop_queue(struct rk29xx_spi *dws)
\r
1774 unsigned long flags;
\r
1775 unsigned limit = 50;
\r
1778 spin_lock_irqsave(&dws->lock, flags);
\r
1779 dws->run = QUEUE_STOPPED;
\r
1780 while (!list_empty(&dws->queue) && dws->busy && limit--) {
\r
1781 spin_unlock_irqrestore(&dws->lock, flags);
\r
1783 spin_lock_irqsave(&dws->lock, flags);
\r
1786 if (!list_empty(&dws->queue) || dws->busy)
\r
1788 spin_unlock_irqrestore(&dws->lock, flags);
\r
1793 static int destroy_queue(struct rk29xx_spi *dws)
\r
1797 status = stop_queue(dws);
\r
1800 destroy_workqueue(dws->workqueue);
\r
1804 /* Restart the controller, disable all interrupts, clean rx fifo */
\r
1805 static void spi_hw_init(struct rk29xx_spi *dws)
\r
1807 spi_enable_chip(dws, 0);
\r
1808 spi_mask_intr(dws, 0xff);
\r
1811 * Try to detect the FIFO depth if not set by interface driver,
\r
1812 * the depth could be from 2 to 32 from HW spec
\r
1814 if (!dws->fifo_len) {
\r
1816 for (fifo = 2; fifo <= 31; fifo++) {
\r
1817 rk29xx_writew(dws, SPIM_TXFTLR, fifo);
\r
1818 if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))
\r
1822 dws->fifo_len = (fifo == 31) ? 0 : fifo;
\r
1823 rk29xx_writew(dws, SPIM_TXFTLR, 0);
\r
1826 spi_enable_chip(dws, 1);
\r
1830 /* cpufreq driver support */
\r
1831 #ifdef CONFIG_CPU_FREQ
\r
1833 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
\r
1835 struct rk29xx_spi *info;
\r
1836 unsigned long newclk;
\r
1838 info = container_of(nb, struct rk29xx_spi, freq_transition);
\r
1839 newclk = clk_get_rate(info->clock_spim);
\r
1844 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)
\r
1846 info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;
\r
1848 return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
\r
1851 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)
\r
1853 cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
\r
1857 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)
\r
1862 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)
\r
1866 static int __init rk29xx_spim_probe(struct platform_device *pdev)
\r
1868 struct resource *regs, *dmatx_res, *dmarx_res;
\r
1869 struct rk29xx_spi *dws;
\r
1870 struct spi_master *master;
\r
1873 struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;
\r
1875 if (pdata && pdata->io_init) {
\r
1876 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);
\r
1882 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1885 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
\r
1886 if (dmatx_res == NULL) {
\r
1887 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
\r
1891 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
\r
1892 if (dmarx_res == NULL) {
\r
1893 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
\r
1896 irq = platform_get_irq(pdev, 0);
\r
1899 /* setup spi core then atmel-specific driver state */
\r
1901 master = spi_alloc_master(&pdev->dev, sizeof *dws);
\r
1907 platform_set_drvdata(pdev, master);
\r
1908 dws = spi_master_get_devdata(master);
\r
1909 dws->clock_spim = clk_get(&pdev->dev, "spi");
\r
1910 clk_enable(dws->clock_spim);
\r
1911 if (IS_ERR(dws->clock_spim)) {
\r
1912 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);
\r
1913 return PTR_ERR(dws->clock_spim);
\r
1916 mutex_init(&dws->dma_lock);
\r
1918 dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
\r
1920 release_mem_region(regs->start, (regs->end - regs->start) + 1);
\r
1923 DBG(KERN_INFO "dws->regs: %p\n", dws->regs);
\r
1925 dws->irq_polarity = IRQF_TRIGGER_NONE;
\r
1926 dws->master = master;
\r
1927 dws->type = SSI_MOTO_SPI;
\r
1928 dws->prev_chip = NULL;
\r
1929 dws->sfr_start = regs->start;
\r
1930 dws->tx_dmach = dmatx_res->start;
\r
1931 dws->rx_dmach = dmarx_res->start;
\r
1932 dws->dma_inited = 0; ///0;
\r
1933 ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
\r
1934 ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,
\r
1935 "rk29xx_spim", dws);
\r
1937 dev_err(&master->dev, "can not get IRQ\n");
\r
1938 goto err_free_master;
\r
1941 master->mode_bits = SPI_CPOL | SPI_CPHA;
\r
1942 master->bus_num = pdev->id;
\r
1943 master->num_chipselect = pdata->num_chipselect;
\r
1944 master->dev.platform_data = pdata;
\r
1945 master->cleanup = rk29xx_spi_cleanup;
\r
1946 master->setup = rk29xx_spi_setup;
\r
1947 #if defined(QUICK_TRANSFER)
\r
1948 master->transfer = rk29xx_spi_quick_transfer;
\r
1950 master->transfer = rk29xx_spi_transfer;
\r
1954 /* Basic HW init */
\r
1957 /* Initial and start queue */
\r
1958 ret = init_queue(dws);
\r
1960 dev_err(&master->dev, "problem initializing queue\n");
\r
1961 goto err_diable_hw;
\r
1964 ret = start_queue(dws);
\r
1966 dev_err(&master->dev, "problem starting queue\n");
\r
1967 goto err_diable_hw;
\r
1970 spi_master_set_devdata(master, dws);
\r
1971 ret = spi_register_master(master);
\r
1973 dev_err(&master->dev, "problem registering spi master\n");
\r
1974 goto err_queue_alloc;
\r
1977 ret =rk29xx_spim_cpufreq_register(dws);
\r
1979 dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");
\r
1980 goto err_queue_alloc;
\r
1982 printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);
\r
1983 mrst_spi_debugfs_init(dws);
\r
1987 destroy_queue(dws);
\r
1989 spi_enable_chip(dws, 0);
\r
1990 free_irq(dws->irq, dws);
\r
1992 spi_master_put(master);
\r
1993 iounmap(dws->regs);
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1998 static void __exit rk29xx_spim_remove(struct platform_device *pdev)
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2000 struct spi_master *master = platform_get_drvdata(pdev);
\r
2001 struct rk29xx_spi *dws = spi_master_get_devdata(master);
\r
2006 rk29xx_spim_cpufreq_deregister(dws);
\r
2007 mrst_spi_debugfs_remove(dws);
\r
2009 if(dws->buffer_tx_dma)
\r
2010 dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);
\r
2011 if(dws->buffer_rx_dma)
\r
2012 dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);
\r
2015 /* Remove the queue */
\r
2016 status = destroy_queue(dws);
\r
2018 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "
\r
2019 "complete, message memory not freed\n");
\r
2020 clk_put(dws->clock_spim);
\r
2021 clk_disable(dws->clock_spim);
\r
2022 spi_enable_chip(dws, 0);
\r
2024 spi_set_clk(dws, 0);
\r
2025 free_irq(dws->irq, dws);
\r
2027 /* Disconnect from the SPI framework */
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2028 spi_unregister_master(dws->master);
\r
2029 iounmap(dws->regs);
\r
2035 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)
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2037 struct spi_master *master = platform_get_drvdata(pdev);
\r
2038 struct rk29xx_spi *dws = spi_master_get_devdata(master);
\r
2039 struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;
\r
2043 status = stop_queue(dws);
\r
2046 clk_disable(dws->clock_spim);
\r
2047 if (pdata && pdata->io_fix_leakage_bug)
\r
2049 pdata->io_fix_leakage_bug( );
\r
2054 static int rk29xx_spim_resume(struct platform_device *pdev)
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2056 struct spi_master *master = platform_get_drvdata(pdev);
\r
2057 struct rk29xx_spi *dws = spi_master_get_devdata(master);
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2058 struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;
\r
2061 clk_enable(dws->clock_spim);
\r
2063 ret = start_queue(dws);
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2065 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
\r
2066 if (pdata && pdata->io_resume_leakage_bug)
\r
2068 pdata->io_resume_leakage_bug( );
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2074 #define rk29xx_spim_suspend NULL
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2075 #define rk29xx_spim_resume NULL
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2078 static struct platform_driver rk29xx_platform_spim_driver = {
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2079 .remove = __exit_p(rk29xx_spim_remove),
\r
2081 .name = "rk29xx_spim",
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2082 .owner = THIS_MODULE,
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2084 .suspend = rk29xx_spim_suspend,
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2085 .resume = rk29xx_spim_resume,
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2088 static int __init rk29xx_spim_init(void)
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2091 ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);
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2095 static void __exit rk29xx_spim_exit(void)
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2097 platform_driver_unregister(&rk29xx_platform_spim_driver);
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2100 arch_initcall_sync(rk29xx_spim_init);
\r
2101 module_exit(rk29xx_spim_exit);
\r
2103 MODULE_AUTHOR("www.rock-chips.com");
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2104 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");
\r
2105 MODULE_LICENSE("GPL");;
\r