drivers/spi/rk29_spim.c

   1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device \r
   2  *\r
   3  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   4  *\r
   5  * This software is licensed under the terms of the GNU General Public\r
   6  * License version 2, as published by the Free Software Foundation, and\r
   7  * may be copied, distributed, and modified under those terms.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful,\r
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  12  * GNU General Public License for more details.\r
  13  */\r
  14 \r
  15 #include <linux/dma-mapping.h>\r
  16 #include <linux/interrupt.h>\r
  17 #include <linux/highmem.h>\r
  18 #include <linux/delay.h>\r
  19 #include <linux/slab.h>\r
  20 #include <linux/platform_device.h>\r
  21 #include <linux/clk.h>\r
  22 #include <linux/cpufreq.h>\r
  23 #include <mach/gpio.h>\r
  24 #include <mach/irqs.h>\r
  25 #include <linux/dma-mapping.h>\r
  26 #include <asm/dma.h>\r
  27 #include <linux/preempt.h>\r
  28 #include "rk29_spim.h"\r
  29 #include <linux/spi/spi.h>\r
  30 #include <mach/board.h>\r
  31 \r
  32 #ifdef CONFIG_DEBUG_FS\r
  33 #include <linux/debugfs.h>\r
  34 #endif\r
  35 \r
  36 /*ÔÓÐµÄspiÇý¶¯Ð§ÂÊ±È½ÏµÍ£¬\r
  37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Êä£»\r
  38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Êä£¬Í¬Ê±¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬\r
  39 Ä¬ÈÏÊ¹ÓÃ°ëË«¹¤\r
  40 */\r
  41 \r
  42 //#define QUICK_TRANSFER         \r
  43 \r
  44 #if 0\r
  45 #define DBG   printk\r
  46 #else\r
  47 #define DBG(x...)\r
  48 #endif\r
  49 \r
  50 #define DMA_BUFFER_SIZE PAGE_SIZE\r
  51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO\r
  52 \r
  53 \r
  54 #define START_STATE     ((void *)0)\r
  55 #define RUNNING_STATE   ((void *)1)\r
  56 #define DONE_STATE      ((void *)2)\r
  57 #define ERROR_STATE     ((void *)-1)\r
  58 \r
  59 #define QUEUE_RUNNING   0\r
  60 #define QUEUE_STOPPED   1\r
  61 \r
  62 #define MRST_SPI_DEASSERT       0\r
  63 #define MRST_SPI_ASSERT         1  ///CS0\r
  64 #define MRST_SPI_ASSERT1        2  ///CS1\r
  65 \r
  66 /* Slave spi_dev related */\r
  67 struct chip_data {\r
  68         u16 cr0;\r
  69         u8 cs;                  /* chip select pin */\r
  70         u8 n_bytes;             /* current is a 1/2/4 byte op */\r
  71         u8 tmode;               /* TR/TO/RO/EEPROM */\r
  72         u8 type;                /* SPI/SSP/MicroWire */\r
  73 \r
  74         u8 poll_mode;           /* 1 means use poll mode */\r
  75 \r
  76         u32 dma_width;\r
  77         u32 rx_threshold;\r
  78         u32 tx_threshold;\r
  79         u8 enable_dma:1;\r
  80         u8 bits_per_word;\r
  81         u16 clk_div;            /* baud rate divider */\r
  82         u32 speed_hz;           /* baud rate */\r
  83         int (*write)(struct rk29xx_spi *dws);\r
  84         int (*read)(struct rk29xx_spi *dws);\r
  85         void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);\r
  86 };\r
  87 \r
  88 #define SUSPND    (1<<0)\r
  89 #define SPIBUSY   (1<<1)\r
  90 #define RXBUSY    (1<<2)\r
  91 #define TXBUSY    (1<<3)\r
  92 \r
  93 //\r
  94 #ifdef CONFIG_LCD_USE_SPIM_CONTROL\r
  95 void rk29_lcd_spim_spin_lock(void)\r
  96 {\r
  97 #ifdef CONFIG_LCD_USE_SPI0\r
  98         disable_irq(IRQ_SPI0);\r
  99 #endif\r
 100 \r
 101 #ifdef CONFIG_LCD_USE_SPI1\r
 102         disable_irq(IRQ_SPI1);\r
 103 #endif\r
 104 \r
 105         preempt_disable();\r
 106 }\r
 107 \r
 108 void rk29_lcd_spim_spin_unlock(void)\r
 109 {\r
 110         preempt_enable();\r
 111         \r
 112 #ifdef CONFIG_LCD_USE_SPI0\r
 113         enable_irq(IRQ_SPI0);\r
 114 #endif\r
 115 \r
 116 #ifdef CONFIG_LCD_USE_SPI1\r
 117         enable_irq(IRQ_SPI1);\r
 118 #endif\r
 119 }\r
 120 #else\r
 121 void rk29_lcd_spim_spin_lock(void)\r
 122 {\r
 123      return;\r
 124 }\r
 125 \r
 126 void rk29_lcd_spim_spin_unlock(void)\r
 127 {\r
 128      return;\r
 129 }\r
 130 #endif\r
 131 \r
 132 \r
 133 static void spi_dump_regs(struct rk29xx_spi *dws) {\r
 134         DBG("MRST SPI0 registers:\n");\r
 135         DBG("=================================\n");\r
 136         DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 137         DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 138         DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 139         DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 140         DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 141         DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 142         DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 143         DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 144         DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 145         DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 146         DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 147         DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 148         DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 149         DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 150         DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 151         DBG("=================================\n");\r
 152 \r
 153 }\r
 154 \r
 155 #ifdef CONFIG_DEBUG_FS\r
 156 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 157 {\r
 158         file->private_data = inode->i_private;\r
 159         return 0;\r
 160 }\r
 161 \r
 162 #define SPI_REGS_BUFSIZE        1024\r
 163 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,\r
 164                                 size_t count, loff_t *ppos)\r
 165 {\r
 166         struct rk29xx_spi *dws;\r
 167         char *buf;\r
 168         u32 len = 0;\r
 169         ssize_t ret;\r
 170 \r
 171         dws = file->private_data;\r
 172 \r
 173         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);\r
 174         if (!buf)\r
 175                 return 0;\r
 176 \r
 177         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 178                         "MRST SPI0 registers:\n");\r
 179         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 180                         "=================================\n");\r
 181         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 182                         "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 183         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 184                         "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 185         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 186                         "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 187         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 188                         "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 189         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 190                         "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 191         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 192                         "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 193         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 194                         "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 195         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 196                         "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 197         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 198                         "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 199         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 200                         "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 201         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 202                         "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 203         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 204                         "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 205         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 206                         "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 207         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 208                         "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 209         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 210                         "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 211         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 212                         "=================================\n");\r
 213 \r
 214         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);\r
 215         kfree(buf);\r
 216         return ret;\r
 217 }\r
 218 \r
 219 static const struct file_operations mrst_spi_regs_ops = {\r
 220         .owner          = THIS_MODULE,\r
 221         .open           = spi_show_regs_open,\r
 222         .read           = spi_show_regs,\r
 223 };\r
 224 \r
 225 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 226 {\r
 227         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);\r
 228         if (!dws->debugfs)\r
 229                 return -ENOMEM;\r
 230 \r
 231         debugfs_create_file("registers", S_IFREG | S_IRUGO,\r
 232                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);\r
 233         return 0;\r
 234 }\r
 235 \r
 236 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 237 {\r
 238         if (dws->debugfs)\r
 239                 debugfs_remove_recursive(dws->debugfs);\r
 240 }\r
 241 \r
 242 #else\r
 243 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 244 {\r
 245         return 0;\r
 246 }\r
 247 \r
 248 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 249 {\r
 250 }\r
 251 #endif /* CONFIG_DEBUG_FS */\r
 252 \r
 253 static void dma_transfer(struct rk29xx_spi *dws) ;\r
 254 static void transfer_complete(struct rk29xx_spi *dws);\r
 255 \r
 256 static void wait_till_not_busy(struct rk29xx_spi *dws)\r
 257 {\r
 258         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 259 \r
 260         while (time_before(jiffies, end)) {\r
 261                 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
 262                         return;\r
 263         }\r
 264         dev_err(&dws->master->dev,\r
 265                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 266 }\r
 267 \r
 268 #if defined(QUICK_TRANSFER)\r
 269 static void wait_till_tf_empty(struct rk29xx_spi *dws)\r
 270 {\r
 271         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 272 \r
 273         while (time_before(jiffies, end)) {\r
 274                 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)\r
 275                         return;\r
 276         }\r
 277         dev_err(&dws->master->dev,\r
 278                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 279 }\r
 280 #endif\r
 281 \r
 282 static void flush(struct rk29xx_spi *dws)\r
 283 {\r
 284         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 285                 rk29xx_readw(dws, SPIM_RXDR);\r
 286 \r
 287         wait_till_not_busy(dws);\r
 288 }\r
 289 \r
 290 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 291 {\r
 292         #if 1\r
 293         if (flag)\r
 294                 rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 295         else            \r
 296                 rk29xx_writel(dws, SPIM_SER, 0);\r
 297         return;\r
 298         #else\r
 299         struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
 300         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 301 \r
 302         if (flag == 0) {\r
 303                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
 304         }\r
 305         else {\r
 306                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
 307         }\r
 308         #endif\r
 309 }\r
 310 \r
 311 static int null_writer(struct rk29xx_spi *dws)\r
 312 {\r
 313         u8 n_bytes = dws->n_bytes;\r
 314 \r
 315         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 316                 || (dws->tx == dws->tx_end))\r
 317                 return 0;\r
 318         rk29xx_writew(dws, SPIM_TXDR, 0);\r
 319         dws->tx += n_bytes;\r
 320         //wait_till_not_busy(dws);\r
 321 \r
 322         return 1;\r
 323 }\r
 324 \r
 325 static int null_reader(struct rk29xx_spi *dws)\r
 326 {\r
 327         u8 n_bytes = dws->n_bytes;\r
 328         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 329         while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 330                 && (dws->rx < dws->rx_end)) {\r
 331                 rk29xx_readw(dws, SPIM_RXDR);\r
 332                 dws->rx += n_bytes;\r
 333         }\r
 334         wait_till_not_busy(dws);\r
 335         return dws->rx == dws->rx_end;\r
 336 }\r
 337 \r
 338 static int u8_writer(struct rk29xx_spi *dws)\r
 339 {       \r
 340         spi_dump_regs(dws);\r
 341         DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
 342         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 343                 || (dws->tx == dws->tx_end))\r
 344                 return 0;\r
 345         rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));\r
 346         ++dws->tx;\r
 347         //wait_till_not_busy(dws);\r
 348 \r
 349         return 1;\r
 350 }\r
 351 \r
 352 static int u8_reader(struct rk29xx_spi *dws)\r
 353 {\r
 354     spi_dump_regs(dws);\r
 355         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 356                 && (dws->rx < dws->rx_end)) {\r
 357                 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;\r
 358                 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));\r
 359                 ++dws->rx;\r
 360         }\r
 361 \r
 362         wait_till_not_busy(dws);\r
 363         return dws->rx == dws->rx_end;\r
 364 }\r
 365 \r
 366 static int u16_writer(struct rk29xx_spi *dws)\r
 367 {\r
 368         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 369                 || (dws->tx == dws->tx_end))\r
 370                 return 0;\r
 371 \r
 372         rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));\r
 373         dws->tx += 2;\r
 374         //wait_till_not_busy(dws);\r
 375 \r
 376         return 1;\r
 377 }\r
 378 \r
 379 static int u16_reader(struct rk29xx_spi *dws)\r
 380 {\r
 381         u16 temp;\r
 382 \r
 383         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 384                 && (dws->rx < dws->rx_end)) {\r
 385                 temp = rk29xx_readw(dws, SPIM_RXDR);\r
 386                 *(u16 *)(dws->rx) = temp;\r
 387                 //DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));\r
 388                 dws->rx += 2;\r
 389         }\r
 390 \r
 391         wait_till_not_busy(dws);\r
 392         return dws->rx == dws->rx_end;\r
 393 }\r
 394 \r
 395 static void *next_transfer(struct rk29xx_spi *dws)\r
 396 {\r
 397         struct spi_message *msg = dws->cur_msg;\r
 398         struct spi_transfer *trans = dws->cur_transfer;\r
 399 \r
 400         /* Move to next transfer */\r
 401         if (trans->transfer_list.next != &msg->transfers) {\r
 402                 dws->cur_transfer =\r
 403                         list_entry(trans->transfer_list.next,\r
 404                                         struct spi_transfer,\r
 405                                         transfer_list);\r
 406                 return RUNNING_STATE;\r
 407         } else\r
 408                 return DONE_STATE;\r
 409 }\r
 410 \r
 411 static void rk29_spi_dma_rxcb(void *buf_id,\r
 412                                  int size, enum rk29_dma_buffresult res)\r
 413 {\r
 414         struct rk29xx_spi *dws = buf_id;\r
 415         unsigned long flags;\r
 416 \r
 417         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 418         \r
 419         spin_lock_irqsave(&dws->lock, flags);\r
 420 \r
 421         if (res == RK29_RES_OK)\r
 422                 dws->state &= ~RXBUSY;\r
 423         else\r
 424                 dev_err(&dws->master->dev, "DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);\r
 425 \r
 426         /* If the other done */\r
 427         //if (!(dws->state & TXBUSY))\r
 428         //      complete(&dws->rx_completion);\r
 429         \r
 430         spin_unlock_irqrestore(&dws->lock, flags);\r
 431         \r
 432         //DMA could not lose intterupt\r
 433         transfer_complete(dws);\r
 434 \r
 435 }\r
 436 \r
 437 static void rk29_spi_dma_txcb(void *buf_id,\r
 438                                  int size, enum rk29_dma_buffresult res)\r
 439 {\r
 440         struct rk29xx_spi *dws = buf_id;\r
 441         unsigned long flags;\r
 442 \r
 443         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 444         \r
 445         spin_lock_irqsave(&dws->lock, flags);\r
 446 \r
 447         if (res == RK29_RES_OK)\r
 448                 dws->state &= ~TXBUSY;\r
 449         else\r
 450                 dev_err(&dws->master->dev, "DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);\r
 451 \r
 452         /* If the other done */\r
 453         //if (!(dws->state & RXBUSY)) \r
 454         //      complete(&dws->tx_completion);\r
 455 \r
 456         spin_unlock_irqrestore(&dws->lock, flags);\r
 457         \r
 458         //DMA could not lose intterupt\r
 459         transfer_complete(dws);\r
 460 \r
 461 }\r
 462 \r
 463 \r
 464 static struct rk29_dma_client rk29_spi_dma_client = {\r
 465         .name = "rk29xx-spi-dma",\r
 466 };\r
 467 \r
 468 static int acquire_dma(struct rk29xx_spi *dws)\r
 469 {       \r
 470         if (dws->dma_inited) {\r
 471                 return 0;\r
 472         }\r
 473 \r
 474         dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);\r
 475         if (!dws->buffer_tx_dma)\r
 476         {\r
 477                 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");\r
 478                 return -1;\r
 479         }\r
 480 \r
 481         dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);\r
 482         if (!dws->buffer_rx_dma)\r
 483         {\r
 484                 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");\r
 485                 return -1;\r
 486         }\r
 487 \r
 488         if(rk29_dma_request(dws->rx_dmach, \r
 489                 &rk29_spi_dma_client, NULL) < 0) {\r
 490                 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);\r
 491                 return -1;\r
 492         }\r
 493 \r
 494         if (rk29_dma_request(dws->tx_dmach,\r
 495                                         &rk29_spi_dma_client, NULL) < 0) {\r
 496                 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);\r
 497                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 498                 return -1;\r
 499         }\r
 500 \r
 501         if (dws->tx_dma) {\r
 502                 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {\r
 503                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 504                         return -1;\r
 505                 }\r
 506                 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
 507                                         dws->sfr_start + SPIM_TXDR)) {\r
 508                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 509                         return -1;\r
 510                 }\r
 511         }\r
 512 \r
 513         if (dws->rx_dma) {\r
 514                 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {\r
 515                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 516                         return -1;\r
 517                 }\r
 518                 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
 519                                         dws->sfr_start + SPIM_RXDR)) {\r
 520                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 521                         return -1;\r
 522                 }\r
 523         }\r
 524         \r
 525         dws->dma_inited = 1;\r
 526         return 0;\r
 527 }\r
 528 \r
 529 static void release_dma(struct rk29xx_spi *dws)\r
 530 {\r
 531         if(!dws && dws->dma_inited) {\r
 532                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 533                 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);\r
 534         }\r
 535 }\r
 536 \r
 537 /*\r
 538  * Note: first step is the protocol driver prepares\r
 539  * a dma-capable memory, and this func just need translate\r
 540  * the virt addr to physical\r
 541  */\r
 542 static int map_dma_buffers(struct rk29xx_spi *dws)\r
 543 {\r
 544         if (!dws->dma_inited || !dws->cur_chip->enable_dma)\r
 545         {\r
 546                 printk("%s:error\n",__func__);\r
 547                 return -1;\r
 548         }\r
 549 \r
 550         if(dws->cur_transfer->tx_buf)\r
 551         {\r
 552                 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);\r
 553                 dws->cur_transfer->tx_buf = dws->buffer_tx_dma; \r
 554         }\r
 555 \r
 556         if(dws->cur_transfer->rx_buf)\r
 557         {\r
 558                 //memcpy(dws->buffer_rx_dma,dws->cur_transfer->rx_buf,dws->cur_transfer->len);\r
 559                 dws->cur_transfer->rx_buf = dws->buffer_rx_dma; \r
 560         }\r
 561         \r
 562         dws->cur_transfer->tx_dma = dws->tx_dma;\r
 563         dws->cur_transfer->rx_dma = dws->rx_dma;\r
 564         \r
 565         return 0;\r
 566 }\r
 567 \r
 568 /* Caller already set message->status; dma and pio irqs are blocked */\r
 569 static void giveback(struct rk29xx_spi *dws)\r
 570 {\r
 571         struct spi_transfer *last_transfer;\r
 572         unsigned long flags;\r
 573         struct spi_message *msg;\r
 574 \r
 575         spin_lock_irqsave(&dws->lock, flags);\r
 576         msg = dws->cur_msg;\r
 577         dws->cur_msg = NULL;\r
 578         dws->cur_transfer = NULL;\r
 579         dws->prev_chip = dws->cur_chip;\r
 580         dws->cur_chip = NULL;\r
 581         dws->dma_mapped = 0;\r
 582         \r
 583         /*it is important to close intterrupt*/\r
 584         spi_umask_intr(dws, 0);\r
 585         rk29xx_writew(dws, SPIM_DMACR, 0);\r
 586         \r
 587         queue_work(dws->workqueue, &dws->pump_messages);\r
 588         spin_unlock_irqrestore(&dws->lock, flags);\r
 589 \r
 590         last_transfer = list_entry(msg->transfers.prev,\r
 591                                         struct spi_transfer,\r
 592                                         transfer_list);\r
 593 \r
 594         if (!last_transfer->cs_change && dws->cs_control)\r
 595                 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 596 \r
 597         msg->state = NULL;\r
 598         if (msg->complete)\r
 599                 msg->complete(msg->context);\r
 600 \r
 601 }\r
 602 \r
 603 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)\r
 604 {\r
 605         /* Stop and reset hw */\r
 606         flush(dws);\r
 607         spi_enable_chip(dws, 0);\r
 608 \r
 609         dev_err(&dws->master->dev, "%s\n", msg);\r
 610         dws->cur_msg->state = ERROR_STATE;\r
 611         tasklet_schedule(&dws->pump_transfers);\r
 612 }\r
 613 \r
 614 static void transfer_complete(struct rk29xx_spi *dws)\r
 615 {\r
 616         /* Update total byte transfered return count actual bytes read */\r
 617         dws->cur_msg->actual_length += dws->len;\r
 618 \r
 619         /* Move to next transfer */\r
 620         dws->cur_msg->state = next_transfer(dws);\r
 621 \r
 622         /* Handle end of message */\r
 623         if (dws->cur_msg->state == DONE_STATE) {\r
 624                 dws->cur_msg->status = 0;\r
 625                 giveback(dws);\r
 626         } else\r
 627                 tasklet_schedule(&dws->pump_transfers);\r
 628 }\r
 629 \r
 630 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 631 {\r
 632         u16 irq_status, irq_mask = 0x1f;\r
 633         u32 int_level = dws->fifo_len / 2;\r
 634         u32 left;\r
 635 \r
 636         irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;\r
 637         /* Error handling */\r
 638         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {\r
 639                 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);\r
 640                 int_error_stop(dws, "interrupt_transfer: fifo overrun");\r
 641                 mutex_unlock(&dws->dma_lock);   \r
 642                 return IRQ_HANDLED;\r
 643         }\r
 644 \r
 645         if (irq_status & SPI_INT_TXEI) {\r
 646                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 647 \r
 648                 left = (dws->tx_end - dws->tx) / dws->n_bytes;\r
 649                 left = (left > int_level) ? int_level : left;\r
 650 \r
 651                 while (left--) {\r
 652                         dws->write(dws);\r
 653                         wait_till_not_busy(dws);\r
 654                 }\r
 655                 if (dws->rx) {\r
 656                     dws->read(dws);\r
 657                 }\r
 658 \r
 659                 /* Re-enable the IRQ if there is still data left to tx */\r
 660                 if (dws->tx_end > dws->tx)\r
 661                         spi_umask_intr(dws, SPI_INT_TXEI);\r
 662                 else\r
 663                         transfer_complete(dws);\r
 664         }\r
 665 \r
 666         if (irq_status & SPI_INT_RXFI) {\r
 667                 spi_mask_intr(dws, SPI_INT_RXFI);\r
 668                 \r
 669                 dws->read(dws);\r
 670 \r
 671                 /* Re-enable the IRQ if there is still data left to rx */\r
 672                 if (dws->rx_end > dws->rx) {\r
 673                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;\r
 674                     left = (left > int_level) ? int_level : left;\r
 675 \r
 676                         rk29xx_writew(dws, SPIM_RXFTLR, left);\r
 677                         spi_umask_intr(dws, SPI_INT_RXFI);\r
 678                 }\r
 679                 else {\r
 680                         transfer_complete(dws);\r
 681                 }\r
 682                 \r
 683         }       \r
 684 \r
 685         return IRQ_HANDLED;\r
 686 }\r
 687 \r
 688 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)\r
 689 {\r
 690         struct rk29xx_spi *dws = dev_id;\r
 691 \r
 692         if (!dws->cur_msg) {\r
 693                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 694                 /* Never fail */\r
 695                 return IRQ_HANDLED;\r
 696         }\r
 697 \r
 698         return dws->transfer_handler(dws);\r
 699 }\r
 700 \r
 701 /* Must be called inside pump_transfers() */\r
 702 static void poll_transfer(struct rk29xx_spi *dws)\r
 703 {\r
 704         DBG("%s\n",__func__);\r
 705         while (dws->write(dws)) {\r
 706                 wait_till_not_busy(dws);\r
 707                 dws->read(dws);\r
 708         }\r
 709         transfer_complete(dws);\r
 710 }\r
 711 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)\r
 712 {\r
 713     if(cs >= dws->master->num_chipselect)\r
 714                 return;\r
 715 \r
 716         if (dws->cs_control){\r
 717             dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
 718         }\r
 719         rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 720 }\r
 721 \r
 722 static void pump_transfers(unsigned long data)\r
 723 {\r
 724         struct rk29xx_spi *dws = (struct rk29xx_spi *)data;\r
 725         struct spi_message *message = NULL;\r
 726         struct spi_transfer *transfer = NULL;\r
 727         struct spi_transfer *previous = NULL;\r
 728         struct spi_device *spi = NULL;\r
 729         struct chip_data *chip = NULL;\r
 730         u8 bits = 0;\r
 731         u8 spi_dfs = 0;\r
 732         u8 imask = 0;\r
 733         u8 cs_change = 0;\r
 734         u16 txint_level = 0;\r
 735         u16 rxint_level = 0;\r
 736         u16 clk_div = 0;\r
 737         u32 speed = 0;\r
 738         u32 cr0 = 0;\r
 739 \r
 740         if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){      \r
 741                 dma_transfer(dws);\r
 742                 return;\r
 743         }       \r
 744         \r
 745         DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);\r
 746 \r
 747         /* Get current state information */\r
 748         message = dws->cur_msg;\r
 749         transfer = dws->cur_transfer;\r
 750         chip = dws->cur_chip;\r
 751         spi = message->spi;     \r
 752         if (unlikely(!chip->clk_div))\r
 753                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 754         if (message->state == ERROR_STATE) {\r
 755                 message->status = -EIO;\r
 756                 goto early_exit;\r
 757         }\r
 758 \r
 759         /* Handle end of message */\r
 760         if (message->state == DONE_STATE) {\r
 761                 message->status = 0;\r
 762                 goto early_exit;\r
 763         }\r
 764 \r
 765         /* Delay if requested at end of transfer*/\r
 766         if (message->state == RUNNING_STATE) {\r
 767                 previous = list_entry(transfer->transfer_list.prev,\r
 768                                         struct spi_transfer,\r
 769                                         transfer_list);\r
 770                 if (previous->delay_usecs)\r
 771                         udelay(previous->delay_usecs);\r
 772         }\r
 773 \r
 774         dws->n_bytes = chip->n_bytes;\r
 775         dws->dma_width = chip->dma_width;\r
 776         dws->cs_control = chip->cs_control;\r
 777 \r
 778         //dws->rx_dma = transfer->rx_dma;\r
 779         //dws->tx_dma = transfer->tx_dma;\r
 780         dws->tx = (void *)transfer->tx_buf;\r
 781         dws->tx_end = dws->tx + transfer->len;\r
 782         dws->rx = (void *)transfer->rx_buf;\r
 783         dws->rx_end = dws->rx + transfer->len;\r
 784         dws->write = dws->tx ? chip->write : null_writer;\r
 785         dws->read = dws->rx ? chip->read : null_reader;\r
 786         dws->cs_change = transfer->cs_change;\r
 787         dws->len = dws->cur_transfer->len;\r
 788         if (chip != dws->prev_chip)\r
 789                 cs_change = 1;\r
 790 \r
 791         cr0 = chip->cr0;\r
 792 \r
 793         /* Handle per transfer options for bpw and speed */\r
 794         if (transfer->speed_hz) {\r
 795                 speed = chip->speed_hz;\r
 796 \r
 797                 if (transfer->speed_hz != speed) {\r
 798                         speed = transfer->speed_hz;\r
 799                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 800                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
 801                                         "freq: %dHz\n", speed);\r
 802                                 message->status = -EIO;\r
 803                                 goto early_exit;\r
 804                         }\r
 805 \r
 806                         /* clk_div doesn't support odd number */\r
 807                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 808                         clk_div = (clk_div + 1) & 0xfffe;\r
 809 \r
 810                         chip->speed_hz = speed;\r
 811                         chip->clk_div = clk_div;\r
 812                 }\r
 813         }\r
 814         \r
 815         if (transfer->bits_per_word) {\r
 816                 bits = transfer->bits_per_word;\r
 817 \r
 818                 switch (bits) {\r
 819                 case 8:\r
 820                         dws->n_bytes = 1;\r
 821                         dws->dma_width = 1;\r
 822                         dws->read = (dws->read != null_reader) ?\r
 823                                         u8_reader : null_reader;\r
 824                         dws->write = (dws->write != null_writer) ?\r
 825                                         u8_writer : null_writer;\r
 826                         spi_dfs = SPI_DFS_8BIT;\r
 827                         break;\r
 828                 case 16:\r
 829                         dws->n_bytes = 2;\r
 830                         dws->dma_width = 2;\r
 831                         dws->read = (dws->read != null_reader) ?\r
 832                                         u16_reader : null_reader;\r
 833                         dws->write = (dws->write != null_writer) ?\r
 834                                         u16_writer : null_writer;\r
 835                         spi_dfs = SPI_DFS_16BIT;\r
 836                         break;\r
 837                 default:\r
 838                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 839                                 "%db\n", bits);\r
 840                         message->status = -EIO;\r
 841                         goto early_exit;\r
 842                 }\r
 843 \r
 844                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 845                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 846                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 847                         | (chip->type << SPI_FRF_OFFSET)\r
 848                         | (spi->mode << SPI_MODE_OFFSET)\r
 849                         | (chip->tmode << SPI_TMOD_OFFSET);\r
 850         }\r
 851         message->state = RUNNING_STATE;\r
 852  \r
 853         /*\r
 854          * Adjust transfer mode if necessary. Requires platform dependent\r
 855          * chipselect mechanism.\r
 856          */\r
 857         if (dws->cs_control) {\r
 858                 if (dws->rx && dws->tx)\r
 859                         chip->tmode = SPI_TMOD_TR;\r
 860                 else if (dws->rx)\r
 861                         chip->tmode = SPI_TMOD_RO;\r
 862                 else\r
 863                         chip->tmode = SPI_TMOD_TO;\r
 864 \r
 865                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
 866                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
 867         } \r
 868 \r
 869         /*\r
 870          * Interrupt mode\r
 871          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely\r
 872          */\r
 873         if (!dws->dma_mapped && !chip->poll_mode) {     \r
 874                 int templen ;\r
 875                 \r
 876                 if (chip->tmode == SPI_TMOD_RO) {\r
 877                         templen = dws->len / dws->n_bytes - 1;\r
 878                         rxint_level = dws->fifo_len / 2;\r
 879                         rxint_level = (templen > rxint_level) ? rxint_level : templen;\r
 880                         imask |= SPI_INT_RXFI;\r
 881                 }\r
 882                 else {  \r
 883                         templen = dws->len / dws->n_bytes;\r
 884                         txint_level = dws->fifo_len / 2;\r
 885                         txint_level = (templen > txint_level) ? txint_level : templen;\r
 886                         imask |= SPI_INT_TXEI;\r
 887                 }\r
 888                 dws->transfer_handler = interrupt_transfer;\r
 889         }\r
 890 \r
 891         /*\r
 892          * Reprogram registers only if\r
 893          *      1. chip select changes\r
 894          *      2. clk_div is changed\r
 895          *      3. control value changes\r
 896          */\r
 897         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {\r
 898                 spi_enable_chip(dws, 0);\r
 899                 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)\r
 900                         rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
 901 \r
 902                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
 903                 spi_chip_sel(dws, spi->chip_select);\r
 904 \r
 905         rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
 906                 spi_enable_chip(dws, 1);\r
 907 \r
 908                 if (txint_level)\r
 909                         rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
 910                 if (rxint_level)\r
 911                         rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
 912                 /* Set the interrupt mask, for poll mode just diable all int */\r
 913                 spi_mask_intr(dws, 0xff);\r
 914                 if (imask)\r
 915                         spi_umask_intr(dws, imask);\r
 916                 \r
 917                 if (cs_change)\r
 918                         dws->prev_chip = chip;\r
 919         } \r
 920 \r
 921         if (chip->poll_mode)\r
 922                 poll_transfer(dws);\r
 923 \r
 924         return;\r
 925 \r
 926 early_exit:\r
 927         giveback(dws);\r
 928         return;\r
 929 }\r
 930 \r
 931 static void dma_transfer(struct rk29xx_spi *dws) \r
 932 {\r
 933         struct spi_message *message = NULL;\r
 934         struct spi_transfer *transfer = NULL;\r
 935         struct spi_transfer *previous = NULL;\r
 936         struct spi_device *spi = NULL;\r
 937         struct chip_data *chip = NULL;\r
 938         //unsigned long val;    \r
 939         //unsigned long flags;\r
 940         //int ms;\r
 941         int iRet;\r
 942         //int burst;\r
 943         u8 bits = 0;\r
 944         u8 spi_dfs = 0;\r
 945         u8 cs_change = 0;\r
 946         u16 clk_div = 0;\r
 947         u32 speed = 0;\r
 948         u32 cr0 = 0;\r
 949         u32 dmacr = 0;\r
 950         \r
 951         DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);  \r
 952         \r
 953         if (acquire_dma(dws)) {\r
 954                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 955                 goto err_out;\r
 956         }\r
 957 \r
 958         if (map_dma_buffers(dws)) {\r
 959                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 960                 goto err_out;\r
 961         }\r
 962 \r
 963         /* Get current state information */\r
 964         message = dws->cur_msg;\r
 965         transfer = dws->cur_transfer;\r
 966         chip = dws->cur_chip;\r
 967         spi = message->spi;     \r
 968         if (unlikely(!chip->clk_div))\r
 969                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 970         if (message->state == ERROR_STATE) {\r
 971                 message->status = -EIO;\r
 972                 goto err_out;\r
 973         }\r
 974 \r
 975         /* Handle end of message */\r
 976         if (message->state == DONE_STATE) {\r
 977                 message->status = 0;\r
 978                 goto err_out;\r
 979         }\r
 980 \r
 981         /* Delay if requested at end of transfer*/\r
 982         if (message->state == RUNNING_STATE) {\r
 983                 previous = list_entry(transfer->transfer_list.prev,\r
 984                                         struct spi_transfer,\r
 985                                         transfer_list);\r
 986                 if (previous->delay_usecs)\r
 987                         udelay(previous->delay_usecs);\r
 988         }\r
 989 \r
 990         dws->n_bytes = chip->n_bytes;\r
 991         dws->dma_width = chip->dma_width;\r
 992         dws->cs_control = chip->cs_control;\r
 993 \r
 994         //dws->rx_dma = transfer->rx_dma;\r
 995         //dws->tx_dma = transfer->tx_dma;\r
 996         dws->tx = (void *)transfer->tx_buf;\r
 997         dws->tx_end = dws->tx + transfer->len;\r
 998         dws->rx = (void *)transfer->rx_buf;\r
 999         dws->rx_end = dws->rx + transfer->len;\r
1000         dws->write = dws->tx ? chip->write : null_writer;\r
1001         dws->read = dws->rx ? chip->read : null_reader;\r
1002         dws->cs_change = transfer->cs_change;\r
1003         dws->len = dws->cur_transfer->len;\r
1004         if (chip != dws->prev_chip)\r
1005                 cs_change = 1;\r
1006 \r
1007         cr0 = chip->cr0;\r
1008         \r
1009         /* Handle per transfer options for bpw and speed */\r
1010         if (transfer->speed_hz) {\r
1011                 speed = chip->speed_hz;\r
1012                 if (transfer->speed_hz != speed) {\r
1013                         speed = transfer->speed_hz;\r
1014                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1015                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1016                                         "freq: %dHz\n", speed);\r
1017                                 message->status = -EIO;\r
1018                                 goto err_out;\r
1019                         }\r
1020 \r
1021                         /* clk_div doesn't support odd number */\r
1022                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1023                         clk_div = (clk_div + 1) & 0xfffe;\r
1024 \r
1025                         chip->speed_hz = speed;\r
1026                         chip->clk_div = clk_div;\r
1027                 }\r
1028         }\r
1029 \r
1030         \r
1031         if (transfer->bits_per_word) {\r
1032                 bits = transfer->bits_per_word;\r
1033 \r
1034                 switch (bits) {\r
1035                 case 8:\r
1036                         dws->n_bytes = 1;\r
1037                         dws->dma_width = 1;\r
1038                         spi_dfs = SPI_DFS_8BIT;\r
1039                         break;\r
1040                 case 16:\r
1041                         dws->n_bytes = 2;\r
1042                         dws->dma_width = 2;\r
1043                         spi_dfs = SPI_DFS_16BIT;\r
1044                         break;\r
1045                 default:\r
1046                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1047                                 "%db\n", bits);\r
1048                         message->status = -EIO;\r
1049                         goto err_out;\r
1050                 }\r
1051 \r
1052                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1053                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1054                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1055                         | (chip->type << SPI_FRF_OFFSET)\r
1056                         | (spi->mode << SPI_MODE_OFFSET)\r
1057                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1058         }\r
1059         message->state = RUNNING_STATE;\r
1060  \r
1061         /*\r
1062          * Adjust transfer mode if necessary. Requires platform dependent\r
1063          * chipselect mechanism.\r
1064          */\r
1065         if (dws->cs_control) {\r
1066                 if (dws->rx && dws->tx)\r
1067                         chip->tmode = SPI_TMOD_TR;\r
1068                 else if (dws->rx)\r
1069                         chip->tmode = SPI_TMOD_RO;\r
1070                 else\r
1071                         chip->tmode = SPI_TMOD_TO;\r
1072 \r
1073                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1074                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1075         }\r
1076 \r
1077         /*\r
1078          * Reprogram registers only if\r
1079          *      1. chip select changes\r
1080          *      2. clk_div is changed\r
1081          *      3. control value changes\r
1082          */\r
1083         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div) {\r
1084                 spi_enable_chip(dws, 0);\r
1085                 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0) {\r
1086                         rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
1087                 }\r
1088 \r
1089                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1090                 spi_chip_sel(dws, spi->chip_select);\r
1091                 /* Set the interrupt mask, for poll mode just diable all int */\r
1092                 spi_mask_intr(dws, 0xff);\r
1093                 \r
1094                 if (transfer->tx_buf != NULL) {\r
1095                         dmacr |= SPI_DMACR_TX_ENABLE;\r
1096                         rk29xx_writew(dws, SPIM_DMATDLR, 0);\r
1097                 }\r
1098                 if (transfer->rx_buf != NULL) {\r
1099                         dmacr |= SPI_DMACR_RX_ENABLE;\r
1100                         rk29xx_writew(dws, SPIM_DMARDLR, 0);\r
1101                         rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);\r
1102                 }\r
1103                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1104                 spi_enable_chip(dws, 1);\r
1105                 if (cs_change)\r
1106                         dws->prev_chip = chip;\r
1107         } \r
1108 \r
1109         //INIT_COMPLETION(dws->xfer_completion);\r
1110 \r
1111         spi_dump_regs(dws);\r
1112         DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, transfer->tx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)transfer->tx_dma);\r
1113         if (transfer->tx_buf != NULL) {\r
1114                 dws->state |= TXBUSY;\r
1115                 /*if (transfer->len & 0x3) {\r
1116                         burst = 1;\r
1117                 }\r
1118                 else {\r
1119                         burst = 4;\r
1120                 }\r
1121                 if (rk29_dma_config(dws->tx_dmach, burst)) {*/\r
1122                 if (rk29_dma_config(dws->tx_dmach, 1, 1)) {//there is not dma burst but bitwide, set it 1 alwayss\r
1123                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1124                         goto err_out;\r
1125                 }\r
1126                 \r
1127                 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH); \r
1128                 \r
1129                 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,\r
1130                                         transfer->tx_dma, transfer->len);\r
1131                 if (iRet) {\r
1132                         dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet, \r
1133                                 dws->tx_dmach, (unsigned int)transfer->tx_dma);\r
1134                         goto err_out;\r
1135                 }\r
1136                 \r
1137                 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {\r
1138                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1139                         goto err_out;\r
1140                 }\r
1141         }\r
1142 \r
1143         //wait_till_not_busy(dws);\r
1144         \r
1145         if (transfer->rx_buf != NULL) {\r
1146                 dws->state |= RXBUSY;\r
1147                 if (rk29_dma_config(dws->rx_dmach, 1, 1)) {\r
1148                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1149                         goto err_out;\r
1150                 }\r
1151 \r
1152                 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH); \r
1153                 \r
1154                 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,\r
1155                                         transfer->rx_dma, transfer->len);\r
1156                 if (iRet) {\r
1157                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1158                         goto err_out;\r
1159                 }\r
1160                 \r
1161                 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {\r
1162                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1163                         goto err_out;\r
1164                 }\r
1165         }\r
1166         \r
1167         return;\r
1168 \r
1169 err_out:\r
1170         giveback(dws);\r
1171         return;\r
1172 \r
1173 }\r
1174 \r
1175 static void pump_messages(struct work_struct *work)\r
1176 {\r
1177         struct rk29xx_spi *dws =\r
1178                 container_of(work, struct rk29xx_spi, pump_messages);\r
1179         unsigned long flags;\r
1180 \r
1181         DBG(KERN_INFO "pump_messages\n");\r
1182         \r
1183         /* Lock queue and check for queue work */\r
1184         spin_lock_irqsave(&dws->lock, flags);\r
1185         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1186                 dws->busy = 0;\r
1187                 spin_unlock_irqrestore(&dws->lock, flags);\r
1188                 mutex_unlock(&dws->dma_lock);\r
1189                 return;\r
1190         }\r
1191 \r
1192         /* Make sure we are not already running a message */\r
1193         if (dws->cur_msg) {\r
1194                 spin_unlock_irqrestore(&dws->lock, flags);\r
1195                 mutex_unlock(&dws->dma_lock);\r
1196                 return;\r
1197         }\r
1198 \r
1199         /* Extract head of queue */\r
1200         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1201         list_del_init(&dws->cur_msg->queue);\r
1202 \r
1203         /* Initial message state*/\r
1204         dws->cur_msg->state = START_STATE;\r
1205         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1206                                                 struct spi_transfer,\r
1207                                                 transfer_list);\r
1208         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1209         dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1210 \r
1211         /* Mark as busy and launch transfers */\r
1212         tasklet_schedule(&dws->pump_transfers);\r
1213         dws->busy = 1;\r
1214         spin_unlock_irqrestore(&dws->lock, flags);\r
1215         \r
1216 }\r
1217 \r
1218 #if defined(QUICK_TRANSFER)\r
1219 static void do_read(struct rk29xx_spi *dws)\r
1220 {\r
1221         int count = 0;\r
1222 \r
1223         spi_enable_chip(dws, 0);\r
1224         rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);\r
1225         spi_enable_chip(dws, 1);                \r
1226         rk29xx_writew(dws, SPIM_TXDR, 0);\r
1227         while (1) {\r
1228                 if (dws->read(dws))\r
1229                         break;\r
1230                 if (count++ == 0x20) {\r
1231                         dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");\r
1232                         break;\r
1233                 }\r
1234                 \r
1235         }\r
1236 }\r
1237 \r
1238 static void do_write(struct rk29xx_spi *dws)\r
1239 {\r
1240         while (dws->tx<dws->tx_end) {\r
1241                 dws->write(dws);\r
1242         }\r
1243 }\r
1244 \r
1245 /* Caller already set message->status; dma and pio irqs are blocked */\r
1246 static void msg_giveback(struct rk29xx_spi *dws)\r
1247 {\r
1248         struct spi_transfer *last_transfer;\r
1249         struct spi_message *msg;\r
1250 \r
1251         DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1252 \r
1253         msg = dws->cur_msg;\r
1254         dws->cur_msg = NULL;\r
1255         dws->cur_transfer = NULL;\r
1256         dws->prev_chip = dws->cur_chip;\r
1257         dws->cur_chip = NULL;\r
1258         dws->dma_mapped = 0;\r
1259         dws->busy = 0;\r
1260 \r
1261         last_transfer = list_entry(msg->transfers.prev,\r
1262                                         struct spi_transfer,\r
1263                                         transfer_list);\r
1264 \r
1265         if (!last_transfer->cs_change && dws->cs_control)\r
1266                 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
1267 \r
1268         msg->state = NULL;      \r
1269 }\r
1270 \r
1271 /* Must be called inside pump_transfers() */\r
1272 static int do_full_transfer(struct rk29xx_spi *dws)\r
1273 {\r
1274         if ((dws->read(dws))) {\r
1275                 goto comple;\r
1276         }\r
1277         \r
1278         while (dws->tx<dws->tx_end){\r
1279                 dws->write(dws);                \r
1280                 dws->read(dws);\r
1281         }\r
1282         \r
1283         if (dws->rx < dws->rx_end) {\r
1284                 dws->read(dws);\r
1285         }\r
1286 \r
1287 comple:\r
1288         \r
1289         dws->cur_msg->actual_length += dws->len;\r
1290         \r
1291         /* Move to next transfer */\r
1292         dws->cur_msg->state = next_transfer(dws);\r
1293                                         \r
1294         if (dws->cur_msg->state == DONE_STATE) {\r
1295                 dws->cur_msg->status = 0;\r
1296                 //msg_giveback(dws);\r
1297                 return 0;\r
1298         }\r
1299         else {\r
1300                 return -1;\r
1301         }\r
1302         \r
1303 }\r
1304 \r
1305 \r
1306 /* Must be called inside pump_transfers() */\r
1307 static int do_half_transfer(struct rk29xx_spi *dws)\r
1308 {\r
1309         if (dws->rx) {\r
1310                 if (dws->tx) {\r
1311                         do_write(dws);\r
1312                 }\r
1313                 wait_till_tf_empty(dws);\r
1314                 wait_till_not_busy(dws);\r
1315                 do_read(dws);\r
1316         }\r
1317         else {\r
1318                 do_write(dws);\r
1319                 wait_till_tf_empty(dws);\r
1320                 wait_till_not_busy(dws);\r
1321         }\r
1322         \r
1323         dws->cur_msg->actual_length += dws->len;\r
1324         \r
1325         /* Move to next transfer */\r
1326         dws->cur_msg->state = next_transfer(dws);\r
1327                                         \r
1328         if (dws->cur_msg->state == DONE_STATE) {\r
1329                 dws->cur_msg->status = 0;\r
1330                 //msg_giveback(dws);\r
1331                 return 0;\r
1332         }\r
1333         else {\r
1334                 return -1;\r
1335         }\r
1336 }\r
1337 \r
1338 \r
1339 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)\r
1340 {\r
1341         struct spi_message *message = NULL;\r
1342         struct spi_transfer *transfer = NULL;\r
1343         struct spi_transfer *previous = NULL;\r
1344         struct spi_device *spi = NULL;\r
1345         struct chip_data *chip = NULL;\r
1346         u8 bits = 0;\r
1347         u8 spi_dfs = 0;\r
1348         u8 cs_change = 0;\r
1349         u16 clk_div = 0;\r
1350         u32 speed = 0;\r
1351         u32 cr0 = 0;\r
1352         u32 dmacr = 0;\r
1353         \r
1354         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1355 \r
1356         /* Get current state information */\r
1357         message = dws->cur_msg;\r
1358         transfer = dws->cur_transfer;\r
1359         chip = dws->cur_chip;\r
1360         spi = message->spi;     \r
1361 \r
1362         if (unlikely(!chip->clk_div))\r
1363                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;\r
1364         if (message->state == ERROR_STATE) {\r
1365                 message->status = -EIO;\r
1366                 goto early_exit;\r
1367         }\r
1368 \r
1369         /* Handle end of message */\r
1370         if (message->state == DONE_STATE) {\r
1371                 message->status = 0;\r
1372                 goto early_exit;\r
1373         }\r
1374 \r
1375         /* Delay if requested at end of transfer*/\r
1376         if (message->state == RUNNING_STATE) {\r
1377                 previous = list_entry(transfer->transfer_list.prev,\r
1378                                         struct spi_transfer,\r
1379                                         transfer_list);\r
1380                 if (previous->delay_usecs)\r
1381                         udelay(previous->delay_usecs);\r
1382         }\r
1383 \r
1384         dws->n_bytes = chip->n_bytes;\r
1385         dws->dma_width = chip->dma_width;\r
1386         dws->cs_control = chip->cs_control;\r
1387 \r
1388         dws->rx_dma = transfer->rx_dma;\r
1389         dws->tx_dma = transfer->tx_dma;\r
1390         dws->tx = (void *)transfer->tx_buf;\r
1391         dws->tx_end = dws->tx + transfer->len;\r
1392         dws->rx = transfer->rx_buf;\r
1393         dws->rx_end = dws->rx + transfer->len;\r
1394         dws->write = dws->tx ? chip->write : null_writer;\r
1395         dws->read = dws->rx ? chip->read : null_reader;\r
1396         if (dws->rx && dws->tx) {\r
1397                 int temp_len = transfer->len;\r
1398                 int len;\r
1399                 unsigned char *tx_buf;\r
1400                 for (len=0; *tx_buf++ != 0; len++);\r
1401                 dws->tx_end = dws->tx + len;\r
1402                 dws->rx_end = dws->rx + temp_len - len;\r
1403         }\r
1404         dws->cs_change = transfer->cs_change;\r
1405         dws->len = dws->cur_transfer->len;\r
1406         if (chip != dws->prev_chip)\r
1407                 cs_change = 1;\r
1408 \r
1409         cr0 = chip->cr0;\r
1410 \r
1411         /* Handle per transfer options for bpw and speed */\r
1412         if (transfer->speed_hz) {\r
1413                 speed = chip->speed_hz;\r
1414 \r
1415                 if (transfer->speed_hz != speed) {\r
1416                         speed = transfer->speed_hz;\r
1417                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1418                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1419                                         "freq: %dHz\n", speed);\r
1420                                 message->status = -EIO;\r
1421                                 goto early_exit;\r
1422                         }\r
1423 \r
1424                         /* clk_div doesn't support odd number */\r
1425                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1426                         clk_div = (clk_div + 1) & 0xfffe;\r
1427 \r
1428                         chip->speed_hz = speed;\r
1429                         chip->clk_div = clk_div;\r
1430                 }\r
1431         }\r
1432         if (transfer->bits_per_word) {\r
1433                 bits = transfer->bits_per_word;\r
1434 \r
1435                 switch (bits) {\r
1436                 case 8:\r
1437                         dws->n_bytes = 1;\r
1438                         dws->dma_width = 1;\r
1439                         dws->read = (dws->read != null_reader) ?\r
1440                                         u8_reader : null_reader;\r
1441                         dws->write = (dws->write != null_writer) ?\r
1442                                         u8_writer : null_writer;\r
1443                         spi_dfs = SPI_DFS_8BIT;\r
1444                         break;\r
1445                 case 16:\r
1446                         dws->n_bytes = 2;\r
1447                         dws->dma_width = 2;\r
1448                         dws->read = (dws->read != null_reader) ?\r
1449                                         u16_reader : null_reader;\r
1450                         dws->write = (dws->write != null_writer) ?\r
1451                                         u16_writer : null_writer;\r
1452                         spi_dfs = SPI_DFS_16BIT;\r
1453                         break;\r
1454                 default:\r
1455                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1456                                 "%db\n", bits);\r
1457                         message->status = -EIO;\r
1458                         goto early_exit;\r
1459                 }\r
1460 \r
1461                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1462                         | (chip->type << SPI_FRF_OFFSET)\r
1463                         | (spi->mode << SPI_MODE_OFFSET)\r
1464                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1465         }\r
1466         message->state = RUNNING_STATE;\r
1467  \r
1468         /*\r
1469          * Adjust transfer mode if necessary. Requires platform dependent\r
1470          * chipselect mechanism.\r
1471          */\r
1472         if (dws->cs_control) {\r
1473                 if (dws->rx && dws->tx)\r
1474                         chip->tmode = SPI_TMOD_TR;\r
1475                 else if (dws->rx)\r
1476                         chip->tmode = SPI_TMOD_RO;\r
1477                 else\r
1478                         chip->tmode = SPI_TMOD_TO;\r
1479 \r
1480                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1481                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1482         }\r
1483         \r
1484         /* Check if current transfer is a DMA transaction */\r
1485         dws->dma_mapped = map_dma_buffers(dws);\r
1486 \r
1487         /*\r
1488          * Reprogram registers only if\r
1489          *      1. chip select changes\r
1490          *      2. clk_div is changed\r
1491          *      3. control value changes\r
1492          */\r
1493         spi_enable_chip(dws, 0);\r
1494         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)\r
1495                 rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
1496 \r
1497     DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);\r
1498         spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1499         spi_chip_sel(dws, spi->chip_select);            \r
1500         rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx\r
1501         if(dws->dma_mapped ) {\r
1502                 dmacr = rk29xx_readw(dws, SPIM_DMACR);\r
1503                 dmacr = dmacr | SPI_DMACR_TX_ENABLE;\r
1504                 if (mode) \r
1505                         dmacr = dmacr | SPI_DMACR_RX_ENABLE;\r
1506                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1507         }\r
1508         spi_enable_chip(dws, 1);\r
1509         if (cs_change)\r
1510                 dws->prev_chip = chip;\r
1511         \r
1512         if (mode)\r
1513                 return do_full_transfer(dws);\r
1514         else\r
1515                 return do_half_transfer(dws);   \r
1516         \r
1517 early_exit:\r
1518         \r
1519         //msg_giveback(dws);\r
1520         \r
1521         return 0;\r
1522 }\r
1523 \r
1524 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)\r
1525 {\r
1526         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1527         \r
1528         while (!acquire_dma(dws))\r
1529                         msleep(10);\r
1530 \r
1531         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1532                 dws->busy = 0;\r
1533                 return;\r
1534         }\r
1535 \r
1536         /* Make sure we are not already running a message */\r
1537         if (dws->cur_msg) {\r
1538                 return;\r
1539         }\r
1540 \r
1541         /* Extract head of queue */\r
1542         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1543         list_del_init(&dws->cur_msg->queue);\r
1544 \r
1545         /* Initial message state*/\r
1546         dws->cur_msg->state = START_STATE;\r
1547         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1548                                                 struct spi_transfer,\r
1549                                                 transfer_list);\r
1550         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1551     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1552     \r
1553         /* Mark as busy and launch transfers */\r
1554         dws->busy = 1;\r
1555 \r
1556         while (rk29xx_pump_transfers(dws, mode)) ;\r
1557 }\r
1558 \r
1559 /* spi_device use this to queue in their spi_msg */\r
1560 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)\r
1561 {\r
1562         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1563         unsigned long flags;\r
1564         struct rk29xx_spi_chip *chip_info = spi->controller_data;\r
1565         struct spi_message *mmsg;\r
1566         \r
1567         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1568         \r
1569         spin_lock_irqsave(&dws->lock, flags);\r
1570 \r
1571         if (dws->run == QUEUE_STOPPED) {\r
1572                 spin_unlock_irqrestore(&dws->lock, flags);\r
1573                 return -ESHUTDOWN;\r
1574         }\r
1575 \r
1576         msg->actual_length = 0;\r
1577         msg->status = -EINPROGRESS;\r
1578         msg->state = START_STATE;\r
1579 \r
1580         list_add_tail(&msg->queue, &dws->queue);\r
1581 \r
1582         if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {\r
1583                 rk29xx_pump_messages(dws,1);\r
1584         }\r
1585         else {          \r
1586                 rk29xx_pump_messages(dws,0);\r
1587         }\r
1588 \r
1589         mmsg = dws->cur_msg;\r
1590         msg_giveback(dws);\r
1591         \r
1592         spin_unlock_irqrestore(&dws->lock, flags);\r
1593 \r
1594         if (mmsg->complete)\r
1595                 mmsg->complete(mmsg->context);\r
1596         \r
1597         return 0;\r
1598 }\r
1599 \r
1600 #else\r
1601 \r
1602 /* spi_device use this to queue in their spi_msg */\r
1603 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)\r
1604 {\r
1605         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1606         unsigned long flags;\r
1607 \r
1608         spin_lock_irqsave(&dws->lock, flags);\r
1609 \r
1610         if (dws->run == QUEUE_STOPPED) {\r
1611                 spin_unlock_irqrestore(&dws->lock, flags);\r
1612                 return -ESHUTDOWN;\r
1613         }\r
1614 \r
1615         msg->actual_length = 0;\r
1616         msg->status = -EINPROGRESS;\r
1617         msg->state = START_STATE;\r
1618 \r
1619         list_add_tail(&msg->queue, &dws->queue);\r
1620 \r
1621         if (dws->run == QUEUE_RUNNING && !dws->busy) {\r
1622 \r
1623                 if (dws->cur_transfer || dws->cur_msg)\r
1624                         queue_work(dws->workqueue,\r
1625                                         &dws->pump_messages);\r
1626                 else {\r
1627                         /* If no other data transaction in air, just go */\r
1628                         spin_unlock_irqrestore(&dws->lock, flags);\r
1629                         pump_messages(&dws->pump_messages);                     \r
1630                         return 0;\r
1631                 }\r
1632         }\r
1633 \r
1634         spin_unlock_irqrestore(&dws->lock, flags);\r
1635         \r
1636         return 0;\r
1637 }\r
1638 \r
1639 #endif\r
1640 \r
1641 /* This may be called twice for each spi dev */\r
1642 static int rk29xx_spi_setup(struct spi_device *spi)\r
1643 {\r
1644         struct rk29xx_spi_chip *chip_info = NULL;\r
1645         struct chip_data *chip;\r
1646         u8 spi_dfs = 0;\r
1647 \r
1648         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)\r
1649                 return -EINVAL;\r
1650 \r
1651         /* Only alloc on first setup */\r
1652         chip = spi_get_ctldata(spi);\r
1653         if (!chip) {\r
1654                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\r
1655                 if (!chip)\r
1656                         return -ENOMEM;\r
1657 \r
1658                 chip->cs_control = spi_cs_control;\r
1659                 chip->enable_dma = 0;  //0;\r
1660         }\r
1661 \r
1662         /*\r
1663          * Protocol drivers may change the chip settings, so...\r
1664          * if chip_info exists, use it\r
1665          */\r
1666         chip_info = spi->controller_data;\r
1667 \r
1668         /* chip_info doesn't always exist */\r
1669         if (chip_info) {\r
1670                 if (chip_info->cs_control)\r
1671                         chip->cs_control = chip_info->cs_control;\r
1672 \r
1673                 chip->poll_mode = chip_info->poll_mode;\r
1674                 chip->type = chip_info->type;\r
1675 \r
1676                 chip->rx_threshold = 0;\r
1677                 chip->tx_threshold = 0;\r
1678 \r
1679                 chip->enable_dma = chip_info->enable_dma;\r
1680         }\r
1681 \r
1682         if (spi->bits_per_word == 8) {\r
1683                 chip->n_bytes = 1;\r
1684                 chip->dma_width = 1;\r
1685                 chip->read = u8_reader;\r
1686                 chip->write = u8_writer;\r
1687                 spi_dfs = SPI_DFS_8BIT;\r
1688         } else if (spi->bits_per_word == 16) {\r
1689                 chip->n_bytes = 2;\r
1690                 chip->dma_width = 2;\r
1691                 chip->read = u16_reader;\r
1692                 chip->write = u16_writer;\r
1693                 spi_dfs = SPI_DFS_16BIT;\r
1694         } else {\r
1695                 /* Never take >16b case for MRST SPIC */\r
1696                 dev_err(&spi->dev, "invalid wordsize\n");\r
1697                 return -EINVAL;\r
1698         }\r
1699         chip->bits_per_word = spi->bits_per_word;\r
1700 \r
1701         if (!spi->max_speed_hz) {\r
1702                 dev_err(&spi->dev, "No max speed HZ parameter\n");\r
1703                 return -EINVAL;\r
1704         }\r
1705         chip->speed_hz = spi->max_speed_hz;\r
1706 \r
1707         chip->tmode = 0; /* Tx & Rx */\r
1708         /* Default SPI mode is SCPOL = 0, SCPH = 0 */\r
1709         chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1710                 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1711                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1712                         | (chip->type << SPI_FRF_OFFSET)\r
1713                         | (spi->mode  << SPI_MODE_OFFSET)\r
1714                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1715 \r
1716         spi_set_ctldata(spi, chip);\r
1717         return 0;\r
1718 }\r
1719 \r
1720 static void rk29xx_spi_cleanup(struct spi_device *spi)\r
1721 {\r
1722         struct chip_data *chip = spi_get_ctldata(spi);\r
1723         kfree(chip);\r
1724 }\r
1725 \r
1726 static int __devinit init_queue(struct rk29xx_spi *dws)\r
1727 {\r
1728         INIT_LIST_HEAD(&dws->queue);\r
1729         spin_lock_init(&dws->lock);\r
1730 \r
1731         dws->run = QUEUE_STOPPED;\r
1732         dws->busy = 0;\r
1733 \r
1734         init_completion(&dws->xfer_completion);\r
1735 \r
1736         tasklet_init(&dws->pump_transfers,\r
1737                         pump_transfers, (unsigned long)dws);\r
1738 \r
1739         INIT_WORK(&dws->pump_messages, pump_messages);\r
1740         dws->workqueue = create_singlethread_workqueue(\r
1741                                         dev_name(dws->master->dev.parent));\r
1742         if (dws->workqueue == NULL)\r
1743                 return -EBUSY;\r
1744 \r
1745 \r
1746         return 0;\r
1747 }\r
1748 \r
1749 static int start_queue(struct rk29xx_spi *dws)\r
1750 {\r
1751         unsigned long flags;\r
1752 \r
1753         spin_lock_irqsave(&dws->lock, flags);\r
1754 \r
1755         if (dws->run == QUEUE_RUNNING || dws->busy) {\r
1756                 spin_unlock_irqrestore(&dws->lock, flags);\r
1757                 return -EBUSY;\r
1758         }\r
1759 \r
1760         dws->run = QUEUE_RUNNING;\r
1761         dws->cur_msg = NULL;\r
1762         dws->cur_transfer = NULL;\r
1763         dws->cur_chip = NULL;\r
1764         dws->prev_chip = NULL;\r
1765         spin_unlock_irqrestore(&dws->lock, flags);\r
1766 \r
1767         queue_work(dws->workqueue, &dws->pump_messages);\r
1768 \r
1769         return 0;\r
1770 }\r
1771 \r
1772 static int stop_queue(struct rk29xx_spi *dws)\r
1773 {\r
1774         unsigned long flags;\r
1775         unsigned limit = 50;\r
1776         int status = 0;\r
1777 \r
1778         spin_lock_irqsave(&dws->lock, flags);\r
1779         dws->run = QUEUE_STOPPED;\r
1780         while (!list_empty(&dws->queue) && dws->busy && limit--) {\r
1781                 spin_unlock_irqrestore(&dws->lock, flags);\r
1782                 msleep(10);\r
1783                 spin_lock_irqsave(&dws->lock, flags);\r
1784         }\r
1785 \r
1786         if (!list_empty(&dws->queue) || dws->busy)\r
1787                 status = -EBUSY;\r
1788         spin_unlock_irqrestore(&dws->lock, flags);\r
1789 \r
1790         return status;\r
1791 }\r
1792 \r
1793 static int destroy_queue(struct rk29xx_spi *dws)\r
1794 {\r
1795         int status;\r
1796 \r
1797         status = stop_queue(dws);\r
1798         if (status != 0)\r
1799                 return status;\r
1800         destroy_workqueue(dws->workqueue);\r
1801         return 0;\r
1802 }\r
1803 \r
1804 /* Restart the controller, disable all interrupts, clean rx fifo */\r
1805 static void spi_hw_init(struct rk29xx_spi *dws)\r
1806 {\r
1807         spi_enable_chip(dws, 0);\r
1808         spi_mask_intr(dws, 0xff);\r
1809         \r
1810         /*\r
1811          * Try to detect the FIFO depth if not set by interface driver,\r
1812          * the depth could be from 2 to 32 from HW spec\r
1813          */\r
1814         if (!dws->fifo_len) {\r
1815                 u32 fifo;\r
1816                 for (fifo = 2; fifo <= 31; fifo++) {\r
1817                         rk29xx_writew(dws, SPIM_TXFTLR, fifo);\r
1818                         if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))\r
1819                                 break;\r
1820                 }\r
1821 \r
1822                 dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
1823                 rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
1824         }\r
1825         \r
1826         spi_enable_chip(dws, 1);\r
1827         //flush(dws);\r
1828 }\r
1829 \r
1830 /* cpufreq driver support */\r
1831 #ifdef CONFIG_CPU_FREQ\r
1832 \r
1833 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)\r
1834 {\r
1835         struct rk29xx_spi *info;\r
1836         unsigned long newclk;\r
1837 \r
1838         info = container_of(nb, struct rk29xx_spi, freq_transition);\r
1839         newclk = clk_get_rate(info->clock_spim);\r
1840 \r
1841         return 0;\r
1842 }\r
1843 \r
1844 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1845 {\r
1846         info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;\r
1847 \r
1848         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1849 }\r
1850 \r
1851 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1852 {\r
1853         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1854 }\r
1855 \r
1856 #else\r
1857 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1858 {\r
1859         return 0;\r
1860 }\r
1861 \r
1862 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1863 {\r
1864 }\r
1865 #endif\r
1866 static int __init rk29xx_spim_probe(struct platform_device *pdev)\r
1867 {\r
1868         struct resource         *regs, *dmatx_res, *dmarx_res;\r
1869         struct rk29xx_spi   *dws;\r
1870         struct spi_master   *master;\r
1871         int                     irq; \r
1872         int ret;\r
1873         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
1874 \r
1875         if (pdata && pdata->io_init) {\r
1876                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
1877                 if (ret) {                      \r
1878                         return -ENXIO;  \r
1879                 }\r
1880         }\r
1881         \r
1882         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1883         if (!regs)\r
1884                 return -ENXIO;\r
1885         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);\r
1886         if (dmatx_res == NULL) {\r
1887                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");\r
1888                 return -ENXIO;\r
1889         }\r
1890 \r
1891         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);\r
1892         if (dmarx_res == NULL) {\r
1893                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");\r
1894                 return -ENXIO;\r
1895         }\r
1896         irq = platform_get_irq(pdev, 0);\r
1897         if (irq < 0)\r
1898                 return irq;                     \r
1899         /* setup spi core then atmel-specific driver state */\r
1900         ret = -ENOMEM;  \r
1901         master = spi_alloc_master(&pdev->dev, sizeof *dws);\r
1902         if (!master) {\r
1903                 ret = -ENOMEM;\r
1904                 goto exit;\r
1905         }\r
1906 \r
1907         platform_set_drvdata(pdev, master);\r
1908         dws = spi_master_get_devdata(master);\r
1909         dws->clock_spim = clk_get(&pdev->dev, "spi");\r
1910         clk_enable(dws->clock_spim);\r
1911         if (IS_ERR(dws->clock_spim)) {\r
1912                 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
1913                 return PTR_ERR(dws->clock_spim);\r
1914         }\r
1915         \r
1916         mutex_init(&dws->dma_lock);\r
1917         \r
1918         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);\r
1919         if (!dws->regs){\r
1920         release_mem_region(regs->start, (regs->end - regs->start) + 1);\r
1921                 return -EBUSY;\r
1922         }\r
1923         DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
1924         dws->irq = irq;\r
1925         dws->irq_polarity = IRQF_TRIGGER_NONE;\r
1926         dws->master = master;\r
1927         dws->type = SSI_MOTO_SPI;\r
1928         dws->prev_chip = NULL;\r
1929         dws->sfr_start = regs->start;\r
1930         dws->tx_dmach = dmatx_res->start;\r
1931         dws->rx_dmach = dmarx_res->start;\r
1932         dws->dma_inited = 0;  ///0;\r
1933         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);\r
1934         ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,\r
1935                         "rk29xx_spim", dws);\r
1936         if (ret < 0) {\r
1937                 dev_err(&master->dev, "can not get IRQ\n");\r
1938                 goto err_free_master;\r
1939         }\r
1940 \r
1941         master->mode_bits = SPI_CPOL | SPI_CPHA;\r
1942         master->bus_num = pdev->id;\r
1943         master->num_chipselect = pdata->num_chipselect;\r
1944         master->dev.platform_data = pdata;\r
1945         master->cleanup = rk29xx_spi_cleanup;\r
1946         master->setup = rk29xx_spi_setup;\r
1947         #if defined(QUICK_TRANSFER)\r
1948         master->transfer = rk29xx_spi_quick_transfer;\r
1949         #else\r
1950         master->transfer = rk29xx_spi_transfer;\r
1951         #endif\r
1952         \r
1953         dws->pdev = pdev;\r
1954         /* Basic HW init */\r
1955         spi_hw_init(dws);\r
1956         flush(dws);\r
1957         /* Initial and start queue */\r
1958         ret = init_queue(dws);\r
1959         if (ret) {\r
1960                 dev_err(&master->dev, "problem initializing queue\n");\r
1961                 goto err_diable_hw;\r
1962         }\r
1963 \r
1964         ret = start_queue(dws);\r
1965         if (ret) {\r
1966                 dev_err(&master->dev, "problem starting queue\n");\r
1967                 goto err_diable_hw;\r
1968         }\r
1969 \r
1970         spi_master_set_devdata(master, dws);\r
1971         ret = spi_register_master(master);\r
1972         if (ret) {\r
1973                 dev_err(&master->dev, "problem registering spi master\n");\r
1974                 goto err_queue_alloc;\r
1975         }\r
1976 \r
1977     ret =rk29xx_spim_cpufreq_register(dws);\r
1978     if (ret < 0) {\r
1979         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
1980         goto err_queue_alloc;\r
1981     }\r
1982         printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);\r
1983         mrst_spi_debugfs_init(dws);\r
1984         return 0;\r
1985 \r
1986 err_queue_alloc:\r
1987         destroy_queue(dws);\r
1988 err_diable_hw:\r
1989         spi_enable_chip(dws, 0);\r
1990         free_irq(dws->irq, dws);\r
1991 err_free_master:\r
1992         spi_master_put(master);\r
1993         iounmap(dws->regs);\r
1994 exit:\r
1995         return ret;\r
1996 }\r
1997 \r
1998 static void __exit rk29xx_spim_remove(struct platform_device *pdev)\r
1999 {\r
2000         struct spi_master *master = platform_get_drvdata(pdev);\r
2001         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2002         int status = 0;\r
2003 \r
2004         if (!dws)\r
2005                 return;\r
2006         rk29xx_spim_cpufreq_deregister(dws);\r
2007         mrst_spi_debugfs_remove(dws);\r
2008 \r
2009         if(dws->buffer_tx_dma)\r
2010         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);\r
2011         if(dws->buffer_rx_dma)\r
2012         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);\r
2013         release_dma(dws);\r
2014 \r
2015         /* Remove the queue */\r
2016         status = destroy_queue(dws);\r
2017         if (status != 0)\r
2018                 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "\r
2019                         "complete, message memory not freed\n");\r
2020         clk_put(dws->clock_spim);\r
2021         clk_disable(dws->clock_spim);\r
2022         spi_enable_chip(dws, 0);\r
2023         /* Disable clk */\r
2024         spi_set_clk(dws, 0);\r
2025         free_irq(dws->irq, dws);\r
2026 \r
2027         /* Disconnect from the SPI framework */\r
2028         spi_unregister_master(dws->master);\r
2029         iounmap(dws->regs);\r
2030 }\r
2031 \r
2032 \r
2033 #ifdef  CONFIG_PM\r
2034 \r
2035 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)\r
2036 {\r
2037         struct spi_master *master = platform_get_drvdata(pdev);\r
2038         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2039         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2040         int status;\r
2041         \r
2042         flush(dws);\r
2043         status = stop_queue(dws);\r
2044         if (status != 0)\r
2045                 return status;\r
2046         clk_disable(dws->clock_spim);\r
2047         if (pdata && pdata->io_fix_leakage_bug)\r
2048         {\r
2049                 pdata->io_fix_leakage_bug( );\r
2050         }\r
2051         return 0;\r
2052 }\r
2053 \r
2054 static int rk29xx_spim_resume(struct platform_device *pdev)\r
2055 {\r
2056         struct spi_master *master = platform_get_drvdata(pdev);\r
2057         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2058         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2059         int ret;\r
2060         \r
2061         clk_enable(dws->clock_spim);    \r
2062         spi_hw_init(dws);\r
2063         ret = start_queue(dws);\r
2064         if (ret)\r
2065                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);\r
2066         if (pdata && pdata->io_resume_leakage_bug)\r
2067         {\r
2068                 pdata->io_resume_leakage_bug( ); \r
2069         }\r
2070         return ret;\r
2071 }\r
2072 \r
2073 #else\r
2074 #define rk29xx_spim_suspend     NULL\r
2075 #define rk29xx_spim_resume      NULL\r
2076 #endif\r
2077 \r
2078 static struct platform_driver rk29xx_platform_spim_driver = {\r
2079         .remove         = __exit_p(rk29xx_spim_remove),\r
2080         .driver         = {\r
2081                 .name   = "rk29xx_spim",\r
2082                 .owner  = THIS_MODULE,\r
2083         },\r
2084         .suspend        = rk29xx_spim_suspend,\r
2085         .resume         = rk29xx_spim_resume,\r
2086 };\r
2087 \r
2088 static int __init rk29xx_spim_init(void)\r
2089 {\r
2090         int ret;\r
2091         ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);   \r
2092         return ret;\r
2093 }\r
2094 \r
2095 static void __exit rk29xx_spim_exit(void)\r
2096 {\r
2097         platform_driver_unregister(&rk29xx_platform_spim_driver);\r
2098 }\r
2099 \r
2100 arch_initcall_sync(rk29xx_spim_init);\r
2101 module_exit(rk29xx_spim_exit);\r
2102 \r
2103 MODULE_AUTHOR("www.rock-chips.com");\r
2104 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");\r
2105 MODULE_LICENSE("GPL");;\r
2106 \r