drivers/spi/rk29_spim.c

   1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device \r
   2  *\r
   3  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   4  *\r
   5  * This software is licensed under the terms of the GNU General Public\r
   6  * License version 2, as published by the Free Software Foundation, and\r
   7  * may be copied, distributed, and modified under those terms.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful,\r
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  12  * GNU General Public License for more details.\r
  13  */\r
  14 \r
  15 #include <linux/dma-mapping.h>\r
  16 #include <linux/interrupt.h>\r
  17 #include <linux/highmem.h>\r
  18 #include <linux/delay.h>\r
  19 #include <linux/slab.h>\r
  20 #include <linux/platform_device.h>\r
  21 #include <linux/clk.h>\r
  22 #include <linux/cpufreq.h>\r
  23 #include <mach/gpio.h>\r
  24 #include <mach/irqs.h>\r
  25 #include <linux/dma-mapping.h>\r
  26 #include <asm/dma.h>\r
  27 #include <linux/preempt.h>\r
  28 #include "rk29_spim.h"\r
  29 #include <linux/spi/spi.h>\r
  30 #include <mach/board.h>\r
  31 \r
  32 #ifdef CONFIG_DEBUG_FS\r
  33 #include <linux/debugfs.h>\r
  34 #endif\r
  35 \r
  36 /*ÔÓÐµÄspiÇý¶¯Ð§ÂÊ±È½ÏµÍ£¬\r
  37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Êä£»\r
  38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Êä£¬Í¬Ê±¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬\r
  39 Ä¬ÈÏÊ¹ÓÃ°ëË«¹¤\r
  40 */\r
  41 \r
  42 //#define QUICK_TRANSFER         \r
  43 #if 0\r
  44 #define DBG   printk\r
  45 //#define PRINT_TRANS_DATA\r
  46 #else\r
  47 #define DBG(x...)\r
  48 #endif\r
  49 \r
  50 #define DMA_BUFFER_SIZE PAGE_SIZE\r
  51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO\r
  52 \r
  53 \r
  54 #define START_STATE     ((void *)0)\r
  55 #define RUNNING_STATE   ((void *)1)\r
  56 #define DONE_STATE      ((void *)2)\r
  57 #define ERROR_STATE     ((void *)-1)\r
  58 \r
  59 #define QUEUE_RUNNING   0\r
  60 #define QUEUE_STOPPED   1\r
  61 \r
  62 #define MRST_SPI_DEASSERT       0\r
  63 #define MRST_SPI_ASSERT         1  ///CS0\r
  64 #define MRST_SPI_ASSERT1        2  ///CS1\r
  65 \r
  66 /* Slave spi_dev related */\r
  67 struct chip_data {\r
  68         u16 cr0;\r
  69         u8 cs;                  /* chip select pin */\r
  70         u8 n_bytes;             /* current is a 1/2/4 byte op */\r
  71         u8 tmode;               /* TR/TO/RO/EEPROM */\r
  72         u8 mode;                /* ??? */\r
  73         u8 type;                /* SPI/SSP/MicroWire */\r
  74 \r
  75         u8 poll_mode;           /* 1 means use poll mode */\r
  76 \r
  77         u32 dma_width;\r
  78         u32 rx_threshold;\r
  79         u32 tx_threshold;\r
  80         u8 enable_dma:1;\r
  81         u8 bits_per_word;\r
  82         u16 clk_div;            /* baud rate divider */\r
  83         u32 speed_hz;           /* baud rate */\r
  84         int (*write)(struct rk29xx_spi *dws);\r
  85         int (*read)(struct rk29xx_spi *dws);\r
  86         void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);\r
  87 };\r
  88 \r
  89 #define SUSPND    (1<<0)\r
  90 #define SPIBUSY   (1<<1)\r
  91 #define RXBUSY    (1<<2)\r
  92 #define TXBUSY    (1<<3)\r
  93 \r
  94 //\r
  95 #ifdef CONFIG_LCD_USE_SPIM_CONTROL\r
  96 void rk29_lcd_spim_spin_lock(void)\r
  97 {\r
  98 #ifdef CONFIG_LCD_USE_SPI0\r
  99         disable_irq(IRQ_SPI0);\r
 100 #endif\r
 101 \r
 102 #ifdef CONFIG_LCD_USE_SPI1\r
 103         disable_irq(IRQ_SPI1);\r
 104 #endif\r
 105 \r
 106         preempt_disable();\r
 107 }\r
 108 \r
 109 void rk29_lcd_spim_spin_unlock(void)\r
 110 {\r
 111         preempt_enable();\r
 112         \r
 113 #ifdef CONFIG_LCD_USE_SPI0\r
 114         enable_irq(IRQ_SPI0);\r
 115 #endif\r
 116 \r
 117 #ifdef CONFIG_LCD_USE_SPI1\r
 118         enable_irq(IRQ_SPI1);\r
 119 #endif\r
 120 }\r
 121 #else\r
 122 void rk29_lcd_spim_spin_lock(void)\r
 123 {\r
 124      return;\r
 125 }\r
 126 \r
 127 void rk29_lcd_spim_spin_unlock(void)\r
 128 {\r
 129      return;\r
 130 }\r
 131 #endif\r
 132 \r
 133 #if defined(PRINT_TRANS_DATA)\r
 134 static void printk_transfer_data(unsigned char *buf, int len)\r
 135 {\r
 136         int i = 0;\r
 137         for(i=0; i<len; i++)\r
 138                 printk("0x%x,",*buf++);\r
 139 \r
 140         printk("\n");\r
 141 \r
 142 }\r
 143 #endif\r
 144 \r
 145 #if 0\r
 146 static void spi_dump_regs(struct rk29xx_spi *dws) {\r
 147         DBG("MRST SPI0 registers:\n");\r
 148         DBG("=================================\n");\r
 149         DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 150         DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 151         DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 152         DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 153         DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 154         DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 155         DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 156         DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 157         DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 158         DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 159         DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 160         DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 161         DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 162         DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 163         DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 164         DBG("=================================\n");\r
 165 \r
 166 }\r
 167 #endif\r
 168 \r
 169 #ifdef CONFIG_DEBUG_FS\r
 170 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 171 {\r
 172         file->private_data = inode->i_private;\r
 173         return 0;\r
 174 }\r
 175 \r
 176 #define SPI_REGS_BUFSIZE        1024\r
 177 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,\r
 178                                 size_t count, loff_t *ppos)\r
 179 {\r
 180         struct rk29xx_spi *dws;\r
 181         char *buf;\r
 182         u32 len = 0;\r
 183         ssize_t ret;\r
 184 \r
 185         dws = file->private_data;\r
 186 \r
 187         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);\r
 188         if (!buf)\r
 189                 return 0;\r
 190 \r
 191         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 192                         "MRST SPI0 registers:\n");\r
 193         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 194                         "=================================\n");\r
 195         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 196                         "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 197         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 198                         "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 199         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 200                         "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 201         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 202                         "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 203         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 204                         "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 205         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 206                         "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 207         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 208                         "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 209         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 210                         "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 211         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 212                         "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 213         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 214                         "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 215         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 216                         "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 217         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 218                         "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 219         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 220                         "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 221         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 222                         "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 223         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 224                         "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 225         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 226                         "=================================\n");\r
 227 \r
 228         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);\r
 229         kfree(buf);\r
 230         return ret;\r
 231 }\r
 232 \r
 233 static const struct file_operations mrst_spi_regs_ops = {\r
 234         .owner          = THIS_MODULE,\r
 235         .open           = spi_show_regs_open,\r
 236         .read           = spi_show_regs,\r
 237 };\r
 238 \r
 239 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 240 {\r
 241         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);\r
 242         if (!dws->debugfs)\r
 243                 return -ENOMEM;\r
 244 \r
 245         debugfs_create_file("registers", S_IFREG | S_IRUGO,\r
 246                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);\r
 247         return 0;\r
 248 }\r
 249 \r
 250 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 251 {\r
 252         if (dws->debugfs)\r
 253                 debugfs_remove_recursive(dws->debugfs);\r
 254 }\r
 255 \r
 256 #else\r
 257 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 258 {\r
 259         return 0;\r
 260 }\r
 261 \r
 262 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 263 {\r
 264 }\r
 265 #endif /* CONFIG_DEBUG_FS */\r
 266 \r
 267 static void dma_transfer(struct rk29xx_spi *dws) ;\r
 268 static void transfer_complete(struct rk29xx_spi *dws);\r
 269 \r
 270 static void wait_till_not_busy(struct rk29xx_spi *dws)\r
 271 {\r
 272         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 273 \r
 274         while (time_before(jiffies, end)) {\r
 275                 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
 276                         return;\r
 277         }\r
 278         dev_err(&dws->master->dev,\r
 279                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 280 }\r
 281 \r
 282 #if defined(QUICK_TRANSFER)\r
 283 static void wait_till_tf_empty(struct rk29xx_spi *dws)\r
 284 {\r
 285         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 286 \r
 287         while (time_before(jiffies, end)) {\r
 288                 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)\r
 289                         return;\r
 290         }\r
 291         dev_err(&dws->master->dev,\r
 292                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 293 }\r
 294 #endif\r
 295 \r
 296 static void flush(struct rk29xx_spi *dws)\r
 297 {\r
 298         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 299                 rk29xx_readw(dws, SPIM_RXDR);\r
 300 \r
 301         wait_till_not_busy(dws);\r
 302 }\r
 303 \r
 304 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 305 {\r
 306         #if 1\r
 307         if (flag)\r
 308                 rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 309         else            \r
 310                 rk29xx_writel(dws, SPIM_SER, 0);\r
 311         return;\r
 312         #else\r
 313         \r
 314         #error "Warning: not support"\r
 315         struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
 316         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 317 \r
 318         if (flag == 0) {\r
 319                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
 320         }\r
 321         else {\r
 322                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
 323         }\r
 324         #endif\r
 325 }\r
 326 \r
 327 static int null_writer(struct rk29xx_spi *dws)\r
 328 {\r
 329         u8 n_bytes = dws->n_bytes;\r
 330 \r
 331         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 332                 || (dws->tx == dws->tx_end))\r
 333                 return 0;\r
 334         rk29xx_writew(dws, SPIM_TXDR, 0);\r
 335         dws->tx += n_bytes;\r
 336         //wait_till_not_busy(dws);\r
 337 \r
 338         return 1;\r
 339 }\r
 340 \r
 341 static int null_reader(struct rk29xx_spi *dws)\r
 342 {\r
 343         u8 n_bytes = dws->n_bytes;\r
 344         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 345         while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 346                 && (dws->rx < dws->rx_end)) {\r
 347                 rk29xx_readw(dws, SPIM_RXDR);\r
 348                 dws->rx += n_bytes;\r
 349         }\r
 350         wait_till_not_busy(dws);\r
 351         return dws->rx == dws->rx_end;\r
 352 }\r
 353 \r
 354 static int u8_writer(struct rk29xx_spi *dws)\r
 355 {       \r
 356         //spi_dump_regs(dws)\r
 357 #if defined(PRINT_TRANS_DATA)\r
 358         DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
 359 #endif\r
 360         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 361                 || (dws->tx == dws->tx_end))\r
 362                 return 0;\r
 363         rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));\r
 364         ++dws->tx;\r
 365         //wait_till_not_busy(dws);\r
 366 \r
 367         return 1;\r
 368 }\r
 369 \r
 370 static int u8_reader(struct rk29xx_spi *dws)\r
 371 {\r
 372     //spi_dump_regs(dws);\r
 373         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 374                 && (dws->rx < dws->rx_end)) {\r
 375                 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;\r
 376 #if defined(PRINT_TRANS_DATA)\r
 377                 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));\r
 378 #endif\r
 379                 ++dws->rx;\r
 380         }\r
 381 \r
 382         wait_till_not_busy(dws);\r
 383         return dws->rx == dws->rx_end;\r
 384 }\r
 385 \r
 386 static int u16_writer(struct rk29xx_spi *dws)\r
 387 {       \r
 388 #if defined(PRINT_TRANS_DATA)\r
 389         DBG("tx: 0x%04x\n", *(u16 *)(dws->tx));\r
 390 #endif\r
 391         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 392                 || (dws->tx == dws->tx_end))\r
 393                 return 0;\r
 394 \r
 395         rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));\r
 396         dws->tx += 2;\r
 397         //wait_till_not_busy(dws);\r
 398 \r
 399         return 1;\r
 400 }\r
 401 \r
 402 static int u16_reader(struct rk29xx_spi *dws)\r
 403 {\r
 404         u16 temp;\r
 405 \r
 406         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 407                 && (dws->rx < dws->rx_end)) {\r
 408                 temp = rk29xx_readw(dws, SPIM_RXDR);\r
 409                 *(u16 *)(dws->rx) = temp;\r
 410 #if defined(PRINT_TRANS_DATA)\r
 411                 DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));\r
 412 #endif\r
 413                 dws->rx += 2;\r
 414         }\r
 415 \r
 416         wait_till_not_busy(dws);\r
 417         return dws->rx == dws->rx_end;\r
 418 }\r
 419 \r
 420 static void *next_transfer(struct rk29xx_spi *dws)\r
 421 {\r
 422         struct spi_message *msg = dws->cur_msg;\r
 423         struct spi_transfer *trans = dws->cur_transfer;\r
 424 \r
 425         /* Move to next transfer */\r
 426         if (trans->transfer_list.next != &msg->transfers) {\r
 427                 dws->cur_transfer =\r
 428                         list_entry(trans->transfer_list.next,\r
 429                                         struct spi_transfer,\r
 430                                         transfer_list);\r
 431                 return RUNNING_STATE;\r
 432         } else\r
 433                 return DONE_STATE;\r
 434 }\r
 435 \r
 436 static void rk29_spi_dma_rxcb(void *buf_id,\r
 437                                  int size, enum rk29_dma_buffresult res)\r
 438 {\r
 439         struct rk29xx_spi *dws = buf_id;\r
 440         unsigned long flags;\r
 441 \r
 442         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 443         \r
 444         spin_lock_irqsave(&dws->lock, flags);\r
 445 \r
 446         if (res == RK29_RES_OK)\r
 447                 dws->state &= ~RXBUSY;\r
 448         else\r
 449                 dev_err(&dws->master->dev, "error:DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);\r
 450 \r
 451         //copy data from dma to transfer buf\r
 452         if(dws->cur_transfer && (dws->cur_transfer->rx_buf != NULL))\r
 453         {\r
 454                 memcpy(dws->cur_transfer->rx_buf, dws->buffer_rx_dma, dws->cur_transfer->len);\r
 455                 \r
 456                 #if defined(PRINT_TRANS_DATA)\r
 457                 printk("dma rx:");\r
 458                 printk_transfer_data(dws->cur_transfer->rx_buf, dws->cur_transfer->len);\r
 459                 #endif\r
 460         }\r
 461         \r
 462         spin_unlock_irqrestore(&dws->lock, flags);\r
 463         \r
 464         /* If the other done */\r
 465         if (!(dws->state & TXBUSY))\r
 466         {\r
 467                 //complete(&dws->xfer_completion);      \r
 468                 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);\r
 469                 //DMA could not lose intterupt\r
 470                 transfer_complete(dws);\r
 471         }\r
 472 \r
 473 }\r
 474 \r
 475 static void rk29_spi_dma_txcb(void *buf_id,\r
 476                                  int size, enum rk29_dma_buffresult res)\r
 477 {\r
 478         struct rk29xx_spi *dws = buf_id;\r
 479         unsigned long flags;\r
 480 \r
 481         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 482         \r
 483         spin_lock_irqsave(&dws->lock, flags);\r
 484 \r
 485         if (res == RK29_RES_OK)\r
 486                 dws->state &= ~TXBUSY;\r
 487         else\r
 488                 dev_err(&dws->master->dev, "error:DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);\r
 489 \r
 490         spin_unlock_irqrestore(&dws->lock, flags);\r
 491         \r
 492         /* If the other done */\r
 493         if (!(dws->state & RXBUSY)) \r
 494         {\r
 495                 //complete(&dws->xfer_completion);\r
 496                 \r
 497                 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);\r
 498                 //DMA could not lose intterupt\r
 499                 transfer_complete(dws);\r
 500         }\r
 501 \r
 502 }\r
 503 \r
 504 \r
 505 static struct rk29_dma_client rk29_spi_dma_client = {\r
 506         .name = "rk29xx-spi-dma",\r
 507 };\r
 508 \r
 509 static int acquire_dma(struct rk29xx_spi *dws)\r
 510 {       \r
 511         if (dws->dma_inited) {\r
 512                 return 0;\r
 513         }\r
 514 \r
 515         dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);\r
 516         if (!dws->buffer_tx_dma)\r
 517         {\r
 518                 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");\r
 519                 return -1;\r
 520         }\r
 521 \r
 522         dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);\r
 523         if (!dws->buffer_rx_dma)\r
 524         {\r
 525                 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");\r
 526                 return -1;\r
 527         }\r
 528 \r
 529         if(rk29_dma_request(dws->rx_dmach, \r
 530                 &rk29_spi_dma_client, NULL) < 0) {\r
 531                 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);\r
 532                 return -1;\r
 533         }\r
 534 \r
 535         if (rk29_dma_request(dws->tx_dmach,\r
 536                                         &rk29_spi_dma_client, NULL) < 0) {\r
 537                 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);\r
 538                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 539                 return -1;\r
 540         }\r
 541 \r
 542         if (dws->tx_dma) {\r
 543                 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {\r
 544                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 545                         return -1;\r
 546                 }\r
 547                 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
 548                                         dws->sfr_start + SPIM_TXDR)) {\r
 549                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 550                         return -1;\r
 551                 }\r
 552         }\r
 553 \r
 554         if (dws->rx_dma) {\r
 555                 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {\r
 556                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 557                         return -1;\r
 558                 }\r
 559                 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
 560                                         dws->sfr_start + SPIM_RXDR)) {\r
 561                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 562                         return -1;\r
 563                 }\r
 564         }\r
 565         \r
 566         dws->dma_inited = 1;\r
 567         return 0;\r
 568 }\r
 569 \r
 570 static void release_dma(struct rk29xx_spi *dws)\r
 571 {\r
 572         if(!dws && dws->dma_inited) {\r
 573                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 574                 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);\r
 575         }\r
 576 }\r
 577 \r
 578 /*\r
 579  * Note: first step is the protocol driver prepares\r
 580  * a dma-capable memory, and this func just need translate\r
 581  * the virt addr to physical\r
 582  */\r
 583 static int map_dma_buffers(struct rk29xx_spi *dws)\r
 584 {\r
 585         if (!dws->dma_inited || !dws->cur_chip->enable_dma)\r
 586         {\r
 587                 printk("%s:error\n",__func__);\r
 588                 return -1;\r
 589         }\r
 590 \r
 591         if(dws->cur_transfer->tx_buf)\r
 592         {\r
 593                 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);\r
 594         }\r
 595         \r
 596         dws->cur_transfer->tx_dma = dws->tx_dma;\r
 597         dws->cur_transfer->rx_dma = dws->rx_dma;\r
 598         \r
 599         return 0;\r
 600 }\r
 601 \r
 602 /* Caller already set message->status; dma and pio irqs are blocked */\r
 603 static void giveback(struct rk29xx_spi *dws)\r
 604 {\r
 605         struct spi_transfer *last_transfer;\r
 606         unsigned long flags;\r
 607         struct spi_message *msg;\r
 608 \r
 609         spin_lock_irqsave(&dws->lock, flags);\r
 610         msg = dws->cur_msg;\r
 611         dws->cur_msg = NULL;\r
 612         dws->cur_transfer = NULL;\r
 613         dws->prev_chip = dws->cur_chip;\r
 614         dws->cur_chip = NULL;\r
 615         dws->dma_mapped = 0;\r
 616         \r
 617         /*it is important to close intterrupt*/\r
 618         spi_mask_intr(dws, 0xff);\r
 619         rk29xx_writew(dws, SPIM_DMACR, 0);\r
 620         \r
 621         queue_work(dws->workqueue, &dws->pump_messages);\r
 622         spin_unlock_irqrestore(&dws->lock, flags);\r
 623 \r
 624         last_transfer = list_entry(msg->transfers.prev,\r
 625                                         struct spi_transfer,\r
 626                                         transfer_list);\r
 627 \r
 628         if (!last_transfer->cs_change && dws->cs_control)\r
 629                 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 630 \r
 631         msg->state = NULL;\r
 632         if (msg->complete)\r
 633                 msg->complete(msg->context);\r
 634 \r
 635         DBG("%s ok\n",__func__);\r
 636 \r
 637 }\r
 638 \r
 639 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)\r
 640 {\r
 641         /* Stop and reset hw */\r
 642         flush(dws);\r
 643         spi_enable_chip(dws, 0);\r
 644 \r
 645         dev_err(&dws->master->dev, "%s\n", msg);\r
 646         dws->cur_msg->state = ERROR_STATE;\r
 647         tasklet_schedule(&dws->pump_transfers);\r
 648 }\r
 649 \r
 650 static void transfer_complete(struct rk29xx_spi *dws)\r
 651 {\r
 652         /* Update total byte transfered return count actual bytes read */\r
 653         dws->cur_msg->actual_length += dws->len;\r
 654 \r
 655         /* Move to next transfer */\r
 656         dws->cur_msg->state = next_transfer(dws);\r
 657 \r
 658         /* Handle end of message */\r
 659         if (dws->cur_msg->state == DONE_STATE) {\r
 660                 dws->cur_msg->status = 0;\r
 661                 giveback(dws);\r
 662         } else\r
 663                 tasklet_schedule(&dws->pump_transfers);\r
 664 }\r
 665 \r
 666 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 667 {\r
 668         u16 irq_status, irq_mask = 0x1f;\r
 669         u32 int_level = dws->fifo_len / 2;\r
 670         u32 left;\r
 671 \r
 672         irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;\r
 673         /* Error handling */\r
 674         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {\r
 675                 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);\r
 676                 int_error_stop(dws, "interrupt_transfer: fifo overrun");\r
 677                 mutex_unlock(&dws->dma_lock);   \r
 678                 return IRQ_HANDLED;\r
 679         }\r
 680 \r
 681         if (irq_status & SPI_INT_TXEI) {\r
 682                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 683 \r
 684                 left = (dws->tx_end - dws->tx) / dws->n_bytes;\r
 685                 left = (left > int_level) ? int_level : left;\r
 686 \r
 687                 while (left--) {\r
 688                         dws->write(dws);\r
 689                         wait_till_not_busy(dws);\r
 690                 }\r
 691                 if (dws->rx) {\r
 692                     dws->read(dws);\r
 693                 }\r
 694 \r
 695                 /* Re-enable the IRQ if there is still data left to tx */\r
 696                 if (dws->tx_end > dws->tx)\r
 697                         spi_umask_intr(dws, SPI_INT_TXEI);\r
 698                 else\r
 699                         transfer_complete(dws);\r
 700         }\r
 701 \r
 702         if (irq_status & SPI_INT_RXFI) {\r
 703                 spi_mask_intr(dws, SPI_INT_RXFI);\r
 704                 \r
 705                 dws->read(dws);\r
 706 \r
 707                 /* Re-enable the IRQ if there is still data left to rx */\r
 708                 if (dws->rx_end > dws->rx) {\r
 709                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;\r
 710                     left = (left > int_level) ? int_level : left;\r
 711 \r
 712                         rk29xx_writew(dws, SPIM_RXFTLR, left);\r
 713                         spi_umask_intr(dws, SPI_INT_RXFI);\r
 714                 }\r
 715                 else {\r
 716                         transfer_complete(dws);\r
 717                 }\r
 718                 \r
 719         }       \r
 720 \r
 721         return IRQ_HANDLED;\r
 722 }\r
 723 \r
 724 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)\r
 725 {\r
 726         struct rk29xx_spi *dws = dev_id;\r
 727 \r
 728         if (!dws->cur_msg) {\r
 729                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 730                 /* Never fail */\r
 731                 return IRQ_HANDLED;\r
 732         }\r
 733 \r
 734         return dws->transfer_handler(dws);\r
 735 }\r
 736 \r
 737 /* Must be called inside pump_transfers() */\r
 738 static void poll_transfer(struct rk29xx_spi *dws)\r
 739 {\r
 740 #if defined(PRINT_TRANS_DATA)\r
 741         DBG("%s\n",__func__);\r
 742 #endif\r
 743         while (dws->write(dws)) {\r
 744                 wait_till_not_busy(dws);\r
 745                 dws->read(dws);\r
 746         }\r
 747         transfer_complete(dws);\r
 748 }\r
 749 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)\r
 750 {\r
 751     if(cs >= dws->master->num_chipselect)\r
 752                 return;\r
 753 \r
 754         if (dws->cs_control){\r
 755             dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
 756         }\r
 757         rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 758 }\r
 759 \r
 760 static void pump_transfers(unsigned long data)\r
 761 {\r
 762         struct rk29xx_spi *dws = (struct rk29xx_spi *)data;\r
 763         struct spi_message *message = NULL;\r
 764         struct spi_transfer *transfer = NULL;\r
 765         struct spi_transfer *previous = NULL;\r
 766         struct spi_device *spi = NULL;\r
 767         struct chip_data *chip = NULL;\r
 768         u8 bits = 0;\r
 769         u8 spi_dfs = 0;\r
 770         u8 imask = 0;\r
 771         u8 cs_change = 0;\r
 772         u16 txint_level = 0;\r
 773         u16 rxint_level = 0;\r
 774         u16 clk_div = 0;\r
 775         u32 speed = 0;\r
 776         u32 cr0 = 0;\r
 777 \r
 778         if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){      \r
 779                 dma_transfer(dws);\r
 780                 return;\r
 781         }       \r
 782         \r
 783         DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);\r
 784 \r
 785         /* Get current state information */\r
 786         message = dws->cur_msg;\r
 787         transfer = dws->cur_transfer;\r
 788         chip = dws->cur_chip;\r
 789         spi = message->spi;     \r
 790         if (unlikely(!chip->clk_div))\r
 791                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 792         if (message->state == ERROR_STATE) {\r
 793                 message->status = -EIO;\r
 794                 goto early_exit;\r
 795         }\r
 796 \r
 797         /* Handle end of message */\r
 798         if (message->state == DONE_STATE) {\r
 799                 message->status = 0;\r
 800                 goto early_exit;\r
 801         }\r
 802 \r
 803         /* Delay if requested at end of transfer*/\r
 804         if (message->state == RUNNING_STATE) {\r
 805                 previous = list_entry(transfer->transfer_list.prev,\r
 806                                         struct spi_transfer,\r
 807                                         transfer_list);\r
 808                 if (previous->delay_usecs)\r
 809                         udelay(previous->delay_usecs);\r
 810         }\r
 811 \r
 812         dws->n_bytes = chip->n_bytes;\r
 813         dws->dma_width = chip->dma_width;\r
 814         dws->cs_control = chip->cs_control;\r
 815 \r
 816         //dws->rx_dma = transfer->rx_dma;\r
 817         //dws->tx_dma = transfer->tx_dma;\r
 818         dws->tx = (void *)transfer->tx_buf;\r
 819         dws->tx_end = dws->tx + transfer->len;\r
 820         dws->rx = (void *)transfer->rx_buf;\r
 821         dws->rx_end = dws->rx + transfer->len;\r
 822         dws->write = dws->tx ? chip->write : null_writer;\r
 823         dws->read = dws->rx ? chip->read : null_reader;\r
 824         dws->cs_change = transfer->cs_change;\r
 825         dws->len = dws->cur_transfer->len;\r
 826         if (chip != dws->prev_chip)\r
 827                 cs_change = 1;\r
 828 \r
 829         cr0 = chip->cr0;\r
 830 \r
 831         /* Handle per transfer options for bpw and speed */\r
 832         if (transfer->speed_hz) {\r
 833                 speed = chip->speed_hz;\r
 834 \r
 835                 if (transfer->speed_hz != speed) {\r
 836                         speed = transfer->speed_hz;\r
 837                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 838                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported "\r
 839                                         "freq: %dHz\n", speed);\r
 840                                 message->status = -EIO;\r
 841                                 goto early_exit;\r
 842                         }\r
 843 \r
 844                         /* clk_div doesn't support odd number */\r
 845                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 846                         clk_div = (clk_div + 1) & 0xfffe;\r
 847 \r
 848                         chip->speed_hz = speed;\r
 849                         chip->clk_div = clk_div;\r
 850                 }\r
 851         }\r
 852         \r
 853         if (transfer->bits_per_word) {\r
 854                 bits = transfer->bits_per_word;\r
 855 \r
 856                 switch (bits) {\r
 857                 case 8:\r
 858                         dws->n_bytes = 1;\r
 859                         dws->dma_width = 1;\r
 860                         dws->read = (dws->read != null_reader) ?\r
 861                                         u8_reader : null_reader;\r
 862                         dws->write = (dws->write != null_writer) ?\r
 863                                         u8_writer : null_writer;\r
 864                         spi_dfs = SPI_DFS_8BIT;\r
 865                         break;\r
 866                 case 16:\r
 867                         dws->n_bytes = 2;\r
 868                         dws->dma_width = 2;\r
 869                         dws->read = (dws->read != null_reader) ?\r
 870                                         u16_reader : null_reader;\r
 871                         dws->write = (dws->write != null_writer) ?\r
 872                                         u16_writer : null_writer;\r
 873                         spi_dfs = SPI_DFS_16BIT;\r
 874                         break;\r
 875                 default:\r
 876                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 877                                 "%db\n", bits);\r
 878                         message->status = -EIO;\r
 879                         goto early_exit;\r
 880                 }\r
 881 \r
 882                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 883                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 884                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 885                         | (chip->type << SPI_FRF_OFFSET)\r
 886                         | (spi->mode << SPI_MODE_OFFSET)\r
 887                         | (chip->tmode << SPI_TMOD_OFFSET);\r
 888         }\r
 889         message->state = RUNNING_STATE;\r
 890  \r
 891         /*\r
 892          * Adjust transfer mode if necessary. Requires platform dependent\r
 893          * chipselect mechanism.\r
 894          */\r
 895         if (dws->cs_control) {\r
 896                 if (dws->rx && dws->tx)\r
 897                         chip->tmode = SPI_TMOD_TR;\r
 898                 else if (dws->rx)\r
 899                         chip->tmode = SPI_TMOD_RO;\r
 900                 else\r
 901                         chip->tmode = SPI_TMOD_TO;\r
 902 \r
 903                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);               \r
 904                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);       \r
 905                 cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
 906                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
 907         } \r
 908 \r
 909         /*\r
 910          * Interrupt mode\r
 911          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely\r
 912          */\r
 913         if (!dws->dma_mapped && !chip->poll_mode) {     \r
 914                 int templen ;\r
 915                 \r
 916                 if (chip->tmode == SPI_TMOD_RO) {\r
 917                         templen = dws->len / dws->n_bytes - 1;\r
 918                         rxint_level = dws->fifo_len / 2;\r
 919                         rxint_level = (templen > rxint_level) ? rxint_level : templen;\r
 920                         imask |= SPI_INT_RXFI;\r
 921                 }\r
 922                 else {  \r
 923                         templen = dws->len / dws->n_bytes;\r
 924                         txint_level = dws->fifo_len / 2;\r
 925                         txint_level = (templen > txint_level) ? txint_level : templen;\r
 926                         imask |= SPI_INT_TXEI;\r
 927                 }\r
 928                 dws->transfer_handler = interrupt_transfer;\r
 929         }\r
 930 \r
 931         /*\r
 932          * Reprogram registers only if\r
 933          *      1. chip select changes\r
 934          *      2. clk_div is changed\r
 935          *      3. control value changes\r
 936          */\r
 937         if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div || imask) {\r
 938                 spi_enable_chip(dws, 0);\r
 939                 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)\r
 940                         rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
 941 \r
 942                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
 943                 spi_chip_sel(dws, spi->chip_select);\r
 944 \r
 945         rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
 946                 spi_enable_chip(dws, 1);\r
 947 \r
 948                 if (txint_level)\r
 949                         rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
 950                 if (rxint_level)\r
 951                         rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
 952                 /* Set the interrupt mask, for poll mode just diable all int */\r
 953                 spi_mask_intr(dws, 0xff);\r
 954                 if (imask)\r
 955                         spi_umask_intr(dws, imask);\r
 956                 \r
 957                 if (cs_change)\r
 958                         dws->prev_chip = chip;\r
 959         } \r
 960 \r
 961         if (chip->poll_mode)\r
 962                 poll_transfer(dws);\r
 963 \r
 964         return;\r
 965 \r
 966 early_exit:\r
 967         giveback(dws);\r
 968         return;\r
 969 }\r
 970 \r
 971 static void dma_transfer(struct rk29xx_spi *dws) \r
 972 {\r
 973         struct spi_message *message = NULL;\r
 974         struct spi_transfer *transfer = NULL;\r
 975         struct spi_transfer *previous = NULL;\r
 976         struct spi_device *spi = NULL;\r
 977         struct chip_data *chip = NULL;\r
 978         //unsigned long val;    \r
 979         //unsigned long flags;\r
 980         //int ms;\r
 981         int iRet;\r
 982         //int burst;\r
 983         u8 bits = 0;\r
 984         u8 spi_dfs = 0;\r
 985         u8 cs_change = 0;\r
 986         u16 clk_div = 0;\r
 987         u32 speed = 0;\r
 988         u32 cr0 = 0;\r
 989         u32 dmacr = 0;\r
 990         \r
 991         DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);  \r
 992         \r
 993         if (acquire_dma(dws)) {\r
 994                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 995                 goto err_out;\r
 996         }\r
 997 \r
 998         if (map_dma_buffers(dws)) {\r
 999                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
1000                 goto err_out;\r
1001         }\r
1002 \r
1003         /* Get current state information */\r
1004         message = dws->cur_msg;\r
1005         transfer = dws->cur_transfer;\r
1006         chip = dws->cur_chip;\r
1007         spi = message->spi;     \r
1008         if (unlikely(!chip->clk_div))\r
1009                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
1010         if (message->state == ERROR_STATE) {\r
1011                 message->status = -EIO;\r
1012                 goto err_out;\r
1013         }\r
1014 \r
1015         /* Handle end of message */\r
1016         if (message->state == DONE_STATE) {\r
1017                 message->status = 0;\r
1018                 goto err_out;\r
1019         }\r
1020 \r
1021         /* Delay if requested at end of transfer*/\r
1022         if (message->state == RUNNING_STATE) {\r
1023                 previous = list_entry(transfer->transfer_list.prev,\r
1024                                         struct spi_transfer,\r
1025                                         transfer_list);\r
1026                 if (previous->delay_usecs)\r
1027                         udelay(previous->delay_usecs);\r
1028         }\r
1029 \r
1030         dws->n_bytes = chip->n_bytes;\r
1031         dws->dma_width = chip->dma_width;\r
1032         dws->cs_control = chip->cs_control;\r
1033 \r
1034         //dws->rx_dma = transfer->rx_dma;\r
1035         //dws->tx_dma = transfer->tx_dma;\r
1036         dws->tx = (void *)transfer->tx_buf;\r
1037         dws->tx_end = dws->tx + transfer->len;\r
1038         dws->rx = (void *)transfer->rx_buf;\r
1039         dws->rx_end = dws->rx + transfer->len;\r
1040         dws->write = dws->tx ? chip->write : null_writer;\r
1041         dws->read = dws->rx ? chip->read : null_reader;\r
1042         dws->cs_change = transfer->cs_change;\r
1043         dws->len = dws->cur_transfer->len;\r
1044         if (chip != dws->prev_chip)\r
1045                 cs_change = 1;\r
1046 \r
1047         cr0 = chip->cr0;\r
1048         \r
1049         /* Handle per transfer options for bpw and speed */\r
1050         if (transfer->speed_hz) {\r
1051                 speed = chip->speed_hz;\r
1052                 if (transfer->speed_hz != speed) {\r
1053                         speed = transfer->speed_hz;\r
1054                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1055                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported "\r
1056                                         "freq: %dHz\n", speed);\r
1057                                 message->status = -EIO;\r
1058                                 goto err_out;\r
1059                         }\r
1060 \r
1061                         /* clk_div doesn't support odd number */\r
1062                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1063                         clk_div = (clk_div + 1) & 0xfffe;\r
1064 \r
1065                         chip->speed_hz = speed;\r
1066                         chip->clk_div = clk_div;\r
1067                 }\r
1068         }\r
1069 \r
1070         \r
1071         if (transfer->bits_per_word) {\r
1072                 bits = transfer->bits_per_word;\r
1073 \r
1074                 switch (bits) {\r
1075                 case 8:\r
1076                         dws->n_bytes = 1;\r
1077                         dws->dma_width = 1;\r
1078                         spi_dfs = SPI_DFS_8BIT;\r
1079                         break;\r
1080                 case 16:\r
1081                         dws->n_bytes = 2;\r
1082                         dws->dma_width = 2;\r
1083                         spi_dfs = SPI_DFS_16BIT;\r
1084                         break;\r
1085                 default:\r
1086                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1087                                 "%db\n", bits);\r
1088                         message->status = -EIO;\r
1089                         goto err_out;\r
1090                 }\r
1091 \r
1092                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1093                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1094                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1095                         | (chip->type << SPI_FRF_OFFSET)\r
1096                         | (spi->mode << SPI_MODE_OFFSET)\r
1097                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1098         }\r
1099         message->state = RUNNING_STATE;\r
1100  \r
1101         /*\r
1102          * Adjust transfer mode if necessary. Requires platform dependent\r
1103          * chipselect mechanism.\r
1104          */\r
1105         if (dws->cs_control) {\r
1106                 if (dws->rx && dws->tx)\r
1107                         chip->tmode = SPI_TMOD_TR;\r
1108                 else if (dws->rx)\r
1109                         chip->tmode = SPI_TMOD_RO;\r
1110                 else\r
1111                         chip->tmode = SPI_TMOD_TO;\r
1112 \r
1113                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1114                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);               \r
1115                 cr0 |= (chip->mode << SPI_MODE_OFFSET);\r
1116                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1117         }\r
1118 \r
1119         /*\r
1120          * Reprogram registers only if\r
1121          *      1. chip select changes\r
1122          *      2. clk_div is changed\r
1123          *      3. control value changes\r
1124          */\r
1125         if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div) {\r
1126                 spi_enable_chip(dws, 0);\r
1127                 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0) {\r
1128                         rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
1129                 }\r
1130                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1131                 spi_chip_sel(dws, spi->chip_select);\r
1132                 /* Set the interrupt mask, for poll mode just diable all int */\r
1133                 spi_mask_intr(dws, 0xff);\r
1134                 \r
1135                 if (transfer->tx_buf != NULL) {\r
1136                         dmacr |= SPI_DMACR_TX_ENABLE;\r
1137                         rk29xx_writew(dws, SPIM_DMATDLR, 0);\r
1138                 }\r
1139                 if (transfer->rx_buf != NULL) {\r
1140                         dmacr |= SPI_DMACR_RX_ENABLE;\r
1141                         rk29xx_writew(dws, SPIM_DMARDLR, 0);\r
1142                         rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);       \r
1143                 }\r
1144                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1145                 spi_enable_chip(dws, 1);\r
1146                 if (cs_change)\r
1147                         dws->prev_chip = chip;\r
1148         } \r
1149 \r
1150         //INIT_COMPLETION(dws->xfer_completion);\r
1151 \r
1152         //spi_dump_regs(dws);\r
1153         \r
1154         DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, dws->tx_dma: 0x%x,dws->rx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)dws->tx_dma,(unsigned int)dws->rx_dma);  \r
1155         DBG("dws->buffer_tx_dma: 0x%p, dws->buffer_rx_dma: 0x%p,dws->dma_width=%d\n", dws->buffer_tx_dma, dws->buffer_rx_dma,dws->dma_width);   \r
1156 \r
1157         if (transfer->tx_buf != NULL)           \r
1158                 dws->state |= TXBUSY;   \r
1159         if (transfer->rx_buf != NULL) \r
1160                 dws->state |= RXBUSY;\r
1161 \r
1162         if (transfer->tx_buf != NULL) { \r
1163                 DBG("%s:start dma tx,dws->state=0x%x\n",__func__,dws->state);\r
1164                 #if defined(PRINT_TRANS_DATA)\r
1165                 printk("dma tx:");\r
1166                 printk_transfer_data(dws->buffer_tx_dma, dws->cur_transfer->len);\r
1167                 #endif\r
1168                 /*if (transfer->len & 0x3) {\r
1169                         burst = 1;\r
1170                 }\r
1171                 else {\r
1172                         burst = 4;\r
1173                 }\r
1174                 if (rk29_dma_config(dws->tx_dmach, burst)) {*/\r
1175                 if (rk29_dma_config(dws->tx_dmach, dws->dma_width, 1)) {//there is not dma burst but bitwide, set it 1 alwayss\r
1176                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1177                         goto err_out;\r
1178                 }\r
1179                 \r
1180                 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH); \r
1181                 \r
1182                 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,\r
1183                                         dws->tx_dma, transfer->len);\r
1184                 if (iRet) {\r
1185                         dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet, \r
1186                                 dws->tx_dmach, (unsigned int)transfer->tx_dma);\r
1187                         goto err_out;\r
1188                 }\r
1189                 \r
1190                 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {\r
1191                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1192                         goto err_out;\r
1193                 }\r
1194         }\r
1195 \r
1196         //wait_till_not_busy(dws);\r
1197         \r
1198         if (transfer->rx_buf != NULL) {                 \r
1199                 DBG("%s:start dma rx,dws->state=0x%x\n",__func__,dws->state);\r
1200                 if (rk29_dma_config(dws->rx_dmach, dws->dma_width, 1)) {\r
1201                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1202                         goto err_out;\r
1203                 }\r
1204 \r
1205                 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH); \r
1206                 \r
1207                 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,\r
1208                                         dws->rx_dma, transfer->len);\r
1209                 if (iRet) {\r
1210                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1211                         goto err_out;\r
1212                 }\r
1213                 \r
1214                 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {\r
1215                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1216                         goto err_out;\r
1217                 }\r
1218         }\r
1219         \r
1220         //wait_till_not_busy(dws);\r
1221         \r
1222         return;\r
1223 \r
1224 err_out:\r
1225         giveback(dws);\r
1226         return;\r
1227 \r
1228 }\r
1229 \r
1230 static void pump_messages(struct work_struct *work)\r
1231 {\r
1232         struct rk29xx_spi *dws =\r
1233                 container_of(work, struct rk29xx_spi, pump_messages);\r
1234         unsigned long flags;\r
1235 \r
1236         DBG(KERN_INFO "pump_messages,line=%d\n",__LINE__);\r
1237         \r
1238         /* Lock queue and check for queue work */\r
1239         spin_lock_irqsave(&dws->lock, flags);\r
1240         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1241                 dws->busy = 0;\r
1242                 spin_unlock_irqrestore(&dws->lock, flags);\r
1243                 DBG("%s:line=%d,list_empty\n",__func__,__LINE__);\r
1244                 return;\r
1245         }\r
1246 \r
1247         /* Make sure we are not already running a message */\r
1248         if (dws->cur_msg) {\r
1249                 spin_unlock_irqrestore(&dws->lock, flags);              \r
1250                 DBG("%s:line=%d,dws->cur_msg\n",__func__,__LINE__);\r
1251                 return;\r
1252         }\r
1253 \r
1254         /* Extract head of queue */\r
1255         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1256         list_del_init(&dws->cur_msg->queue);\r
1257 \r
1258         /* Initial message state*/\r
1259         dws->cur_msg->state = START_STATE;\r
1260         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1261                                                 struct spi_transfer,\r
1262                                                 transfer_list);\r
1263         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1264         dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1265 \r
1266         \r
1267         /* Mark as busy and launch transfers */\r
1268         tasklet_schedule(&dws->pump_transfers);\r
1269         dws->busy = 1;\r
1270         spin_unlock_irqrestore(&dws->lock, flags);\r
1271         \r
1272 }\r
1273 \r
1274 #if defined(QUICK_TRANSFER)\r
1275 static void do_read(struct rk29xx_spi *dws)\r
1276 {\r
1277         int count = 0;\r
1278 \r
1279         spi_enable_chip(dws, 0);\r
1280         rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);\r
1281         spi_enable_chip(dws, 1);                \r
1282         rk29xx_writew(dws, SPIM_TXDR, 0);\r
1283         while (1) {\r
1284                 if (dws->read(dws))\r
1285                         break;\r
1286                 if (count++ == 0x20) {\r
1287                         dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");\r
1288                         break;\r
1289                 }\r
1290                 \r
1291         }\r
1292 }\r
1293 \r
1294 static void do_write(struct rk29xx_spi *dws)\r
1295 {\r
1296         while (dws->tx<dws->tx_end) {\r
1297                 dws->write(dws);\r
1298         }\r
1299 }\r
1300 \r
1301 /* Caller already set message->status; dma and pio irqs are blocked */\r
1302 static void msg_giveback(struct rk29xx_spi *dws)\r
1303 {\r
1304         struct spi_transfer *last_transfer;\r
1305         struct spi_message *msg;\r
1306 \r
1307         DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1308 \r
1309         msg = dws->cur_msg;\r
1310         dws->cur_msg = NULL;\r
1311         dws->cur_transfer = NULL;\r
1312         dws->prev_chip = dws->cur_chip;\r
1313         dws->cur_chip = NULL;\r
1314         dws->dma_mapped = 0;\r
1315         dws->busy = 0;\r
1316 \r
1317         last_transfer = list_entry(msg->transfers.prev,\r
1318                                         struct spi_transfer,\r
1319                                         transfer_list);\r
1320 \r
1321         if (!last_transfer->cs_change && dws->cs_control)\r
1322                 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
1323 \r
1324         msg->state = NULL;      \r
1325 }\r
1326 \r
1327 /* Must be called inside pump_transfers() */\r
1328 static int do_full_transfer(struct rk29xx_spi *dws)\r
1329 {\r
1330         if ((dws->read(dws))) {\r
1331                 goto comple;\r
1332         }\r
1333         \r
1334         while (dws->tx<dws->tx_end){\r
1335                 dws->write(dws);                \r
1336                 dws->read(dws);\r
1337         }\r
1338         \r
1339         if (dws->rx < dws->rx_end) {\r
1340                 dws->read(dws);\r
1341         }\r
1342 \r
1343 comple:\r
1344         \r
1345         dws->cur_msg->actual_length += dws->len;\r
1346         \r
1347         /* Move to next transfer */\r
1348         dws->cur_msg->state = next_transfer(dws);\r
1349                                         \r
1350         if (dws->cur_msg->state == DONE_STATE) {\r
1351                 dws->cur_msg->status = 0;\r
1352                 //msg_giveback(dws);\r
1353                 return 0;\r
1354         }\r
1355         else {\r
1356                 return -1;\r
1357         }\r
1358         \r
1359 }\r
1360 \r
1361 \r
1362 /* Must be called inside pump_transfers() */\r
1363 static int do_half_transfer(struct rk29xx_spi *dws)\r
1364 {\r
1365         if (dws->rx) {\r
1366                 if (dws->tx) {\r
1367                         do_write(dws);\r
1368                 }\r
1369                 wait_till_tf_empty(dws);\r
1370                 wait_till_not_busy(dws);\r
1371                 do_read(dws);\r
1372         }\r
1373         else {\r
1374                 do_write(dws);\r
1375                 wait_till_tf_empty(dws);\r
1376                 wait_till_not_busy(dws);\r
1377         }\r
1378         \r
1379         dws->cur_msg->actual_length += dws->len;\r
1380         \r
1381         /* Move to next transfer */\r
1382         dws->cur_msg->state = next_transfer(dws);\r
1383                                         \r
1384         if (dws->cur_msg->state == DONE_STATE) {\r
1385                 dws->cur_msg->status = 0;\r
1386                 //msg_giveback(dws);\r
1387                 return 0;\r
1388         }\r
1389         else {\r
1390                 return -1;\r
1391         }\r
1392 }\r
1393 \r
1394 \r
1395 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)\r
1396 {\r
1397         struct spi_message *message = NULL;\r
1398         struct spi_transfer *transfer = NULL;\r
1399         struct spi_transfer *previous = NULL;\r
1400         struct spi_device *spi = NULL;\r
1401         struct chip_data *chip = NULL;\r
1402         u8 bits = 0;\r
1403         u8 spi_dfs = 0;\r
1404         u8 cs_change = 0;\r
1405         u16 clk_div = 0;\r
1406         u32 speed = 0;\r
1407         u32 cr0 = 0;\r
1408         u32 dmacr = 0;\r
1409         \r
1410         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1411 \r
1412         /* Get current state information */\r
1413         message = dws->cur_msg;\r
1414         transfer = dws->cur_transfer;\r
1415         chip = dws->cur_chip;\r
1416         spi = message->spi;     \r
1417 \r
1418         if (unlikely(!chip->clk_div))\r
1419                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;\r
1420         if (message->state == ERROR_STATE) {\r
1421                 message->status = -EIO;\r
1422                 goto early_exit;\r
1423         }\r
1424 \r
1425         /* Handle end of message */\r
1426         if (message->state == DONE_STATE) {\r
1427                 message->status = 0;\r
1428                 goto early_exit;\r
1429         }\r
1430 \r
1431         /* Delay if requested at end of transfer*/\r
1432         if (message->state == RUNNING_STATE) {\r
1433                 previous = list_entry(transfer->transfer_list.prev,\r
1434                                         struct spi_transfer,\r
1435                                         transfer_list);\r
1436                 if (previous->delay_usecs)\r
1437                         udelay(previous->delay_usecs);\r
1438         }\r
1439 \r
1440         dws->n_bytes = chip->n_bytes;\r
1441         dws->dma_width = chip->dma_width;\r
1442         dws->cs_control = chip->cs_control;\r
1443 \r
1444         dws->rx_dma = transfer->rx_dma;\r
1445         dws->tx_dma = transfer->tx_dma;\r
1446         dws->tx = (void *)transfer->tx_buf;\r
1447         dws->tx_end = dws->tx + transfer->len;\r
1448         dws->rx = transfer->rx_buf;\r
1449         dws->rx_end = dws->rx + transfer->len;\r
1450         dws->write = dws->tx ? chip->write : null_writer;\r
1451         dws->read = dws->rx ? chip->read : null_reader;\r
1452         if (dws->rx && dws->tx) {\r
1453                 int temp_len = transfer->len;\r
1454                 int len;\r
1455                 unsigned char *tx_buf;\r
1456                 for (len=0; *tx_buf++ != 0; len++);\r
1457                 dws->tx_end = dws->tx + len;\r
1458                 dws->rx_end = dws->rx + temp_len - len;\r
1459         }\r
1460         dws->cs_change = transfer->cs_change;\r
1461         dws->len = dws->cur_transfer->len;\r
1462         if (chip != dws->prev_chip)\r
1463                 cs_change = 1;\r
1464 \r
1465         cr0 = chip->cr0;\r
1466 \r
1467         /* Handle per transfer options for bpw and speed */\r
1468         if (transfer->speed_hz) {\r
1469                 speed = chip->speed_hz;\r
1470 \r
1471                 if (transfer->speed_hz != speed) {\r
1472                         speed = transfer->speed_hz;\r
1473                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1474                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1475                                         "freq: %dHz\n", speed);\r
1476                                 message->status = -EIO;\r
1477                                 goto early_exit;\r
1478                         }\r
1479 \r
1480                         /* clk_div doesn't support odd number */\r
1481                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1482                         clk_div = (clk_div + 1) & 0xfffe;\r
1483 \r
1484                         chip->speed_hz = speed;\r
1485                         chip->clk_div = clk_div;\r
1486                 }\r
1487         }\r
1488         if (transfer->bits_per_word) {\r
1489                 bits = transfer->bits_per_word;\r
1490 \r
1491                 switch (bits) {\r
1492                 case 8:\r
1493                         dws->n_bytes = 1;\r
1494                         dws->dma_width = 1;\r
1495                         dws->read = (dws->read != null_reader) ?\r
1496                                         u8_reader : null_reader;\r
1497                         dws->write = (dws->write != null_writer) ?\r
1498                                         u8_writer : null_writer;\r
1499                         spi_dfs = SPI_DFS_8BIT;\r
1500                         break;\r
1501                 case 16:\r
1502                         dws->n_bytes = 2;\r
1503                         dws->dma_width = 2;\r
1504                         dws->read = (dws->read != null_reader) ?\r
1505                                         u16_reader : null_reader;\r
1506                         dws->write = (dws->write != null_writer) ?\r
1507                                         u16_writer : null_writer;\r
1508                         spi_dfs = SPI_DFS_16BIT;\r
1509                         break;\r
1510                 default:\r
1511                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1512                                 "%db\n", bits);\r
1513                         message->status = -EIO;\r
1514                         goto early_exit;\r
1515                 }\r
1516 \r
1517                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1518                         | (chip->type << SPI_FRF_OFFSET)\r
1519                         | (spi->mode << SPI_MODE_OFFSET)\r
1520                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1521         }\r
1522         message->state = RUNNING_STATE;\r
1523  \r
1524         /*\r
1525          * Adjust transfer mode if necessary. Requires platform dependent\r
1526          * chipselect mechanism.\r
1527          */\r
1528         if (dws->cs_control) {\r
1529                 if (dws->rx && dws->tx)\r
1530                         chip->tmode = SPI_TMOD_TR;\r
1531                 else if (dws->rx)\r
1532                         chip->tmode = SPI_TMOD_RO;\r
1533                 else\r
1534                         chip->tmode = SPI_TMOD_TO;\r
1535 \r
1536                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1537                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
1538                 cr0 |= (spi->mode << SPI_MODE_OFFSET);\r
1539                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1540         }\r
1541         \r
1542         /* Check if current transfer is a DMA transaction */\r
1543         dws->dma_mapped = map_dma_buffers(dws);\r
1544 \r
1545         /*\r
1546          * Reprogram registers only if\r
1547          *      1. chip select changes\r
1548          *      2. clk_div is changed\r
1549          *      3. control value changes\r
1550          */\r
1551         spi_enable_chip(dws, 0);\r
1552         if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)\r
1553                 rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
1554 \r
1555     DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);\r
1556         spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1557         spi_chip_sel(dws, spi->chip_select);            \r
1558         rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx\r
1559         if(dws->dma_mapped ) {\r
1560                 dmacr = rk29xx_readw(dws, SPIM_DMACR);\r
1561                 dmacr = dmacr | SPI_DMACR_TX_ENABLE;\r
1562                 if (mode) \r
1563                         dmacr = dmacr | SPI_DMACR_RX_ENABLE;\r
1564                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1565         }\r
1566         spi_enable_chip(dws, 1);\r
1567         if (cs_change)\r
1568                 dws->prev_chip = chip;\r
1569         \r
1570         if (mode)\r
1571                 return do_full_transfer(dws);\r
1572         else\r
1573                 return do_half_transfer(dws);   \r
1574         \r
1575 early_exit:\r
1576         \r
1577         //msg_giveback(dws);\r
1578         \r
1579         return 0;\r
1580 }\r
1581 \r
1582 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)\r
1583 {\r
1584         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1585         \r
1586         while (!acquire_dma(dws))\r
1587                         msleep(10);\r
1588 \r
1589         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1590                 dws->busy = 0;\r
1591                 return;\r
1592         }\r
1593 \r
1594         /* Make sure we are not already running a message */\r
1595         if (dws->cur_msg) {\r
1596                 return;\r
1597         }\r
1598 \r
1599         /* Extract head of queue */\r
1600         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1601         list_del_init(&dws->cur_msg->queue);\r
1602 \r
1603         /* Initial message state*/\r
1604         dws->cur_msg->state = START_STATE;\r
1605         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1606                                                 struct spi_transfer,\r
1607                                                 transfer_list);\r
1608         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1609     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1610     \r
1611         /* Mark as busy and launch transfers */\r
1612         dws->busy = 1;\r
1613 \r
1614         while (rk29xx_pump_transfers(dws, mode)) ;\r
1615 }\r
1616 \r
1617 /* spi_device use this to queue in their spi_msg */\r
1618 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)\r
1619 {\r
1620         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1621         unsigned long flags;\r
1622         struct rk29xx_spi_chip *chip_info = spi->controller_data;\r
1623         struct spi_message *mmsg;\r
1624         \r
1625         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1626         \r
1627         spin_lock_irqsave(&dws->lock, flags);\r
1628 \r
1629         if (dws->run == QUEUE_STOPPED) {\r
1630                 spin_unlock_irqrestore(&dws->lock, flags);\r
1631                 return -ESHUTDOWN;\r
1632         }\r
1633 \r
1634         msg->actual_length = 0;\r
1635         msg->status = -EINPROGRESS;\r
1636         msg->state = START_STATE;\r
1637 \r
1638         list_add_tail(&msg->queue, &dws->queue);\r
1639 \r
1640         if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {\r
1641                 rk29xx_pump_messages(dws,1);\r
1642         }\r
1643         else {          \r
1644                 rk29xx_pump_messages(dws,0);\r
1645         }\r
1646 \r
1647         mmsg = dws->cur_msg;\r
1648         msg_giveback(dws);\r
1649         \r
1650         spin_unlock_irqrestore(&dws->lock, flags);\r
1651 \r
1652         if (mmsg->complete)\r
1653                 mmsg->complete(mmsg->context);\r
1654         \r
1655         return 0;\r
1656 }\r
1657 \r
1658 #else\r
1659 \r
1660 /* spi_device use this to queue in their spi_msg */\r
1661 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)\r
1662 {\r
1663         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1664         unsigned long flags;\r
1665 \r
1666         spin_lock_irqsave(&dws->lock, flags);\r
1667 \r
1668         if (dws->run == QUEUE_STOPPED) {\r
1669                 spin_unlock_irqrestore(&dws->lock, flags);\r
1670                 return -ESHUTDOWN;\r
1671         }\r
1672 \r
1673         msg->actual_length = 0;\r
1674         msg->status = -EINPROGRESS;\r
1675         msg->state = START_STATE;\r
1676 \r
1677         list_add_tail(&msg->queue, &dws->queue);\r
1678 \r
1679         if (dws->run == QUEUE_RUNNING && !dws->busy) {\r
1680 \r
1681                 if (dws->cur_transfer || dws->cur_msg)\r
1682                         queue_work(dws->workqueue,\r
1683                                         &dws->pump_messages);\r
1684                 else {\r
1685                         /* If no other data transaction in air, just go */\r
1686                         spin_unlock_irqrestore(&dws->lock, flags);\r
1687                         pump_messages(&dws->pump_messages);                     \r
1688                         return 0;\r
1689                 }\r
1690         }\r
1691 \r
1692         spin_unlock_irqrestore(&dws->lock, flags);\r
1693         \r
1694         return 0;\r
1695 }\r
1696 \r
1697 #endif\r
1698 \r
1699 /* This may be called twice for each spi dev */\r
1700 static int rk29xx_spi_setup(struct spi_device *spi)\r
1701 {\r
1702         struct rk29xx_spi_chip *chip_info = NULL;\r
1703         struct chip_data *chip;\r
1704         u8 spi_dfs = 0;\r
1705 \r
1706         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)\r
1707                 return -EINVAL;\r
1708 \r
1709         /* Only alloc on first setup */\r
1710         chip = spi_get_ctldata(spi);\r
1711         if (!chip) {\r
1712                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\r
1713                 if (!chip)\r
1714                         return -ENOMEM;\r
1715 \r
1716                 chip->cs_control = spi_cs_control;\r
1717                 chip->enable_dma = 0;  //0;\r
1718         }\r
1719 \r
1720         /*\r
1721          * Protocol drivers may change the chip settings, so...\r
1722          * if chip_info exists, use it\r
1723          */\r
1724         chip_info = spi->controller_data;\r
1725 \r
1726         /* chip_info doesn't always exist */\r
1727         if (chip_info) {\r
1728                 if (chip_info->cs_control)\r
1729                         chip->cs_control = chip_info->cs_control;\r
1730 \r
1731                 chip->poll_mode = chip_info->poll_mode;\r
1732                 chip->type = chip_info->type;\r
1733 \r
1734                 chip->rx_threshold = 0;\r
1735                 chip->tx_threshold = 0;\r
1736 \r
1737                 chip->enable_dma = chip_info->enable_dma;\r
1738         }\r
1739 \r
1740         if (spi->bits_per_word == 8) {\r
1741                 chip->n_bytes = 1;\r
1742                 chip->dma_width = 1;\r
1743                 chip->read = u8_reader;\r
1744                 chip->write = u8_writer;\r
1745                 spi_dfs = SPI_DFS_8BIT;\r
1746         } else if (spi->bits_per_word == 16) {\r
1747                 chip->n_bytes = 2;\r
1748                 chip->dma_width = 2;\r
1749                 chip->read = u16_reader;\r
1750                 chip->write = u16_writer;\r
1751                 spi_dfs = SPI_DFS_16BIT;\r
1752         } else {\r
1753                 /* Never take >16b case for MRST SPIC */\r
1754                 dev_err(&spi->dev, "invalid wordsize\n");\r
1755                 return -EINVAL;\r
1756         }\r
1757         chip->bits_per_word = spi->bits_per_word;\r
1758 \r
1759         if (!spi->max_speed_hz) {\r
1760                 dev_err(&spi->dev, "No max speed HZ parameter\n");\r
1761                 return -EINVAL;\r
1762         }\r
1763         chip->speed_hz = spi->max_speed_hz;\r
1764 \r
1765         chip->tmode = 0; /* Tx & Rx */\r
1766         /* Default SPI mode is SCPOL = 0, SCPH = 0 */\r
1767         chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1768                 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1769                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1770                         | (chip->type << SPI_FRF_OFFSET)\r
1771                         | (spi->mode  << SPI_MODE_OFFSET)\r
1772                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1773 \r
1774         spi_set_ctldata(spi, chip);\r
1775         return 0;\r
1776 }\r
1777 \r
1778 static void rk29xx_spi_cleanup(struct spi_device *spi)\r
1779 {\r
1780         struct chip_data *chip = spi_get_ctldata(spi);\r
1781         kfree(chip);\r
1782 }\r
1783 \r
1784 static int __devinit init_queue(struct rk29xx_spi *dws)\r
1785 {\r
1786         INIT_LIST_HEAD(&dws->queue);\r
1787         spin_lock_init(&dws->lock);\r
1788 \r
1789         dws->run = QUEUE_STOPPED;\r
1790         dws->busy = 0;\r
1791 \r
1792         init_completion(&dws->xfer_completion);\r
1793 \r
1794         tasklet_init(&dws->pump_transfers,\r
1795                         pump_transfers, (unsigned long)dws);\r
1796 \r
1797         INIT_WORK(&dws->pump_messages, pump_messages);\r
1798         dws->workqueue = create_singlethread_workqueue(\r
1799                                         dev_name(dws->master->dev.parent));\r
1800         if (dws->workqueue == NULL)\r
1801                 return -EBUSY;\r
1802 \r
1803 \r
1804         return 0;\r
1805 }\r
1806 \r
1807 static int start_queue(struct rk29xx_spi *dws)\r
1808 {\r
1809         unsigned long flags;\r
1810 \r
1811         spin_lock_irqsave(&dws->lock, flags);\r
1812 \r
1813         if (dws->run == QUEUE_RUNNING || dws->busy) {\r
1814                 spin_unlock_irqrestore(&dws->lock, flags);\r
1815                 return -EBUSY;\r
1816         }\r
1817 \r
1818         dws->run = QUEUE_RUNNING;\r
1819         dws->cur_msg = NULL;\r
1820         dws->cur_transfer = NULL;\r
1821         dws->cur_chip = NULL;\r
1822         dws->prev_chip = NULL;\r
1823         spin_unlock_irqrestore(&dws->lock, flags);\r
1824 \r
1825         queue_work(dws->workqueue, &dws->pump_messages);\r
1826 \r
1827         return 0;\r
1828 }\r
1829 \r
1830 static int stop_queue(struct rk29xx_spi *dws)\r
1831 {\r
1832         unsigned long flags;\r
1833         unsigned limit = 50;\r
1834         int status = 0;\r
1835 \r
1836         spin_lock_irqsave(&dws->lock, flags);\r
1837         dws->run = QUEUE_STOPPED;\r
1838         while (!list_empty(&dws->queue) && dws->busy && limit--) {\r
1839                 spin_unlock_irqrestore(&dws->lock, flags);\r
1840                 msleep(10);\r
1841                 spin_lock_irqsave(&dws->lock, flags);\r
1842         }\r
1843 \r
1844         if (!list_empty(&dws->queue) || dws->busy)\r
1845                 status = -EBUSY;\r
1846         spin_unlock_irqrestore(&dws->lock, flags);\r
1847 \r
1848         return status;\r
1849 }\r
1850 \r
1851 static int destroy_queue(struct rk29xx_spi *dws)\r
1852 {\r
1853         int status;\r
1854 \r
1855         status = stop_queue(dws);\r
1856         if (status != 0)\r
1857                 return status;\r
1858         destroy_workqueue(dws->workqueue);\r
1859         return 0;\r
1860 }\r
1861 \r
1862 /* Restart the controller, disable all interrupts, clean rx fifo */\r
1863 static void spi_hw_init(struct rk29xx_spi *dws)\r
1864 {\r
1865         spi_enable_chip(dws, 0);\r
1866         spi_mask_intr(dws, 0xff);\r
1867         \r
1868         /*\r
1869          * Try to detect the FIFO depth if not set by interface driver,\r
1870          * the depth could be from 2 to 32 from HW spec\r
1871          */\r
1872         if (!dws->fifo_len) {\r
1873                 u32 fifo;\r
1874                 for (fifo = 2; fifo <= 31; fifo++) {\r
1875                         rk29xx_writew(dws, SPIM_TXFTLR, fifo);\r
1876                         if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))\r
1877                                 break;\r
1878                 }\r
1879 \r
1880                 dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
1881                 rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
1882         }\r
1883         \r
1884         spi_enable_chip(dws, 1);\r
1885         //flush(dws);\r
1886 }\r
1887 \r
1888 /* cpufreq driver support */\r
1889 #ifdef CONFIG_CPU_FREQ\r
1890 \r
1891 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)\r
1892 {\r
1893         struct rk29xx_spi *info;\r
1894         unsigned long newclk;\r
1895 \r
1896         info = container_of(nb, struct rk29xx_spi, freq_transition);\r
1897         newclk = clk_get_rate(info->clock_spim);\r
1898 \r
1899         return 0;\r
1900 }\r
1901 \r
1902 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1903 {\r
1904         info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;\r
1905 \r
1906         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1907 }\r
1908 \r
1909 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1910 {\r
1911         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1912 }\r
1913 \r
1914 #else\r
1915 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1916 {\r
1917         return 0;\r
1918 }\r
1919 \r
1920 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1921 {\r
1922 }\r
1923 #endif\r
1924 static int __init rk29xx_spim_probe(struct platform_device *pdev)\r
1925 {\r
1926         struct resource         *regs, *dmatx_res, *dmarx_res;\r
1927         struct rk29xx_spi   *dws;\r
1928         struct spi_master   *master;\r
1929         int                     irq; \r
1930         int ret;\r
1931         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
1932 \r
1933         if (pdata && pdata->io_init) {\r
1934                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
1935                 if (ret) {                      \r
1936                         return -ENXIO;  \r
1937                 }\r
1938         }\r
1939         \r
1940         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1941         if (!regs)\r
1942                 return -ENXIO;\r
1943         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);\r
1944         if (dmatx_res == NULL) {\r
1945                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");\r
1946                 return -ENXIO;\r
1947         }\r
1948 \r
1949         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);\r
1950         if (dmarx_res == NULL) {\r
1951                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");\r
1952                 return -ENXIO;\r
1953         }\r
1954         irq = platform_get_irq(pdev, 0);\r
1955         if (irq < 0)\r
1956                 return irq;                     \r
1957         /* setup spi core then atmel-specific driver state */\r
1958         ret = -ENOMEM;  \r
1959         master = spi_alloc_master(&pdev->dev, sizeof *dws);\r
1960         if (!master) {\r
1961                 ret = -ENOMEM;\r
1962                 goto exit;\r
1963         }\r
1964 \r
1965         platform_set_drvdata(pdev, master);\r
1966         dws = spi_master_get_devdata(master);\r
1967         dws->clock_spim = clk_get(&pdev->dev, "spi");\r
1968         clk_enable(dws->clock_spim);\r
1969         if (IS_ERR(dws->clock_spim)) {\r
1970                 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
1971                 return PTR_ERR(dws->clock_spim);\r
1972         }\r
1973 \r
1974         dws->pclk = clk_get(&pdev->dev, "pclk_spi");\r
1975         clk_enable(dws->pclk);\r
1976         \r
1977         mutex_init(&dws->dma_lock);\r
1978         \r
1979         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);\r
1980         if (!dws->regs){\r
1981         release_mem_region(regs->start, (regs->end - regs->start) + 1);\r
1982                 return -EBUSY;\r
1983         }\r
1984         DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
1985         dws->irq = irq;\r
1986         dws->irq_polarity = IRQF_TRIGGER_NONE;\r
1987         dws->master = master;\r
1988         dws->type = SSI_MOTO_SPI;\r
1989         dws->prev_chip = NULL;\r
1990         dws->sfr_start = regs->start;\r
1991         dws->tx_dmach = dmatx_res->start;\r
1992         dws->rx_dmach = dmarx_res->start;\r
1993         dws->dma_inited = 0;  ///0;\r
1994         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);\r
1995         ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,\r
1996                         "rk29xx_spim", dws);\r
1997         if (ret < 0) {\r
1998                 dev_err(&master->dev, "can not get IRQ\n");\r
1999                 goto err_free_master;\r
2000         }\r
2001 \r
2002         master->mode_bits = SPI_CPOL | SPI_CPHA;\r
2003         master->bus_num = pdev->id;\r
2004         master->num_chipselect = pdata->num_chipselect;\r
2005         master->dev.platform_data = pdata;\r
2006         master->cleanup = rk29xx_spi_cleanup;\r
2007         master->setup = rk29xx_spi_setup;\r
2008         #if defined(QUICK_TRANSFER)\r
2009         master->transfer = rk29xx_spi_quick_transfer;\r
2010         #else\r
2011         master->transfer = rk29xx_spi_transfer;\r
2012         #endif\r
2013         \r
2014         dws->pdev = pdev;\r
2015         /* Basic HW init */\r
2016         spi_hw_init(dws);\r
2017         flush(dws);\r
2018         /* Initial and start queue */\r
2019         ret = init_queue(dws);\r
2020         if (ret) {\r
2021                 dev_err(&master->dev, "problem initializing queue\n");\r
2022                 goto err_diable_hw;\r
2023         }\r
2024 \r
2025         ret = start_queue(dws);\r
2026         if (ret) {\r
2027                 dev_err(&master->dev, "problem starting queue\n");\r
2028                 goto err_diable_hw;\r
2029         }\r
2030 \r
2031         spi_master_set_devdata(master, dws);\r
2032         ret = spi_register_master(master);\r
2033         if (ret) {\r
2034                 dev_err(&master->dev, "problem registering spi master\n");\r
2035                 goto err_queue_alloc;\r
2036         }\r
2037 \r
2038     ret =rk29xx_spim_cpufreq_register(dws);\r
2039     if (ret < 0) {\r
2040         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
2041         goto err_queue_alloc;\r
2042     }\r
2043         printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);\r
2044         mrst_spi_debugfs_init(dws);\r
2045         return 0;\r
2046 \r
2047 err_queue_alloc:\r
2048         destroy_queue(dws);\r
2049 err_diable_hw:\r
2050         spi_enable_chip(dws, 0);\r
2051         free_irq(dws->irq, dws);\r
2052 err_free_master:\r
2053         spi_master_put(master);\r
2054         iounmap(dws->regs);\r
2055 exit:\r
2056         return ret;\r
2057 }\r
2058 \r
2059 static void __exit rk29xx_spim_remove(struct platform_device *pdev)\r
2060 {\r
2061         struct spi_master *master = platform_get_drvdata(pdev);\r
2062         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2063         int status = 0;\r
2064 \r
2065         if (!dws)\r
2066                 return;\r
2067         rk29xx_spim_cpufreq_deregister(dws);\r
2068         mrst_spi_debugfs_remove(dws);\r
2069 \r
2070         if(dws->buffer_tx_dma)\r
2071         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);\r
2072         if(dws->buffer_rx_dma)\r
2073         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);\r
2074         release_dma(dws);\r
2075 \r
2076         /* Remove the queue */\r
2077         status = destroy_queue(dws);\r
2078         if (status != 0)\r
2079                 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "\r
2080                         "complete, message memory not freed\n");\r
2081         \r
2082         clk_disable(dws->clock_spim);\r
2083         clk_put(dws->clock_spim);\r
2084         clk_disable(dws->pclk);\r
2085         clk_put(dws->pclk);\r
2086         spi_enable_chip(dws, 0);\r
2087         /* Disable clk */\r
2088         spi_set_clk(dws, 0);\r
2089         free_irq(dws->irq, dws);\r
2090 \r
2091         /* Disconnect from the SPI framework */\r
2092         spi_unregister_master(dws->master);\r
2093         iounmap(dws->regs);\r
2094 }\r
2095 \r
2096 \r
2097 #ifdef  CONFIG_PM\r
2098 \r
2099 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)\r
2100 {\r
2101         struct spi_master *master = platform_get_drvdata(pdev);\r
2102         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2103         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2104         int status;\r
2105         \r
2106         flush(dws);\r
2107         status = stop_queue(dws);\r
2108         if (status != 0)\r
2109                 return status;\r
2110         clk_disable(dws->clock_spim);\r
2111         if (pdata && pdata->io_fix_leakage_bug)\r
2112         {\r
2113                 pdata->io_fix_leakage_bug( );\r
2114         }\r
2115         clk_disable(dws->pclk);\r
2116         return 0;\r
2117 }\r
2118 \r
2119 static int rk29xx_spim_resume(struct platform_device *pdev)\r
2120 {\r
2121         struct spi_master *master = platform_get_drvdata(pdev);\r
2122         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2123         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2124         int ret;\r
2125 \r
2126         clk_enable(dws->pclk);\r
2127         clk_enable(dws->clock_spim);    \r
2128         spi_hw_init(dws);\r
2129         ret = start_queue(dws);\r
2130         if (ret)\r
2131                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);\r
2132         if (pdata && pdata->io_resume_leakage_bug)\r
2133         {\r
2134                 pdata->io_resume_leakage_bug( ); \r
2135         }\r
2136         return ret;\r
2137 }\r
2138 \r
2139 #else\r
2140 #define rk29xx_spim_suspend     NULL\r
2141 #define rk29xx_spim_resume      NULL\r
2142 #endif\r
2143 \r
2144 static struct platform_driver rk29xx_platform_spim_driver = {\r
2145         .remove         = __exit_p(rk29xx_spim_remove),\r
2146         .driver         = {\r
2147                 .name   = "rk29xx_spim",\r
2148                 .owner  = THIS_MODULE,\r
2149         },\r
2150         .suspend        = rk29xx_spim_suspend,\r
2151         .resume         = rk29xx_spim_resume,\r
2152 };\r
2153 \r
2154 static int __init rk29xx_spim_init(void)\r
2155 {\r
2156         int ret;\r
2157         ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);   \r
2158         return ret;\r
2159 }\r
2160 \r
2161 static void __exit rk29xx_spim_exit(void)\r
2162 {\r
2163         platform_driver_unregister(&rk29xx_platform_spim_driver);\r
2164 }\r
2165 \r
2166 arch_initcall_sync(rk29xx_spim_init);\r
2167 module_exit(rk29xx_spim_exit);\r
2168 \r
2169 MODULE_AUTHOR("www.rock-chips.com");\r
2170 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");\r
2171 MODULE_LICENSE("GPL");;\r
2172 \r