drivers/spi/rk29_spim.c

   1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device \r
   2  *\r
   3  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   4  *\r
   5  * This software is licensed under the terms of the GNU General Public\r
   6  * License version 2, as published by the Free Software Foundation, and\r
   7  * may be copied, distributed, and modified under those terms.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful,\r
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  12  * GNU General Public License for more details.\r
  13  */\r
  14 \r
  15 #include <linux/dma-mapping.h>\r
  16 #include <linux/interrupt.h>\r
  17 #include <linux/highmem.h>\r
  18 #include <linux/delay.h>\r
  19 #include <linux/slab.h>\r
  20 #include <linux/platform_device.h>\r
  21 #include <linux/clk.h>\r
  22 #include <linux/cpufreq.h>\r
  23 #include <mach/gpio.h>\r
  24 #include <mach/irqs.h>\r
  25 #include <linux/dma-mapping.h>\r
  26 #include <asm/dma.h>\r
  27 #include <linux/preempt.h>\r
  28 #include "rk29_spim.h"\r
  29 #include <linux/spi/spi.h>\r
  30 #include <mach/board.h>\r
  31 \r
  32 #ifdef CONFIG_DEBUG_FS\r
  33 #include <linux/debugfs.h>\r
  34 #endif\r
  35 \r
  36 /*ÔÓÐµÄspiÇý¶¯Ð§ÂÊ±È½ÏµÍ£¬\r
  37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Êä£»\r
  38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Êä£¬Í¬Ê±¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬\r
  39 Ä¬ÈÏÊ¹ÓÃ°ëË«¹¤\r
  40 */\r
  41 \r
  42 //#define QUICK_TRANSFER         \r
  43 #if 0\r
  44 #define DBG   printk\r
  45 //#define PRINT_TRANS_DATA\r
  46 #else\r
  47 #define DBG(x...)\r
  48 #endif\r
  49 \r
  50 #define DMA_BUFFER_SIZE PAGE_SIZE\r
  51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO\r
  52 \r
  53 \r
  54 #define START_STATE     ((void *)0)\r
  55 #define RUNNING_STATE   ((void *)1)\r
  56 #define DONE_STATE      ((void *)2)\r
  57 #define ERROR_STATE     ((void *)-1)\r
  58 \r
  59 #define QUEUE_RUNNING   0\r
  60 #define QUEUE_STOPPED   1\r
  61 \r
  62 #define MRST_SPI_DEASSERT       0\r
  63 #define MRST_SPI_ASSERT         1  ///CS0\r
  64 #define MRST_SPI_ASSERT1        2  ///CS1\r
  65 \r
  66 /* Slave spi_dev related */\r
  67 struct chip_data {\r
  68         u16 cr0;\r
  69         u8 cs;                  /* chip select pin */\r
  70         u8 n_bytes;             /* current is a 1/2/4 byte op */\r
  71         u8 tmode;               /* TR/TO/RO/EEPROM */\r
  72         u8 type;                /* SPI/SSP/MicroWire */\r
  73 \r
  74         u8 poll_mode;           /* 1 means use poll mode */\r
  75 \r
  76         u32 dma_width;\r
  77         u32 rx_threshold;\r
  78         u32 tx_threshold;\r
  79         u8 enable_dma:1;\r
  80         u8 bits_per_word;\r
  81         u16 clk_div;            /* baud rate divider */\r
  82         u32 speed_hz;           /* baud rate */\r
  83         int (*write)(struct rk29xx_spi *dws);\r
  84         int (*read)(struct rk29xx_spi *dws);\r
  85         void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);\r
  86 };\r
  87 \r
  88 #define SUSPND    (1<<0)\r
  89 #define SPIBUSY   (1<<1)\r
  90 #define RXBUSY    (1<<2)\r
  91 #define TXBUSY    (1<<3)\r
  92 \r
  93 //\r
  94 #ifdef CONFIG_LCD_USE_SPIM_CONTROL\r
  95 void rk29_lcd_spim_spin_lock(void)\r
  96 {\r
  97 #ifdef CONFIG_LCD_USE_SPI0\r
  98         disable_irq(IRQ_SPI0);\r
  99 #endif\r
 100 \r
 101 #ifdef CONFIG_LCD_USE_SPI1\r
 102         disable_irq(IRQ_SPI1);\r
 103 #endif\r
 104 \r
 105         preempt_disable();\r
 106 }\r
 107 \r
 108 void rk29_lcd_spim_spin_unlock(void)\r
 109 {\r
 110         preempt_enable();\r
 111         \r
 112 #ifdef CONFIG_LCD_USE_SPI0\r
 113         enable_irq(IRQ_SPI0);\r
 114 #endif\r
 115 \r
 116 #ifdef CONFIG_LCD_USE_SPI1\r
 117         enable_irq(IRQ_SPI1);\r
 118 #endif\r
 119 }\r
 120 #else\r
 121 void rk29_lcd_spim_spin_lock(void)\r
 122 {\r
 123      return;\r
 124 }\r
 125 \r
 126 void rk29_lcd_spim_spin_unlock(void)\r
 127 {\r
 128      return;\r
 129 }\r
 130 #endif\r
 131 \r
 132 #if defined(PRINT_TRANS_DATA)\r
 133 static void printk_transfer_data(unsigned char *buf, int len)\r
 134 {\r
 135         int i = 0;\r
 136         for(i=0; i<len; i++)\r
 137                 printk("0x%x,",*buf++);\r
 138 \r
 139         printk("\n");\r
 140 \r
 141 }\r
 142 #endif\r
 143 \r
 144 static void spi_dump_regs(struct rk29xx_spi *dws) {\r
 145         DBG("MRST SPI0 registers:\n");\r
 146         DBG("=================================\n");\r
 147         DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 148         DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 149         DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 150         DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 151         DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 152         DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 153         DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 154         DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 155         DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 156         DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 157         DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 158         DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 159         DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 160         DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 161         DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 162         DBG("=================================\n");\r
 163 \r
 164 }\r
 165 \r
 166 #ifdef CONFIG_DEBUG_FS\r
 167 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 168 {\r
 169         file->private_data = inode->i_private;\r
 170         return 0;\r
 171 }\r
 172 \r
 173 #define SPI_REGS_BUFSIZE        1024\r
 174 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,\r
 175                                 size_t count, loff_t *ppos)\r
 176 {\r
 177         struct rk29xx_spi *dws;\r
 178         char *buf;\r
 179         u32 len = 0;\r
 180         ssize_t ret;\r
 181 \r
 182         dws = file->private_data;\r
 183 \r
 184         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);\r
 185         if (!buf)\r
 186                 return 0;\r
 187 \r
 188         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 189                         "MRST SPI0 registers:\n");\r
 190         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 191                         "=================================\n");\r
 192         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 193                         "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 194         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 195                         "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 196         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 197                         "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 198         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 199                         "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 200         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 201                         "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 202         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 203                         "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 204         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 205                         "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 206         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 207                         "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 208         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 209                         "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 210         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 211                         "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 212         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 213                         "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 214         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 215                         "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 216         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 217                         "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 218         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 219                         "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 220         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 221                         "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 222         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 223                         "=================================\n");\r
 224 \r
 225         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);\r
 226         kfree(buf);\r
 227         return ret;\r
 228 }\r
 229 \r
 230 static const struct file_operations mrst_spi_regs_ops = {\r
 231         .owner          = THIS_MODULE,\r
 232         .open           = spi_show_regs_open,\r
 233         .read           = spi_show_regs,\r
 234 };\r
 235 \r
 236 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 237 {\r
 238         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);\r
 239         if (!dws->debugfs)\r
 240                 return -ENOMEM;\r
 241 \r
 242         debugfs_create_file("registers", S_IFREG | S_IRUGO,\r
 243                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);\r
 244         return 0;\r
 245 }\r
 246 \r
 247 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 248 {\r
 249         if (dws->debugfs)\r
 250                 debugfs_remove_recursive(dws->debugfs);\r
 251 }\r
 252 \r
 253 #else\r
 254 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 255 {\r
 256         return 0;\r
 257 }\r
 258 \r
 259 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 260 {\r
 261 }\r
 262 #endif /* CONFIG_DEBUG_FS */\r
 263 \r
 264 static void dma_transfer(struct rk29xx_spi *dws) ;\r
 265 static void transfer_complete(struct rk29xx_spi *dws);\r
 266 \r
 267 static void wait_till_not_busy(struct rk29xx_spi *dws)\r
 268 {\r
 269         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 270 \r
 271         while (time_before(jiffies, end)) {\r
 272                 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
 273                         return;\r
 274         }\r
 275         dev_err(&dws->master->dev,\r
 276                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 277 }\r
 278 \r
 279 #if defined(QUICK_TRANSFER)\r
 280 static void wait_till_tf_empty(struct rk29xx_spi *dws)\r
 281 {\r
 282         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 283 \r
 284         while (time_before(jiffies, end)) {\r
 285                 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)\r
 286                         return;\r
 287         }\r
 288         dev_err(&dws->master->dev,\r
 289                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 290 }\r
 291 #endif\r
 292 \r
 293 static void flush(struct rk29xx_spi *dws)\r
 294 {\r
 295         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 296                 rk29xx_readw(dws, SPIM_RXDR);\r
 297 \r
 298         wait_till_not_busy(dws);\r
 299 }\r
 300 \r
 301 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 302 {\r
 303         #if 1\r
 304         if (flag)\r
 305                 rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 306         else            \r
 307                 rk29xx_writel(dws, SPIM_SER, 0);\r
 308         return;\r
 309         #else\r
 310         struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
 311         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 312 \r
 313         if (flag == 0) {\r
 314                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
 315         }\r
 316         else {\r
 317                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
 318         }\r
 319         #endif\r
 320 }\r
 321 \r
 322 static int null_writer(struct rk29xx_spi *dws)\r
 323 {\r
 324         u8 n_bytes = dws->n_bytes;\r
 325 \r
 326         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 327                 || (dws->tx == dws->tx_end))\r
 328                 return 0;\r
 329         rk29xx_writew(dws, SPIM_TXDR, 0);\r
 330         dws->tx += n_bytes;\r
 331         //wait_till_not_busy(dws);\r
 332 \r
 333         return 1;\r
 334 }\r
 335 \r
 336 static int null_reader(struct rk29xx_spi *dws)\r
 337 {\r
 338         u8 n_bytes = dws->n_bytes;\r
 339         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 340         while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 341                 && (dws->rx < dws->rx_end)) {\r
 342                 rk29xx_readw(dws, SPIM_RXDR);\r
 343                 dws->rx += n_bytes;\r
 344         }\r
 345         wait_till_not_busy(dws);\r
 346         return dws->rx == dws->rx_end;\r
 347 }\r
 348 \r
 349 static int u8_writer(struct rk29xx_spi *dws)\r
 350 {       \r
 351         //spi_dump_regs(dws)\r
 352 #if defined(PRINT_TRANS_DATA)\r
 353         DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
 354 #endif\r
 355         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 356                 || (dws->tx == dws->tx_end))\r
 357                 return 0;\r
 358         rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));\r
 359         ++dws->tx;\r
 360         //wait_till_not_busy(dws);\r
 361 \r
 362         return 1;\r
 363 }\r
 364 \r
 365 static int u8_reader(struct rk29xx_spi *dws)\r
 366 {\r
 367     //spi_dump_regs(dws);\r
 368         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 369                 && (dws->rx < dws->rx_end)) {\r
 370                 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;\r
 371 #if defined(PRINT_TRANS_DATA)\r
 372                 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));\r
 373 #endif\r
 374                 ++dws->rx;\r
 375         }\r
 376 \r
 377         wait_till_not_busy(dws);\r
 378         return dws->rx == dws->rx_end;\r
 379 }\r
 380 \r
 381 static int u16_writer(struct rk29xx_spi *dws)\r
 382 {       \r
 383 #if defined(PRINT_TRANS_DATA)\r
 384         DBG("tx: 0x%04x\n", *(u16 *)(dws->tx));\r
 385 #endif\r
 386         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 387                 || (dws->tx == dws->tx_end))\r
 388                 return 0;\r
 389 \r
 390         rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));\r
 391         dws->tx += 2;\r
 392         //wait_till_not_busy(dws);\r
 393 \r
 394         return 1;\r
 395 }\r
 396 \r
 397 static int u16_reader(struct rk29xx_spi *dws)\r
 398 {\r
 399         u16 temp;\r
 400 \r
 401         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 402                 && (dws->rx < dws->rx_end)) {\r
 403                 temp = rk29xx_readw(dws, SPIM_RXDR);\r
 404                 *(u16 *)(dws->rx) = temp;\r
 405 #if defined(PRINT_TRANS_DATA)\r
 406                 DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));\r
 407 #endif\r
 408                 dws->rx += 2;\r
 409         }\r
 410 \r
 411         wait_till_not_busy(dws);\r
 412         return dws->rx == dws->rx_end;\r
 413 }\r
 414 \r
 415 static void *next_transfer(struct rk29xx_spi *dws)\r
 416 {\r
 417         struct spi_message *msg = dws->cur_msg;\r
 418         struct spi_transfer *trans = dws->cur_transfer;\r
 419 \r
 420         /* Move to next transfer */\r
 421         if (trans->transfer_list.next != &msg->transfers) {\r
 422                 dws->cur_transfer =\r
 423                         list_entry(trans->transfer_list.next,\r
 424                                         struct spi_transfer,\r
 425                                         transfer_list);\r
 426                 return RUNNING_STATE;\r
 427         } else\r
 428                 return DONE_STATE;\r
 429 }\r
 430 \r
 431 static void rk29_spi_dma_rxcb(void *buf_id,\r
 432                                  int size, enum rk29_dma_buffresult res)\r
 433 {\r
 434         struct rk29xx_spi *dws = buf_id;\r
 435         unsigned long flags;\r
 436 \r
 437         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 438         \r
 439         spin_lock_irqsave(&dws->lock, flags);\r
 440 \r
 441         if (res == RK29_RES_OK)\r
 442                 dws->state &= ~RXBUSY;\r
 443         else\r
 444                 dev_err(&dws->master->dev, "error:DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);\r
 445 \r
 446         //copy data from dma to transfer buf\r
 447         if(dws->cur_transfer && (dws->cur_transfer->rx_buf != NULL))\r
 448         {\r
 449                 memcpy(dws->cur_transfer->rx_buf, dws->buffer_rx_dma, dws->cur_transfer->len);\r
 450                 \r
 451                 #if defined(PRINT_TRANS_DATA)\r
 452                 printk("dma rx:");\r
 453                 printk_transfer_data(dws->cur_transfer->rx_buf, dws->cur_transfer->len);\r
 454                 #endif\r
 455         }\r
 456         \r
 457         spin_unlock_irqrestore(&dws->lock, flags);\r
 458         \r
 459         /* If the other done */\r
 460         if (!(dws->state & TXBUSY))\r
 461         {\r
 462                 //complete(&dws->xfer_completion);      \r
 463                 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);\r
 464                 //DMA could not lose intterupt\r
 465                 transfer_complete(dws);\r
 466         }\r
 467 \r
 468 }\r
 469 \r
 470 static void rk29_spi_dma_txcb(void *buf_id,\r
 471                                  int size, enum rk29_dma_buffresult res)\r
 472 {\r
 473         struct rk29xx_spi *dws = buf_id;\r
 474         unsigned long flags;\r
 475 \r
 476         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 477         \r
 478         spin_lock_irqsave(&dws->lock, flags);\r
 479 \r
 480         if (res == RK29_RES_OK)\r
 481                 dws->state &= ~TXBUSY;\r
 482         else\r
 483                 dev_err(&dws->master->dev, "error:DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);\r
 484 \r
 485         spin_unlock_irqrestore(&dws->lock, flags);\r
 486         \r
 487         /* If the other done */\r
 488         if (!(dws->state & RXBUSY)) \r
 489         {\r
 490                 //complete(&dws->xfer_completion);\r
 491                 \r
 492                 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);\r
 493                 //DMA could not lose intterupt\r
 494                 transfer_complete(dws);\r
 495         }\r
 496 \r
 497 }\r
 498 \r
 499 \r
 500 static struct rk29_dma_client rk29_spi_dma_client = {\r
 501         .name = "rk29xx-spi-dma",\r
 502 };\r
 503 \r
 504 static int acquire_dma(struct rk29xx_spi *dws)\r
 505 {       \r
 506         if (dws->dma_inited) {\r
 507                 return 0;\r
 508         }\r
 509 \r
 510         dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);\r
 511         if (!dws->buffer_tx_dma)\r
 512         {\r
 513                 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");\r
 514                 return -1;\r
 515         }\r
 516 \r
 517         dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);\r
 518         if (!dws->buffer_rx_dma)\r
 519         {\r
 520                 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");\r
 521                 return -1;\r
 522         }\r
 523 \r
 524         if(rk29_dma_request(dws->rx_dmach, \r
 525                 &rk29_spi_dma_client, NULL) < 0) {\r
 526                 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);\r
 527                 return -1;\r
 528         }\r
 529 \r
 530         if (rk29_dma_request(dws->tx_dmach,\r
 531                                         &rk29_spi_dma_client, NULL) < 0) {\r
 532                 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);\r
 533                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 534                 return -1;\r
 535         }\r
 536 \r
 537         if (dws->tx_dma) {\r
 538                 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {\r
 539                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 540                         return -1;\r
 541                 }\r
 542                 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
 543                                         dws->sfr_start + SPIM_TXDR)) {\r
 544                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 545                         return -1;\r
 546                 }\r
 547         }\r
 548 \r
 549         if (dws->rx_dma) {\r
 550                 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {\r
 551                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 552                         return -1;\r
 553                 }\r
 554                 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
 555                                         dws->sfr_start + SPIM_RXDR)) {\r
 556                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 557                         return -1;\r
 558                 }\r
 559         }\r
 560         \r
 561         dws->dma_inited = 1;\r
 562         return 0;\r
 563 }\r
 564 \r
 565 static void release_dma(struct rk29xx_spi *dws)\r
 566 {\r
 567         if(!dws && dws->dma_inited) {\r
 568                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 569                 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);\r
 570         }\r
 571 }\r
 572 \r
 573 /*\r
 574  * Note: first step is the protocol driver prepares\r
 575  * a dma-capable memory, and this func just need translate\r
 576  * the virt addr to physical\r
 577  */\r
 578 static int map_dma_buffers(struct rk29xx_spi *dws)\r
 579 {\r
 580         if (!dws->dma_inited || !dws->cur_chip->enable_dma)\r
 581         {\r
 582                 printk("%s:error\n",__func__);\r
 583                 return -1;\r
 584         }\r
 585 \r
 586         if(dws->cur_transfer->tx_buf)\r
 587         {\r
 588                 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);\r
 589         }\r
 590         \r
 591         dws->cur_transfer->tx_dma = dws->tx_dma;\r
 592         dws->cur_transfer->rx_dma = dws->rx_dma;\r
 593         \r
 594         return 0;\r
 595 }\r
 596 \r
 597 /* Caller already set message->status; dma and pio irqs are blocked */\r
 598 static void giveback(struct rk29xx_spi *dws)\r
 599 {\r
 600         struct spi_transfer *last_transfer;\r
 601         unsigned long flags;\r
 602         struct spi_message *msg;\r
 603 \r
 604         spin_lock_irqsave(&dws->lock, flags);\r
 605         msg = dws->cur_msg;\r
 606         dws->cur_msg = NULL;\r
 607         dws->cur_transfer = NULL;\r
 608         dws->prev_chip = dws->cur_chip;\r
 609         dws->cur_chip = NULL;\r
 610         dws->dma_mapped = 0;\r
 611         \r
 612         /*it is important to close intterrupt*/\r
 613         spi_mask_intr(dws, 0xff);\r
 614         rk29xx_writew(dws, SPIM_DMACR, 0);\r
 615         \r
 616         queue_work(dws->workqueue, &dws->pump_messages);\r
 617         spin_unlock_irqrestore(&dws->lock, flags);\r
 618 \r
 619         last_transfer = list_entry(msg->transfers.prev,\r
 620                                         struct spi_transfer,\r
 621                                         transfer_list);\r
 622 \r
 623         if (!last_transfer->cs_change && dws->cs_control)\r
 624                 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 625 \r
 626         msg->state = NULL;\r
 627         if (msg->complete)\r
 628                 msg->complete(msg->context);\r
 629 \r
 630         DBG("%s ok\n",__func__);\r
 631 \r
 632 }\r
 633 \r
 634 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)\r
 635 {\r
 636         /* Stop and reset hw */\r
 637         flush(dws);\r
 638         spi_enable_chip(dws, 0);\r
 639 \r
 640         dev_err(&dws->master->dev, "%s\n", msg);\r
 641         dws->cur_msg->state = ERROR_STATE;\r
 642         tasklet_schedule(&dws->pump_transfers);\r
 643 }\r
 644 \r
 645 static void transfer_complete(struct rk29xx_spi *dws)\r
 646 {\r
 647         /* Update total byte transfered return count actual bytes read */\r
 648         dws->cur_msg->actual_length += dws->len;\r
 649 \r
 650         /* Move to next transfer */\r
 651         dws->cur_msg->state = next_transfer(dws);\r
 652 \r
 653         /* Handle end of message */\r
 654         if (dws->cur_msg->state == DONE_STATE) {\r
 655                 dws->cur_msg->status = 0;\r
 656                 giveback(dws);\r
 657         } else\r
 658                 tasklet_schedule(&dws->pump_transfers);\r
 659 }\r
 660 \r
 661 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 662 {\r
 663         u16 irq_status, irq_mask = 0x1f;\r
 664         u32 int_level = dws->fifo_len / 2;\r
 665         u32 left;\r
 666 \r
 667         irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;\r
 668         /* Error handling */\r
 669         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {\r
 670                 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);\r
 671                 int_error_stop(dws, "interrupt_transfer: fifo overrun");\r
 672                 mutex_unlock(&dws->dma_lock);   \r
 673                 return IRQ_HANDLED;\r
 674         }\r
 675 \r
 676         if (irq_status & SPI_INT_TXEI) {\r
 677                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 678 \r
 679                 left = (dws->tx_end - dws->tx) / dws->n_bytes;\r
 680                 left = (left > int_level) ? int_level : left;\r
 681 \r
 682                 while (left--) {\r
 683                         dws->write(dws);\r
 684                         wait_till_not_busy(dws);\r
 685                 }\r
 686                 if (dws->rx) {\r
 687                     dws->read(dws);\r
 688                 }\r
 689 \r
 690                 /* Re-enable the IRQ if there is still data left to tx */\r
 691                 if (dws->tx_end > dws->tx)\r
 692                         spi_umask_intr(dws, SPI_INT_TXEI);\r
 693                 else\r
 694                         transfer_complete(dws);\r
 695         }\r
 696 \r
 697         if (irq_status & SPI_INT_RXFI) {\r
 698                 spi_mask_intr(dws, SPI_INT_RXFI);\r
 699                 \r
 700                 dws->read(dws);\r
 701 \r
 702                 /* Re-enable the IRQ if there is still data left to rx */\r
 703                 if (dws->rx_end > dws->rx) {\r
 704                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;\r
 705                     left = (left > int_level) ? int_level : left;\r
 706 \r
 707                         rk29xx_writew(dws, SPIM_RXFTLR, left);\r
 708                         spi_umask_intr(dws, SPI_INT_RXFI);\r
 709                 }\r
 710                 else {\r
 711                         transfer_complete(dws);\r
 712                 }\r
 713                 \r
 714         }       \r
 715 \r
 716         return IRQ_HANDLED;\r
 717 }\r
 718 \r
 719 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)\r
 720 {\r
 721         struct rk29xx_spi *dws = dev_id;\r
 722 \r
 723         if (!dws->cur_msg) {\r
 724                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 725                 /* Never fail */\r
 726                 return IRQ_HANDLED;\r
 727         }\r
 728 \r
 729         return dws->transfer_handler(dws);\r
 730 }\r
 731 \r
 732 /* Must be called inside pump_transfers() */\r
 733 static void poll_transfer(struct rk29xx_spi *dws)\r
 734 {\r
 735 #if defined(PRINT_TRANS_DATA)\r
 736         DBG("%s\n",__func__);\r
 737 #endif\r
 738         while (dws->write(dws)) {\r
 739                 wait_till_not_busy(dws);\r
 740                 dws->read(dws);\r
 741         }\r
 742         transfer_complete(dws);\r
 743 }\r
 744 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)\r
 745 {\r
 746     if(cs >= dws->master->num_chipselect)\r
 747                 return;\r
 748 \r
 749         if (dws->cs_control){\r
 750             dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
 751         }\r
 752         rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 753 }\r
 754 \r
 755 static void pump_transfers(unsigned long data)\r
 756 {\r
 757         struct rk29xx_spi *dws = (struct rk29xx_spi *)data;\r
 758         struct spi_message *message = NULL;\r
 759         struct spi_transfer *transfer = NULL;\r
 760         struct spi_transfer *previous = NULL;\r
 761         struct spi_device *spi = NULL;\r
 762         struct chip_data *chip = NULL;\r
 763         u8 bits = 0;\r
 764         u8 spi_dfs = 0;\r
 765         u8 imask = 0;\r
 766         u8 cs_change = 0;\r
 767         u16 txint_level = 0;\r
 768         u16 rxint_level = 0;\r
 769         u16 clk_div = 0;\r
 770         u32 speed = 0;\r
 771         u32 cr0 = 0;\r
 772 \r
 773         if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){      \r
 774                 dma_transfer(dws);\r
 775                 return;\r
 776         }       \r
 777         \r
 778         DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);\r
 779 \r
 780         /* Get current state information */\r
 781         message = dws->cur_msg;\r
 782         transfer = dws->cur_transfer;\r
 783         chip = dws->cur_chip;\r
 784         spi = message->spi;     \r
 785         if (unlikely(!chip->clk_div))\r
 786                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 787         if (message->state == ERROR_STATE) {\r
 788                 message->status = -EIO;\r
 789                 goto early_exit;\r
 790         }\r
 791 \r
 792         /* Handle end of message */\r
 793         if (message->state == DONE_STATE) {\r
 794                 message->status = 0;\r
 795                 goto early_exit;\r
 796         }\r
 797 \r
 798         /* Delay if requested at end of transfer*/\r
 799         if (message->state == RUNNING_STATE) {\r
 800                 previous = list_entry(transfer->transfer_list.prev,\r
 801                                         struct spi_transfer,\r
 802                                         transfer_list);\r
 803                 if (previous->delay_usecs)\r
 804                         udelay(previous->delay_usecs);\r
 805         }\r
 806 \r
 807         dws->n_bytes = chip->n_bytes;\r
 808         dws->dma_width = chip->dma_width;\r
 809         dws->cs_control = chip->cs_control;\r
 810 \r
 811         //dws->rx_dma = transfer->rx_dma;\r
 812         //dws->tx_dma = transfer->tx_dma;\r
 813         dws->tx = (void *)transfer->tx_buf;\r
 814         dws->tx_end = dws->tx + transfer->len;\r
 815         dws->rx = (void *)transfer->rx_buf;\r
 816         dws->rx_end = dws->rx + transfer->len;\r
 817         dws->write = dws->tx ? chip->write : null_writer;\r
 818         dws->read = dws->rx ? chip->read : null_reader;\r
 819         dws->cs_change = transfer->cs_change;\r
 820         dws->len = dws->cur_transfer->len;\r
 821         if (chip != dws->prev_chip)\r
 822                 cs_change = 1;\r
 823 \r
 824         cr0 = chip->cr0;\r
 825 \r
 826         /* Handle per transfer options for bpw and speed */\r
 827         if (transfer->speed_hz) {\r
 828                 speed = chip->speed_hz;\r
 829 \r
 830                 if (transfer->speed_hz != speed) {\r
 831                         speed = transfer->speed_hz;\r
 832                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 833                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported "\r
 834                                         "freq: %dHz\n", speed);\r
 835                                 message->status = -EIO;\r
 836                                 goto early_exit;\r
 837                         }\r
 838 \r
 839                         /* clk_div doesn't support odd number */\r
 840                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 841                         clk_div = (clk_div + 1) & 0xfffe;\r
 842 \r
 843                         chip->speed_hz = speed;\r
 844                         chip->clk_div = clk_div;\r
 845                 }\r
 846         }\r
 847         \r
 848         if (transfer->bits_per_word) {\r
 849                 bits = transfer->bits_per_word;\r
 850 \r
 851                 switch (bits) {\r
 852                 case 8:\r
 853                         dws->n_bytes = 1;\r
 854                         dws->dma_width = 1;\r
 855                         dws->read = (dws->read != null_reader) ?\r
 856                                         u8_reader : null_reader;\r
 857                         dws->write = (dws->write != null_writer) ?\r
 858                                         u8_writer : null_writer;\r
 859                         spi_dfs = SPI_DFS_8BIT;\r
 860                         break;\r
 861                 case 16:\r
 862                         dws->n_bytes = 2;\r
 863                         dws->dma_width = 2;\r
 864                         dws->read = (dws->read != null_reader) ?\r
 865                                         u16_reader : null_reader;\r
 866                         dws->write = (dws->write != null_writer) ?\r
 867                                         u16_writer : null_writer;\r
 868                         spi_dfs = SPI_DFS_16BIT;\r
 869                         break;\r
 870                 default:\r
 871                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 872                                 "%db\n", bits);\r
 873                         message->status = -EIO;\r
 874                         goto early_exit;\r
 875                 }\r
 876 \r
 877                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 878                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 879                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 880                         | (chip->type << SPI_FRF_OFFSET)\r
 881                         | (spi->mode << SPI_MODE_OFFSET)\r
 882                         | (chip->tmode << SPI_TMOD_OFFSET);\r
 883         }\r
 884         message->state = RUNNING_STATE;\r
 885  \r
 886         /*\r
 887          * Adjust transfer mode if necessary. Requires platform dependent\r
 888          * chipselect mechanism.\r
 889          */\r
 890         if (dws->cs_control) {\r
 891                 if (dws->rx && dws->tx)\r
 892                         chip->tmode = SPI_TMOD_TR;\r
 893                 else if (dws->rx)\r
 894                         chip->tmode = SPI_TMOD_RO;\r
 895                 else\r
 896                         chip->tmode = SPI_TMOD_TO;\r
 897 \r
 898                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);               \r
 899                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
 900                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
 901         } \r
 902 \r
 903         /*\r
 904          * Interrupt mode\r
 905          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely\r
 906          */\r
 907         if (!dws->dma_mapped && !chip->poll_mode) {     \r
 908                 int templen ;\r
 909                 \r
 910                 if (chip->tmode == SPI_TMOD_RO) {\r
 911                         templen = dws->len / dws->n_bytes - 1;\r
 912                         rxint_level = dws->fifo_len / 2;\r
 913                         rxint_level = (templen > rxint_level) ? rxint_level : templen;\r
 914                         imask |= SPI_INT_RXFI;\r
 915                 }\r
 916                 else {  \r
 917                         templen = dws->len / dws->n_bytes;\r
 918                         txint_level = dws->fifo_len / 2;\r
 919                         txint_level = (templen > txint_level) ? txint_level : templen;\r
 920                         imask |= SPI_INT_TXEI;\r
 921                 }\r
 922                 dws->transfer_handler = interrupt_transfer;\r
 923         }\r
 924 \r
 925         /*\r
 926          * Reprogram registers only if\r
 927          *      1. chip select changes\r
 928          *      2. clk_div is changed\r
 929          *      3. control value changes\r
 930          */\r
 931         if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div || imask) {\r
 932                 spi_enable_chip(dws, 0);\r
 933                 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)\r
 934                         rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
 935 \r
 936                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
 937                 spi_chip_sel(dws, spi->chip_select);\r
 938 \r
 939         rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
 940                 spi_enable_chip(dws, 1);\r
 941 \r
 942                 if (txint_level)\r
 943                         rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
 944                 if (rxint_level)\r
 945                         rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
 946                 /* Set the interrupt mask, for poll mode just diable all int */\r
 947                 spi_mask_intr(dws, 0xff);\r
 948                 if (imask)\r
 949                         spi_umask_intr(dws, imask);\r
 950                 \r
 951                 if (cs_change)\r
 952                         dws->prev_chip = chip;\r
 953         } \r
 954 \r
 955         if (chip->poll_mode)\r
 956                 poll_transfer(dws);\r
 957 \r
 958         return;\r
 959 \r
 960 early_exit:\r
 961         giveback(dws);\r
 962         return;\r
 963 }\r
 964 \r
 965 static void dma_transfer(struct rk29xx_spi *dws) \r
 966 {\r
 967         struct spi_message *message = NULL;\r
 968         struct spi_transfer *transfer = NULL;\r
 969         struct spi_transfer *previous = NULL;\r
 970         struct spi_device *spi = NULL;\r
 971         struct chip_data *chip = NULL;\r
 972         //unsigned long val;    \r
 973         //unsigned long flags;\r
 974         //int ms;\r
 975         int iRet;\r
 976         //int burst;\r
 977         u8 bits = 0;\r
 978         u8 spi_dfs = 0;\r
 979         u8 cs_change = 0;\r
 980         u16 clk_div = 0;\r
 981         u32 speed = 0;\r
 982         u32 cr0 = 0;\r
 983         u32 dmacr = 0;\r
 984         \r
 985         DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);  \r
 986         \r
 987         if (acquire_dma(dws)) {\r
 988                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 989                 goto err_out;\r
 990         }\r
 991 \r
 992         if (map_dma_buffers(dws)) {\r
 993                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 994                 goto err_out;\r
 995         }\r
 996 \r
 997         /* Get current state information */\r
 998         message = dws->cur_msg;\r
 999         transfer = dws->cur_transfer;\r
1000         chip = dws->cur_chip;\r
1001         spi = message->spi;     \r
1002         if (unlikely(!chip->clk_div))\r
1003                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
1004         if (message->state == ERROR_STATE) {\r
1005                 message->status = -EIO;\r
1006                 goto err_out;\r
1007         }\r
1008 \r
1009         /* Handle end of message */\r
1010         if (message->state == DONE_STATE) {\r
1011                 message->status = 0;\r
1012                 goto err_out;\r
1013         }\r
1014 \r
1015         /* Delay if requested at end of transfer*/\r
1016         if (message->state == RUNNING_STATE) {\r
1017                 previous = list_entry(transfer->transfer_list.prev,\r
1018                                         struct spi_transfer,\r
1019                                         transfer_list);\r
1020                 if (previous->delay_usecs)\r
1021                         udelay(previous->delay_usecs);\r
1022         }\r
1023 \r
1024         dws->n_bytes = chip->n_bytes;\r
1025         dws->dma_width = chip->dma_width;\r
1026         dws->cs_control = chip->cs_control;\r
1027 \r
1028         //dws->rx_dma = transfer->rx_dma;\r
1029         //dws->tx_dma = transfer->tx_dma;\r
1030         dws->tx = (void *)transfer->tx_buf;\r
1031         dws->tx_end = dws->tx + transfer->len;\r
1032         dws->rx = (void *)transfer->rx_buf;\r
1033         dws->rx_end = dws->rx + transfer->len;\r
1034         dws->write = dws->tx ? chip->write : null_writer;\r
1035         dws->read = dws->rx ? chip->read : null_reader;\r
1036         dws->cs_change = transfer->cs_change;\r
1037         dws->len = dws->cur_transfer->len;\r
1038         if (chip != dws->prev_chip)\r
1039                 cs_change = 1;\r
1040 \r
1041         cr0 = chip->cr0;\r
1042         \r
1043         /* Handle per transfer options for bpw and speed */\r
1044         if (transfer->speed_hz) {\r
1045                 speed = chip->speed_hz;\r
1046                 if (transfer->speed_hz != speed) {\r
1047                         speed = transfer->speed_hz;\r
1048                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1049                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported "\r
1050                                         "freq: %dHz\n", speed);\r
1051                                 message->status = -EIO;\r
1052                                 goto err_out;\r
1053                         }\r
1054 \r
1055                         /* clk_div doesn't support odd number */\r
1056                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1057                         clk_div = (clk_div + 1) & 0xfffe;\r
1058 \r
1059                         chip->speed_hz = speed;\r
1060                         chip->clk_div = clk_div;\r
1061                 }\r
1062         }\r
1063 \r
1064         \r
1065         if (transfer->bits_per_word) {\r
1066                 bits = transfer->bits_per_word;\r
1067 \r
1068                 switch (bits) {\r
1069                 case 8:\r
1070                         dws->n_bytes = 1;\r
1071                         dws->dma_width = 1;\r
1072                         spi_dfs = SPI_DFS_8BIT;\r
1073                         break;\r
1074                 case 16:\r
1075                         dws->n_bytes = 2;\r
1076                         dws->dma_width = 2;\r
1077                         spi_dfs = SPI_DFS_16BIT;\r
1078                         break;\r
1079                 default:\r
1080                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1081                                 "%db\n", bits);\r
1082                         message->status = -EIO;\r
1083                         goto err_out;\r
1084                 }\r
1085 \r
1086                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1087                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1088                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1089                         | (chip->type << SPI_FRF_OFFSET)\r
1090                         | (spi->mode << SPI_MODE_OFFSET)\r
1091                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1092         }\r
1093         message->state = RUNNING_STATE;\r
1094  \r
1095         /*\r
1096          * Adjust transfer mode if necessary. Requires platform dependent\r
1097          * chipselect mechanism.\r
1098          */\r
1099         if (dws->cs_control) {\r
1100                 if (dws->rx && dws->tx)\r
1101                         chip->tmode = SPI_TMOD_TR;\r
1102                 else if (dws->rx)\r
1103                         chip->tmode = SPI_TMOD_RO;\r
1104                 else\r
1105                         chip->tmode = SPI_TMOD_TO;\r
1106 \r
1107                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1108                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);\r
1109                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1110         }\r
1111 \r
1112         /*\r
1113          * Reprogram registers only if\r
1114          *      1. chip select changes\r
1115          *      2. clk_div is changed\r
1116          *      3. control value changes\r
1117          */\r
1118         if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div) {\r
1119                 spi_enable_chip(dws, 0);\r
1120                 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0) {\r
1121                         rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
1122                 }\r
1123                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1124                 spi_chip_sel(dws, spi->chip_select);\r
1125                 /* Set the interrupt mask, for poll mode just diable all int */\r
1126                 spi_mask_intr(dws, 0xff);\r
1127                 \r
1128                 if (transfer->tx_buf != NULL) {\r
1129                         dmacr |= SPI_DMACR_TX_ENABLE;\r
1130                         rk29xx_writew(dws, SPIM_DMATDLR, 0);\r
1131                 }\r
1132                 if (transfer->rx_buf != NULL) {\r
1133                         dmacr |= SPI_DMACR_RX_ENABLE;\r
1134                         rk29xx_writew(dws, SPIM_DMARDLR, 0);\r
1135                         rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);       \r
1136                 }\r
1137                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1138                 spi_enable_chip(dws, 1);\r
1139                 if (cs_change)\r
1140                         dws->prev_chip = chip;\r
1141         } \r
1142 \r
1143         //INIT_COMPLETION(dws->xfer_completion);\r
1144 \r
1145         //spi_dump_regs(dws);\r
1146         \r
1147         DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, dws->tx_dma: 0x%x,dws->rx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)dws->tx_dma,(unsigned int)dws->rx_dma);  \r
1148         DBG("dws->buffer_tx_dma: 0x%p, dws->buffer_rx_dma: 0x%p,dws->dma_width=%d\n", dws->buffer_tx_dma, dws->buffer_rx_dma,dws->dma_width);   \r
1149 \r
1150         if (transfer->tx_buf != NULL)           \r
1151                 dws->state |= TXBUSY;   \r
1152         if (transfer->rx_buf != NULL) \r
1153                 dws->state |= RXBUSY;\r
1154 \r
1155         if (transfer->tx_buf != NULL) { \r
1156                 DBG("%s:start dma tx,dws->state=0x%x\n",__func__,dws->state);\r
1157                 #if defined(PRINT_TRANS_DATA)\r
1158                 printk("dma tx:");\r
1159                 printk_transfer_data(dws->buffer_tx_dma, dws->cur_transfer->len);\r
1160                 #endif\r
1161                 /*if (transfer->len & 0x3) {\r
1162                         burst = 1;\r
1163                 }\r
1164                 else {\r
1165                         burst = 4;\r
1166                 }\r
1167                 if (rk29_dma_config(dws->tx_dmach, burst)) {*/\r
1168                 if (rk29_dma_config(dws->tx_dmach, dws->dma_width, 1)) {//there is not dma burst but bitwide, set it 1 alwayss\r
1169                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1170                         goto err_out;\r
1171                 }\r
1172                 \r
1173                 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH); \r
1174                 \r
1175                 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,\r
1176                                         dws->tx_dma, transfer->len);\r
1177                 if (iRet) {\r
1178                         dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet, \r
1179                                 dws->tx_dmach, (unsigned int)transfer->tx_dma);\r
1180                         goto err_out;\r
1181                 }\r
1182                 \r
1183                 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {\r
1184                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1185                         goto err_out;\r
1186                 }\r
1187         }\r
1188 \r
1189         //wait_till_not_busy(dws);\r
1190         \r
1191         if (transfer->rx_buf != NULL) {                 \r
1192                 DBG("%s:start dma rx,dws->state=0x%x\n",__func__,dws->state);\r
1193                 if (rk29_dma_config(dws->rx_dmach, dws->dma_width, 1)) {\r
1194                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1195                         goto err_out;\r
1196                 }\r
1197 \r
1198                 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH); \r
1199                 \r
1200                 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,\r
1201                                         dws->rx_dma, transfer->len);\r
1202                 if (iRet) {\r
1203                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1204                         goto err_out;\r
1205                 }\r
1206                 \r
1207                 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {\r
1208                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1209                         goto err_out;\r
1210                 }\r
1211         }\r
1212         \r
1213         //wait_till_not_busy(dws);\r
1214         \r
1215         return;\r
1216 \r
1217 err_out:\r
1218         giveback(dws);\r
1219         return;\r
1220 \r
1221 }\r
1222 \r
1223 static void pump_messages(struct work_struct *work)\r
1224 {\r
1225         struct rk29xx_spi *dws =\r
1226                 container_of(work, struct rk29xx_spi, pump_messages);\r
1227         unsigned long flags;\r
1228 \r
1229         DBG(KERN_INFO "pump_messages,line=%d\n",__LINE__);\r
1230         \r
1231         /* Lock queue and check for queue work */\r
1232         spin_lock_irqsave(&dws->lock, flags);\r
1233         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1234                 dws->busy = 0;\r
1235                 spin_unlock_irqrestore(&dws->lock, flags);\r
1236                 DBG("%s:line=%d,list_empty\n",__func__,__LINE__);\r
1237                 return;\r
1238         }\r
1239 \r
1240         /* Make sure we are not already running a message */\r
1241         if (dws->cur_msg) {\r
1242                 spin_unlock_irqrestore(&dws->lock, flags);              \r
1243                 DBG("%s:line=%d,dws->cur_msg\n",__func__,__LINE__);\r
1244                 return;\r
1245         }\r
1246 \r
1247         /* Extract head of queue */\r
1248         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1249         list_del_init(&dws->cur_msg->queue);\r
1250 \r
1251         /* Initial message state*/\r
1252         dws->cur_msg->state = START_STATE;\r
1253         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1254                                                 struct spi_transfer,\r
1255                                                 transfer_list);\r
1256         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1257         dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1258 \r
1259         \r
1260         /* Mark as busy and launch transfers */\r
1261         tasklet_schedule(&dws->pump_transfers);\r
1262         dws->busy = 1;\r
1263         spin_unlock_irqrestore(&dws->lock, flags);\r
1264         \r
1265 }\r
1266 \r
1267 #if defined(QUICK_TRANSFER)\r
1268 static void do_read(struct rk29xx_spi *dws)\r
1269 {\r
1270         int count = 0;\r
1271 \r
1272         spi_enable_chip(dws, 0);\r
1273         rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);\r
1274         spi_enable_chip(dws, 1);                \r
1275         rk29xx_writew(dws, SPIM_TXDR, 0);\r
1276         while (1) {\r
1277                 if (dws->read(dws))\r
1278                         break;\r
1279                 if (count++ == 0x20) {\r
1280                         dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");\r
1281                         break;\r
1282                 }\r
1283                 \r
1284         }\r
1285 }\r
1286 \r
1287 static void do_write(struct rk29xx_spi *dws)\r
1288 {\r
1289         while (dws->tx<dws->tx_end) {\r
1290                 dws->write(dws);\r
1291         }\r
1292 }\r
1293 \r
1294 /* Caller already set message->status; dma and pio irqs are blocked */\r
1295 static void msg_giveback(struct rk29xx_spi *dws)\r
1296 {\r
1297         struct spi_transfer *last_transfer;\r
1298         struct spi_message *msg;\r
1299 \r
1300         DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1301 \r
1302         msg = dws->cur_msg;\r
1303         dws->cur_msg = NULL;\r
1304         dws->cur_transfer = NULL;\r
1305         dws->prev_chip = dws->cur_chip;\r
1306         dws->cur_chip = NULL;\r
1307         dws->dma_mapped = 0;\r
1308         dws->busy = 0;\r
1309 \r
1310         last_transfer = list_entry(msg->transfers.prev,\r
1311                                         struct spi_transfer,\r
1312                                         transfer_list);\r
1313 \r
1314         if (!last_transfer->cs_change && dws->cs_control)\r
1315                 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
1316 \r
1317         msg->state = NULL;      \r
1318 }\r
1319 \r
1320 /* Must be called inside pump_transfers() */\r
1321 static int do_full_transfer(struct rk29xx_spi *dws)\r
1322 {\r
1323         if ((dws->read(dws))) {\r
1324                 goto comple;\r
1325         }\r
1326         \r
1327         while (dws->tx<dws->tx_end){\r
1328                 dws->write(dws);                \r
1329                 dws->read(dws);\r
1330         }\r
1331         \r
1332         if (dws->rx < dws->rx_end) {\r
1333                 dws->read(dws);\r
1334         }\r
1335 \r
1336 comple:\r
1337         \r
1338         dws->cur_msg->actual_length += dws->len;\r
1339         \r
1340         /* Move to next transfer */\r
1341         dws->cur_msg->state = next_transfer(dws);\r
1342                                         \r
1343         if (dws->cur_msg->state == DONE_STATE) {\r
1344                 dws->cur_msg->status = 0;\r
1345                 //msg_giveback(dws);\r
1346                 return 0;\r
1347         }\r
1348         else {\r
1349                 return -1;\r
1350         }\r
1351         \r
1352 }\r
1353 \r
1354 \r
1355 /* Must be called inside pump_transfers() */\r
1356 static int do_half_transfer(struct rk29xx_spi *dws)\r
1357 {\r
1358         if (dws->rx) {\r
1359                 if (dws->tx) {\r
1360                         do_write(dws);\r
1361                 }\r
1362                 wait_till_tf_empty(dws);\r
1363                 wait_till_not_busy(dws);\r
1364                 do_read(dws);\r
1365         }\r
1366         else {\r
1367                 do_write(dws);\r
1368                 wait_till_tf_empty(dws);\r
1369                 wait_till_not_busy(dws);\r
1370         }\r
1371         \r
1372         dws->cur_msg->actual_length += dws->len;\r
1373         \r
1374         /* Move to next transfer */\r
1375         dws->cur_msg->state = next_transfer(dws);\r
1376                                         \r
1377         if (dws->cur_msg->state == DONE_STATE) {\r
1378                 dws->cur_msg->status = 0;\r
1379                 //msg_giveback(dws);\r
1380                 return 0;\r
1381         }\r
1382         else {\r
1383                 return -1;\r
1384         }\r
1385 }\r
1386 \r
1387 \r
1388 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)\r
1389 {\r
1390         struct spi_message *message = NULL;\r
1391         struct spi_transfer *transfer = NULL;\r
1392         struct spi_transfer *previous = NULL;\r
1393         struct spi_device *spi = NULL;\r
1394         struct chip_data *chip = NULL;\r
1395         u8 bits = 0;\r
1396         u8 spi_dfs = 0;\r
1397         u8 cs_change = 0;\r
1398         u16 clk_div = 0;\r
1399         u32 speed = 0;\r
1400         u32 cr0 = 0;\r
1401         u32 dmacr = 0;\r
1402         \r
1403         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1404 \r
1405         /* Get current state information */\r
1406         message = dws->cur_msg;\r
1407         transfer = dws->cur_transfer;\r
1408         chip = dws->cur_chip;\r
1409         spi = message->spi;     \r
1410 \r
1411         if (unlikely(!chip->clk_div))\r
1412                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;\r
1413         if (message->state == ERROR_STATE) {\r
1414                 message->status = -EIO;\r
1415                 goto early_exit;\r
1416         }\r
1417 \r
1418         /* Handle end of message */\r
1419         if (message->state == DONE_STATE) {\r
1420                 message->status = 0;\r
1421                 goto early_exit;\r
1422         }\r
1423 \r
1424         /* Delay if requested at end of transfer*/\r
1425         if (message->state == RUNNING_STATE) {\r
1426                 previous = list_entry(transfer->transfer_list.prev,\r
1427                                         struct spi_transfer,\r
1428                                         transfer_list);\r
1429                 if (previous->delay_usecs)\r
1430                         udelay(previous->delay_usecs);\r
1431         }\r
1432 \r
1433         dws->n_bytes = chip->n_bytes;\r
1434         dws->dma_width = chip->dma_width;\r
1435         dws->cs_control = chip->cs_control;\r
1436 \r
1437         dws->rx_dma = transfer->rx_dma;\r
1438         dws->tx_dma = transfer->tx_dma;\r
1439         dws->tx = (void *)transfer->tx_buf;\r
1440         dws->tx_end = dws->tx + transfer->len;\r
1441         dws->rx = transfer->rx_buf;\r
1442         dws->rx_end = dws->rx + transfer->len;\r
1443         dws->write = dws->tx ? chip->write : null_writer;\r
1444         dws->read = dws->rx ? chip->read : null_reader;\r
1445         if (dws->rx && dws->tx) {\r
1446                 int temp_len = transfer->len;\r
1447                 int len;\r
1448                 unsigned char *tx_buf;\r
1449                 for (len=0; *tx_buf++ != 0; len++);\r
1450                 dws->tx_end = dws->tx + len;\r
1451                 dws->rx_end = dws->rx + temp_len - len;\r
1452         }\r
1453         dws->cs_change = transfer->cs_change;\r
1454         dws->len = dws->cur_transfer->len;\r
1455         if (chip != dws->prev_chip)\r
1456                 cs_change = 1;\r
1457 \r
1458         cr0 = chip->cr0;\r
1459 \r
1460         /* Handle per transfer options for bpw and speed */\r
1461         if (transfer->speed_hz) {\r
1462                 speed = chip->speed_hz;\r
1463 \r
1464                 if (transfer->speed_hz != speed) {\r
1465                         speed = transfer->speed_hz;\r
1466                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1467                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1468                                         "freq: %dHz\n", speed);\r
1469                                 message->status = -EIO;\r
1470                                 goto early_exit;\r
1471                         }\r
1472 \r
1473                         /* clk_div doesn't support odd number */\r
1474                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1475                         clk_div = (clk_div + 1) & 0xfffe;\r
1476 \r
1477                         chip->speed_hz = speed;\r
1478                         chip->clk_div = clk_div;\r
1479                 }\r
1480         }\r
1481         if (transfer->bits_per_word) {\r
1482                 bits = transfer->bits_per_word;\r
1483 \r
1484                 switch (bits) {\r
1485                 case 8:\r
1486                         dws->n_bytes = 1;\r
1487                         dws->dma_width = 1;\r
1488                         dws->read = (dws->read != null_reader) ?\r
1489                                         u8_reader : null_reader;\r
1490                         dws->write = (dws->write != null_writer) ?\r
1491                                         u8_writer : null_writer;\r
1492                         spi_dfs = SPI_DFS_8BIT;\r
1493                         break;\r
1494                 case 16:\r
1495                         dws->n_bytes = 2;\r
1496                         dws->dma_width = 2;\r
1497                         dws->read = (dws->read != null_reader) ?\r
1498                                         u16_reader : null_reader;\r
1499                         dws->write = (dws->write != null_writer) ?\r
1500                                         u16_writer : null_writer;\r
1501                         spi_dfs = SPI_DFS_16BIT;\r
1502                         break;\r
1503                 default:\r
1504                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1505                                 "%db\n", bits);\r
1506                         message->status = -EIO;\r
1507                         goto early_exit;\r
1508                 }\r
1509 \r
1510                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1511                         | (chip->type << SPI_FRF_OFFSET)\r
1512                         | (spi->mode << SPI_MODE_OFFSET)\r
1513                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1514         }\r
1515         message->state = RUNNING_STATE;\r
1516  \r
1517         /*\r
1518          * Adjust transfer mode if necessary. Requires platform dependent\r
1519          * chipselect mechanism.\r
1520          */\r
1521         if (dws->cs_control) {\r
1522                 if (dws->rx && dws->tx)\r
1523                         chip->tmode = SPI_TMOD_TR;\r
1524                 else if (dws->rx)\r
1525                         chip->tmode = SPI_TMOD_RO;\r
1526                 else\r
1527                         chip->tmode = SPI_TMOD_TO;\r
1528 \r
1529                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1530                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1531         }\r
1532         \r
1533         /* Check if current transfer is a DMA transaction */\r
1534         dws->dma_mapped = map_dma_buffers(dws);\r
1535 \r
1536         /*\r
1537          * Reprogram registers only if\r
1538          *      1. chip select changes\r
1539          *      2. clk_div is changed\r
1540          *      3. control value changes\r
1541          */\r
1542         spi_enable_chip(dws, 0);\r
1543         if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)\r
1544                 rk29xx_writel(dws, SPIM_CTRLR0, cr0);\r
1545 \r
1546     DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);\r
1547         spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1548         spi_chip_sel(dws, spi->chip_select);            \r
1549         rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx\r
1550         if(dws->dma_mapped ) {\r
1551                 dmacr = rk29xx_readw(dws, SPIM_DMACR);\r
1552                 dmacr = dmacr | SPI_DMACR_TX_ENABLE;\r
1553                 if (mode) \r
1554                         dmacr = dmacr | SPI_DMACR_RX_ENABLE;\r
1555                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1556         }\r
1557         spi_enable_chip(dws, 1);\r
1558         if (cs_change)\r
1559                 dws->prev_chip = chip;\r
1560         \r
1561         if (mode)\r
1562                 return do_full_transfer(dws);\r
1563         else\r
1564                 return do_half_transfer(dws);   \r
1565         \r
1566 early_exit:\r
1567         \r
1568         //msg_giveback(dws);\r
1569         \r
1570         return 0;\r
1571 }\r
1572 \r
1573 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)\r
1574 {\r
1575         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1576         \r
1577         while (!acquire_dma(dws))\r
1578                         msleep(10);\r
1579 \r
1580         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1581                 dws->busy = 0;\r
1582                 return;\r
1583         }\r
1584 \r
1585         /* Make sure we are not already running a message */\r
1586         if (dws->cur_msg) {\r
1587                 return;\r
1588         }\r
1589 \r
1590         /* Extract head of queue */\r
1591         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1592         list_del_init(&dws->cur_msg->queue);\r
1593 \r
1594         /* Initial message state*/\r
1595         dws->cur_msg->state = START_STATE;\r
1596         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1597                                                 struct spi_transfer,\r
1598                                                 transfer_list);\r
1599         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1600     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1601     \r
1602         /* Mark as busy and launch transfers */\r
1603         dws->busy = 1;\r
1604 \r
1605         while (rk29xx_pump_transfers(dws, mode)) ;\r
1606 }\r
1607 \r
1608 /* spi_device use this to queue in their spi_msg */\r
1609 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)\r
1610 {\r
1611         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1612         unsigned long flags;\r
1613         struct rk29xx_spi_chip *chip_info = spi->controller_data;\r
1614         struct spi_message *mmsg;\r
1615         \r
1616         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1617         \r
1618         spin_lock_irqsave(&dws->lock, flags);\r
1619 \r
1620         if (dws->run == QUEUE_STOPPED) {\r
1621                 spin_unlock_irqrestore(&dws->lock, flags);\r
1622                 return -ESHUTDOWN;\r
1623         }\r
1624 \r
1625         msg->actual_length = 0;\r
1626         msg->status = -EINPROGRESS;\r
1627         msg->state = START_STATE;\r
1628 \r
1629         list_add_tail(&msg->queue, &dws->queue);\r
1630 \r
1631         if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {\r
1632                 rk29xx_pump_messages(dws,1);\r
1633         }\r
1634         else {          \r
1635                 rk29xx_pump_messages(dws,0);\r
1636         }\r
1637 \r
1638         mmsg = dws->cur_msg;\r
1639         msg_giveback(dws);\r
1640         \r
1641         spin_unlock_irqrestore(&dws->lock, flags);\r
1642 \r
1643         if (mmsg->complete)\r
1644                 mmsg->complete(mmsg->context);\r
1645         \r
1646         return 0;\r
1647 }\r
1648 \r
1649 #else\r
1650 \r
1651 /* spi_device use this to queue in their spi_msg */\r
1652 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)\r
1653 {\r
1654         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1655         unsigned long flags;\r
1656 \r
1657         spin_lock_irqsave(&dws->lock, flags);\r
1658 \r
1659         if (dws->run == QUEUE_STOPPED) {\r
1660                 spin_unlock_irqrestore(&dws->lock, flags);\r
1661                 return -ESHUTDOWN;\r
1662         }\r
1663 \r
1664         msg->actual_length = 0;\r
1665         msg->status = -EINPROGRESS;\r
1666         msg->state = START_STATE;\r
1667 \r
1668         list_add_tail(&msg->queue, &dws->queue);\r
1669 \r
1670         if (dws->run == QUEUE_RUNNING && !dws->busy) {\r
1671 \r
1672                 if (dws->cur_transfer || dws->cur_msg)\r
1673                         queue_work(dws->workqueue,\r
1674                                         &dws->pump_messages);\r
1675                 else {\r
1676                         /* If no other data transaction in air, just go */\r
1677                         spin_unlock_irqrestore(&dws->lock, flags);\r
1678                         pump_messages(&dws->pump_messages);                     \r
1679                         return 0;\r
1680                 }\r
1681         }\r
1682 \r
1683         spin_unlock_irqrestore(&dws->lock, flags);\r
1684         \r
1685         return 0;\r
1686 }\r
1687 \r
1688 #endif\r
1689 \r
1690 /* This may be called twice for each spi dev */\r
1691 static int rk29xx_spi_setup(struct spi_device *spi)\r
1692 {\r
1693         struct rk29xx_spi_chip *chip_info = NULL;\r
1694         struct chip_data *chip;\r
1695         u8 spi_dfs = 0;\r
1696 \r
1697         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)\r
1698                 return -EINVAL;\r
1699 \r
1700         /* Only alloc on first setup */\r
1701         chip = spi_get_ctldata(spi);\r
1702         if (!chip) {\r
1703                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\r
1704                 if (!chip)\r
1705                         return -ENOMEM;\r
1706 \r
1707                 chip->cs_control = spi_cs_control;\r
1708                 chip->enable_dma = 0;  //0;\r
1709         }\r
1710 \r
1711         /*\r
1712          * Protocol drivers may change the chip settings, so...\r
1713          * if chip_info exists, use it\r
1714          */\r
1715         chip_info = spi->controller_data;\r
1716 \r
1717         /* chip_info doesn't always exist */\r
1718         if (chip_info) {\r
1719                 if (chip_info->cs_control)\r
1720                         chip->cs_control = chip_info->cs_control;\r
1721 \r
1722                 chip->poll_mode = chip_info->poll_mode;\r
1723                 chip->type = chip_info->type;\r
1724 \r
1725                 chip->rx_threshold = 0;\r
1726                 chip->tx_threshold = 0;\r
1727 \r
1728                 chip->enable_dma = chip_info->enable_dma;\r
1729         }\r
1730 \r
1731         if (spi->bits_per_word == 8) {\r
1732                 chip->n_bytes = 1;\r
1733                 chip->dma_width = 1;\r
1734                 chip->read = u8_reader;\r
1735                 chip->write = u8_writer;\r
1736                 spi_dfs = SPI_DFS_8BIT;\r
1737         } else if (spi->bits_per_word == 16) {\r
1738                 chip->n_bytes = 2;\r
1739                 chip->dma_width = 2;\r
1740                 chip->read = u16_reader;\r
1741                 chip->write = u16_writer;\r
1742                 spi_dfs = SPI_DFS_16BIT;\r
1743         } else {\r
1744                 /* Never take >16b case for MRST SPIC */\r
1745                 dev_err(&spi->dev, "invalid wordsize\n");\r
1746                 return -EINVAL;\r
1747         }\r
1748         chip->bits_per_word = spi->bits_per_word;\r
1749 \r
1750         if (!spi->max_speed_hz) {\r
1751                 dev_err(&spi->dev, "No max speed HZ parameter\n");\r
1752                 return -EINVAL;\r
1753         }\r
1754         chip->speed_hz = spi->max_speed_hz;\r
1755 \r
1756         chip->tmode = 0; /* Tx & Rx */\r
1757         /* Default SPI mode is SCPOL = 0, SCPH = 0 */\r
1758         chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1759                 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1760                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1761                         | (chip->type << SPI_FRF_OFFSET)\r
1762                         | (spi->mode  << SPI_MODE_OFFSET)\r
1763                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1764 \r
1765         spi_set_ctldata(spi, chip);\r
1766         return 0;\r
1767 }\r
1768 \r
1769 static void rk29xx_spi_cleanup(struct spi_device *spi)\r
1770 {\r
1771         struct chip_data *chip = spi_get_ctldata(spi);\r
1772         kfree(chip);\r
1773 }\r
1774 \r
1775 static int __devinit init_queue(struct rk29xx_spi *dws)\r
1776 {\r
1777         INIT_LIST_HEAD(&dws->queue);\r
1778         spin_lock_init(&dws->lock);\r
1779 \r
1780         dws->run = QUEUE_STOPPED;\r
1781         dws->busy = 0;\r
1782 \r
1783         init_completion(&dws->xfer_completion);\r
1784 \r
1785         tasklet_init(&dws->pump_transfers,\r
1786                         pump_transfers, (unsigned long)dws);\r
1787 \r
1788         INIT_WORK(&dws->pump_messages, pump_messages);\r
1789         dws->workqueue = create_singlethread_workqueue(\r
1790                                         dev_name(dws->master->dev.parent));\r
1791         if (dws->workqueue == NULL)\r
1792                 return -EBUSY;\r
1793 \r
1794 \r
1795         return 0;\r
1796 }\r
1797 \r
1798 static int start_queue(struct rk29xx_spi *dws)\r
1799 {\r
1800         unsigned long flags;\r
1801 \r
1802         spin_lock_irqsave(&dws->lock, flags);\r
1803 \r
1804         if (dws->run == QUEUE_RUNNING || dws->busy) {\r
1805                 spin_unlock_irqrestore(&dws->lock, flags);\r
1806                 return -EBUSY;\r
1807         }\r
1808 \r
1809         dws->run = QUEUE_RUNNING;\r
1810         dws->cur_msg = NULL;\r
1811         dws->cur_transfer = NULL;\r
1812         dws->cur_chip = NULL;\r
1813         dws->prev_chip = NULL;\r
1814         spin_unlock_irqrestore(&dws->lock, flags);\r
1815 \r
1816         queue_work(dws->workqueue, &dws->pump_messages);\r
1817 \r
1818         return 0;\r
1819 }\r
1820 \r
1821 static int stop_queue(struct rk29xx_spi *dws)\r
1822 {\r
1823         unsigned long flags;\r
1824         unsigned limit = 50;\r
1825         int status = 0;\r
1826 \r
1827         spin_lock_irqsave(&dws->lock, flags);\r
1828         dws->run = QUEUE_STOPPED;\r
1829         while (!list_empty(&dws->queue) && dws->busy && limit--) {\r
1830                 spin_unlock_irqrestore(&dws->lock, flags);\r
1831                 msleep(10);\r
1832                 spin_lock_irqsave(&dws->lock, flags);\r
1833         }\r
1834 \r
1835         if (!list_empty(&dws->queue) || dws->busy)\r
1836                 status = -EBUSY;\r
1837         spin_unlock_irqrestore(&dws->lock, flags);\r
1838 \r
1839         return status;\r
1840 }\r
1841 \r
1842 static int destroy_queue(struct rk29xx_spi *dws)\r
1843 {\r
1844         int status;\r
1845 \r
1846         status = stop_queue(dws);\r
1847         if (status != 0)\r
1848                 return status;\r
1849         destroy_workqueue(dws->workqueue);\r
1850         return 0;\r
1851 }\r
1852 \r
1853 /* Restart the controller, disable all interrupts, clean rx fifo */\r
1854 static void spi_hw_init(struct rk29xx_spi *dws)\r
1855 {\r
1856         spi_enable_chip(dws, 0);\r
1857         spi_mask_intr(dws, 0xff);\r
1858         \r
1859         /*\r
1860          * Try to detect the FIFO depth if not set by interface driver,\r
1861          * the depth could be from 2 to 32 from HW spec\r
1862          */\r
1863         if (!dws->fifo_len) {\r
1864                 u32 fifo;\r
1865                 for (fifo = 2; fifo <= 31; fifo++) {\r
1866                         rk29xx_writew(dws, SPIM_TXFTLR, fifo);\r
1867                         if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))\r
1868                                 break;\r
1869                 }\r
1870 \r
1871                 dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
1872                 rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
1873         }\r
1874         \r
1875         spi_enable_chip(dws, 1);\r
1876         //flush(dws);\r
1877 }\r
1878 \r
1879 /* cpufreq driver support */\r
1880 #ifdef CONFIG_CPU_FREQ\r
1881 \r
1882 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)\r
1883 {\r
1884         struct rk29xx_spi *info;\r
1885         unsigned long newclk;\r
1886 \r
1887         info = container_of(nb, struct rk29xx_spi, freq_transition);\r
1888         newclk = clk_get_rate(info->clock_spim);\r
1889 \r
1890         return 0;\r
1891 }\r
1892 \r
1893 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1894 {\r
1895         info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;\r
1896 \r
1897         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1898 }\r
1899 \r
1900 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1901 {\r
1902         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1903 }\r
1904 \r
1905 #else\r
1906 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1907 {\r
1908         return 0;\r
1909 }\r
1910 \r
1911 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1912 {\r
1913 }\r
1914 #endif\r
1915 static int __init rk29xx_spim_probe(struct platform_device *pdev)\r
1916 {\r
1917         struct resource         *regs, *dmatx_res, *dmarx_res;\r
1918         struct rk29xx_spi   *dws;\r
1919         struct spi_master   *master;\r
1920         int                     irq; \r
1921         int ret;\r
1922         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
1923 \r
1924         if (pdata && pdata->io_init) {\r
1925                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
1926                 if (ret) {                      \r
1927                         return -ENXIO;  \r
1928                 }\r
1929         }\r
1930         \r
1931         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1932         if (!regs)\r
1933                 return -ENXIO;\r
1934         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);\r
1935         if (dmatx_res == NULL) {\r
1936                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");\r
1937                 return -ENXIO;\r
1938         }\r
1939 \r
1940         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);\r
1941         if (dmarx_res == NULL) {\r
1942                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");\r
1943                 return -ENXIO;\r
1944         }\r
1945         irq = platform_get_irq(pdev, 0);\r
1946         if (irq < 0)\r
1947                 return irq;                     \r
1948         /* setup spi core then atmel-specific driver state */\r
1949         ret = -ENOMEM;  \r
1950         master = spi_alloc_master(&pdev->dev, sizeof *dws);\r
1951         if (!master) {\r
1952                 ret = -ENOMEM;\r
1953                 goto exit;\r
1954         }\r
1955 \r
1956         platform_set_drvdata(pdev, master);\r
1957         dws = spi_master_get_devdata(master);\r
1958         dws->clock_spim = clk_get(&pdev->dev, "spi");\r
1959         clk_enable(dws->clock_spim);\r
1960         if (IS_ERR(dws->clock_spim)) {\r
1961                 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
1962                 return PTR_ERR(dws->clock_spim);\r
1963         }\r
1964 \r
1965         dws->pclk = clk_get(&pdev->dev, "pclk_spi");\r
1966         clk_enable(dws->pclk);\r
1967         \r
1968         mutex_init(&dws->dma_lock);\r
1969         \r
1970         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);\r
1971         if (!dws->regs){\r
1972         release_mem_region(regs->start, (regs->end - regs->start) + 1);\r
1973                 return -EBUSY;\r
1974         }\r
1975         DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
1976         dws->irq = irq;\r
1977         dws->irq_polarity = IRQF_TRIGGER_NONE;\r
1978         dws->master = master;\r
1979         dws->type = SSI_MOTO_SPI;\r
1980         dws->prev_chip = NULL;\r
1981         dws->sfr_start = regs->start;\r
1982         dws->tx_dmach = dmatx_res->start;\r
1983         dws->rx_dmach = dmarx_res->start;\r
1984         dws->dma_inited = 0;  ///0;\r
1985         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);\r
1986         ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,\r
1987                         "rk29xx_spim", dws);\r
1988         if (ret < 0) {\r
1989                 dev_err(&master->dev, "can not get IRQ\n");\r
1990                 goto err_free_master;\r
1991         }\r
1992 \r
1993         master->mode_bits = SPI_CPOL | SPI_CPHA;\r
1994         master->bus_num = pdev->id;\r
1995         master->num_chipselect = pdata->num_chipselect;\r
1996         master->dev.platform_data = pdata;\r
1997         master->cleanup = rk29xx_spi_cleanup;\r
1998         master->setup = rk29xx_spi_setup;\r
1999         #if defined(QUICK_TRANSFER)\r
2000         master->transfer = rk29xx_spi_quick_transfer;\r
2001         #else\r
2002         master->transfer = rk29xx_spi_transfer;\r
2003         #endif\r
2004         \r
2005         dws->pdev = pdev;\r
2006         /* Basic HW init */\r
2007         spi_hw_init(dws);\r
2008         flush(dws);\r
2009         /* Initial and start queue */\r
2010         ret = init_queue(dws);\r
2011         if (ret) {\r
2012                 dev_err(&master->dev, "problem initializing queue\n");\r
2013                 goto err_diable_hw;\r
2014         }\r
2015 \r
2016         ret = start_queue(dws);\r
2017         if (ret) {\r
2018                 dev_err(&master->dev, "problem starting queue\n");\r
2019                 goto err_diable_hw;\r
2020         }\r
2021 \r
2022         spi_master_set_devdata(master, dws);\r
2023         ret = spi_register_master(master);\r
2024         if (ret) {\r
2025                 dev_err(&master->dev, "problem registering spi master\n");\r
2026                 goto err_queue_alloc;\r
2027         }\r
2028 \r
2029     ret =rk29xx_spim_cpufreq_register(dws);\r
2030     if (ret < 0) {\r
2031         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
2032         goto err_queue_alloc;\r
2033     }\r
2034         printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);\r
2035         mrst_spi_debugfs_init(dws);\r
2036         return 0;\r
2037 \r
2038 err_queue_alloc:\r
2039         destroy_queue(dws);\r
2040 err_diable_hw:\r
2041         spi_enable_chip(dws, 0);\r
2042         free_irq(dws->irq, dws);\r
2043 err_free_master:\r
2044         spi_master_put(master);\r
2045         iounmap(dws->regs);\r
2046 exit:\r
2047         return ret;\r
2048 }\r
2049 \r
2050 static void __exit rk29xx_spim_remove(struct platform_device *pdev)\r
2051 {\r
2052         struct spi_master *master = platform_get_drvdata(pdev);\r
2053         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2054         int status = 0;\r
2055 \r
2056         if (!dws)\r
2057                 return;\r
2058         rk29xx_spim_cpufreq_deregister(dws);\r
2059         mrst_spi_debugfs_remove(dws);\r
2060 \r
2061         if(dws->buffer_tx_dma)\r
2062         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);\r
2063         if(dws->buffer_rx_dma)\r
2064         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);\r
2065         release_dma(dws);\r
2066 \r
2067         /* Remove the queue */\r
2068         status = destroy_queue(dws);\r
2069         if (status != 0)\r
2070                 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "\r
2071                         "complete, message memory not freed\n");\r
2072         \r
2073         clk_disable(dws->clock_spim);\r
2074         clk_put(dws->clock_spim);\r
2075         clk_disable(dws->pclk);\r
2076         clk_put(dws->pclk);\r
2077         spi_enable_chip(dws, 0);\r
2078         /* Disable clk */\r
2079         spi_set_clk(dws, 0);\r
2080         free_irq(dws->irq, dws);\r
2081 \r
2082         /* Disconnect from the SPI framework */\r
2083         spi_unregister_master(dws->master);\r
2084         iounmap(dws->regs);\r
2085 }\r
2086 \r
2087 \r
2088 #ifdef  CONFIG_PM\r
2089 \r
2090 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)\r
2091 {\r
2092         struct spi_master *master = platform_get_drvdata(pdev);\r
2093         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2094         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2095         int status;\r
2096         \r
2097         flush(dws);\r
2098         status = stop_queue(dws);\r
2099         if (status != 0)\r
2100                 return status;\r
2101         clk_disable(dws->clock_spim);\r
2102         if (pdata && pdata->io_fix_leakage_bug)\r
2103         {\r
2104                 pdata->io_fix_leakage_bug( );\r
2105         }\r
2106         clk_disable(dws->pclk);\r
2107         return 0;\r
2108 }\r
2109 \r
2110 static int rk29xx_spim_resume(struct platform_device *pdev)\r
2111 {\r
2112         struct spi_master *master = platform_get_drvdata(pdev);\r
2113         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2114         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2115         int ret;\r
2116 \r
2117         clk_enable(dws->pclk);\r
2118         clk_enable(dws->clock_spim);    \r
2119         spi_hw_init(dws);\r
2120         ret = start_queue(dws);\r
2121         if (ret)\r
2122                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);\r
2123         if (pdata && pdata->io_resume_leakage_bug)\r
2124         {\r
2125                 pdata->io_resume_leakage_bug( ); \r
2126         }\r
2127         return ret;\r
2128 }\r
2129 \r
2130 #else\r
2131 #define rk29xx_spim_suspend     NULL\r
2132 #define rk29xx_spim_resume      NULL\r
2133 #endif\r
2134 \r
2135 static struct platform_driver rk29xx_platform_spim_driver = {\r
2136         .remove         = __exit_p(rk29xx_spim_remove),\r
2137         .driver         = {\r
2138                 .name   = "rk29xx_spim",\r
2139                 .owner  = THIS_MODULE,\r
2140         },\r
2141         .suspend        = rk29xx_spim_suspend,\r
2142         .resume         = rk29xx_spim_resume,\r
2143 };\r
2144 \r
2145 static int __init rk29xx_spim_init(void)\r
2146 {\r
2147         int ret;\r
2148         ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);   \r
2149         return ret;\r
2150 }\r
2151 \r
2152 static void __exit rk29xx_spim_exit(void)\r
2153 {\r
2154         platform_driver_unregister(&rk29xx_platform_spim_driver);\r
2155 }\r
2156 \r
2157 arch_initcall_sync(rk29xx_spim_init);\r
2158 module_exit(rk29xx_spim_exit);\r
2159 \r
2160 MODULE_AUTHOR("www.rock-chips.com");\r
2161 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");\r
2162 MODULE_LICENSE("GPL");;\r
2163 \r