1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device
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3 * Copyright (C) 2010 ROCKCHIP, Inc.
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5 * This software is licensed under the terms of the GNU General Public
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6 * License version 2, as published by the Free Software Foundation, and
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7 * may be copied, distributed, and modified under those terms.
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9 * This program is distributed in the hope that it will be useful,
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 * GNU General Public License for more details.
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15 #include <linux/dma-mapping.h>
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16 #include <linux/interrupt.h>
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17 #include <linux/highmem.h>
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18 #include <linux/delay.h>
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19 #include <linux/slab.h>
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20 #include <linux/platform_device.h>
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21 #include <linux/clk.h>
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22 #include <linux/cpufreq.h>
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23 #include <mach/gpio.h>
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24 #include <mach/irqs.h>
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25 #include <linux/dma-mapping.h>
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26 #include <asm/dma.h>
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27 #include <linux/preempt.h>
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28 #include "rk29_spim.h"
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29 #include <linux/spi/spi.h>
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30 #include <mach/board.h>
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32 #ifdef CONFIG_DEBUG_FS
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33 #include <linux/debugfs.h>
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36 /*ÔÓеÄspiÇý¶¯Ð§ÂʱȽϵͣ¬
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37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Ê䣻
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38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Ê䣬ͬʱ¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬
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42 //#define QUICK_TRANSFER
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45 //#define PRINT_TRANS_DATA
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50 #define DMA_BUFFER_SIZE PAGE_SIZE
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51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO
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54 #define START_STATE ((void *)0)
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55 #define RUNNING_STATE ((void *)1)
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56 #define DONE_STATE ((void *)2)
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57 #define ERROR_STATE ((void *)-1)
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59 #define QUEUE_RUNNING 0
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60 #define QUEUE_STOPPED 1
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62 #define MRST_SPI_DEASSERT 0
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63 #define MRST_SPI_ASSERT 1 ///CS0
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64 #define MRST_SPI_ASSERT1 2 ///CS1
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66 /* Slave spi_dev related */
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69 u8 cs; /* chip select pin */
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70 u8 n_bytes; /* current is a 1/2/4 byte op */
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71 u8 tmode; /* TR/TO/RO/EEPROM */
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72 u8 type; /* SPI/SSP/MicroWire */
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74 u8 poll_mode; /* 1 means use poll mode */
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81 u16 clk_div; /* baud rate divider */
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82 u32 speed_hz; /* baud rate */
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83 int (*write)(struct rk29xx_spi *dws);
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84 int (*read)(struct rk29xx_spi *dws);
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85 void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);
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88 #define SUSPND (1<<0)
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89 #define SPIBUSY (1<<1)
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90 #define RXBUSY (1<<2)
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91 #define TXBUSY (1<<3)
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94 #ifdef CONFIG_LCD_USE_SPIM_CONTROL
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95 void rk29_lcd_spim_spin_lock(void)
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97 #ifdef CONFIG_LCD_USE_SPI0
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98 disable_irq(IRQ_SPI0);
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101 #ifdef CONFIG_LCD_USE_SPI1
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102 disable_irq(IRQ_SPI1);
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108 void rk29_lcd_spim_spin_unlock(void)
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112 #ifdef CONFIG_LCD_USE_SPI0
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113 enable_irq(IRQ_SPI0);
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116 #ifdef CONFIG_LCD_USE_SPI1
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117 enable_irq(IRQ_SPI1);
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121 void rk29_lcd_spim_spin_lock(void)
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126 void rk29_lcd_spim_spin_unlock(void)
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132 #if defined(PRINT_TRANS_DATA)
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133 static void printk_transfer_data(unsigned char *buf, int len)
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136 for(i=0; i<len; i++)
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137 printk("0x%x,",*buf++);
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144 static void spi_dump_regs(struct rk29xx_spi *dws) {
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145 DBG("MRST SPI0 registers:\n");
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146 DBG("=================================\n");
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147 DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));
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148 DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));
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149 DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));
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150 DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));
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151 DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));
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152 DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));
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153 DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));
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154 DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));
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155 DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));
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156 DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));
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157 DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));
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158 DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));
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159 DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));
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160 DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));
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161 DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));
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162 DBG("=================================\n");
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166 #ifdef CONFIG_DEBUG_FS
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167 static int spi_show_regs_open(struct inode *inode, struct file *file)
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169 file->private_data = inode->i_private;
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173 #define SPI_REGS_BUFSIZE 1024
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174 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
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175 size_t count, loff_t *ppos)
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177 struct rk29xx_spi *dws;
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182 dws = file->private_data;
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184 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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188 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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189 "MRST SPI0 registers:\n");
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190 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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191 "=================================\n");
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192 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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193 "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));
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194 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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195 "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));
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196 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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197 "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));
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198 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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199 "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));
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200 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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201 "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));
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202 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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203 "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));
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204 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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205 "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));
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206 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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207 "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));
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208 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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209 "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));
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210 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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211 "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));
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212 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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213 "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));
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214 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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215 "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));
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216 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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217 "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));
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218 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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219 "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));
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220 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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221 "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));
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222 len += printk(buf + len, SPI_REGS_BUFSIZE - len,
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223 "=================================\n");
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225 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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230 static const struct file_operations mrst_spi_regs_ops = {
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231 .owner = THIS_MODULE,
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232 .open = spi_show_regs_open,
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233 .read = spi_show_regs,
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236 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)
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238 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
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242 debugfs_create_file("registers", S_IFREG | S_IRUGO,
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243 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
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247 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)
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250 debugfs_remove_recursive(dws->debugfs);
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254 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)
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259 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)
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262 #endif /* CONFIG_DEBUG_FS */
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264 static void dma_transfer(struct rk29xx_spi *dws) ;
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265 static void transfer_complete(struct rk29xx_spi *dws);
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267 static void wait_till_not_busy(struct rk29xx_spi *dws)
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269 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
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271 while (time_before(jiffies, end)) {
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272 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))
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275 dev_err(&dws->master->dev,
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276 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
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279 #if defined(QUICK_TRANSFER)
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280 static void wait_till_tf_empty(struct rk29xx_spi *dws)
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282 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
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284 while (time_before(jiffies, end)) {
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285 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)
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288 dev_err(&dws->master->dev,
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289 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
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293 static void flush(struct rk29xx_spi *dws)
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295 while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))
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296 rk29xx_readw(dws, SPIM_RXDR);
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298 wait_till_not_busy(dws);
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301 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)
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305 rk29xx_writel(dws, SPIM_SER, 1 << cs);
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307 rk29xx_writel(dws, SPIM_SER, 0);
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310 struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;
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311 struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;
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314 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);
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317 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);
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322 static int null_writer(struct rk29xx_spi *dws)
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324 u8 n_bytes = dws->n_bytes;
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326 if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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327 || (dws->tx == dws->tx_end))
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329 rk29xx_writew(dws, SPIM_TXDR, 0);
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330 dws->tx += n_bytes;
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331 //wait_till_not_busy(dws);
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336 static int null_reader(struct rk29xx_spi *dws)
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338 u8 n_bytes = dws->n_bytes;
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339 DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);
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340 while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))
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341 && (dws->rx < dws->rx_end)) {
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342 rk29xx_readw(dws, SPIM_RXDR);
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343 dws->rx += n_bytes;
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345 wait_till_not_busy(dws);
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346 return dws->rx == dws->rx_end;
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349 static int u8_writer(struct rk29xx_spi *dws)
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351 //spi_dump_regs(dws)
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352 #if defined(PRINT_TRANS_DATA)
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353 DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));
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355 if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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356 || (dws->tx == dws->tx_end))
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358 rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));
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360 //wait_till_not_busy(dws);
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365 static int u8_reader(struct rk29xx_spi *dws)
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367 //spi_dump_regs(dws);
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368 while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)
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369 && (dws->rx < dws->rx_end)) {
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370 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;
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371 #if defined(PRINT_TRANS_DATA)
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372 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));
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377 wait_till_not_busy(dws);
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378 return dws->rx == dws->rx_end;
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381 static int u16_writer(struct rk29xx_spi *dws)
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383 #if defined(PRINT_TRANS_DATA)
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384 DBG("tx: 0x%04x\n", *(u16 *)(dws->tx));
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386 if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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387 || (dws->tx == dws->tx_end))
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390 rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));
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392 //wait_till_not_busy(dws);
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397 static int u16_reader(struct rk29xx_spi *dws)
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401 while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)
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402 && (dws->rx < dws->rx_end)) {
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403 temp = rk29xx_readw(dws, SPIM_RXDR);
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404 *(u16 *)(dws->rx) = temp;
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405 #if defined(PRINT_TRANS_DATA)
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406 DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));
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411 wait_till_not_busy(dws);
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412 return dws->rx == dws->rx_end;
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415 static void *next_transfer(struct rk29xx_spi *dws)
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417 struct spi_message *msg = dws->cur_msg;
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418 struct spi_transfer *trans = dws->cur_transfer;
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420 /* Move to next transfer */
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421 if (trans->transfer_list.next != &msg->transfers) {
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422 dws->cur_transfer =
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423 list_entry(trans->transfer_list.next,
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424 struct spi_transfer,
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426 return RUNNING_STATE;
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431 static void rk29_spi_dma_rxcb(void *buf_id,
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432 int size, enum rk29_dma_buffresult res)
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434 struct rk29xx_spi *dws = buf_id;
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435 unsigned long flags;
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437 DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);
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439 spin_lock_irqsave(&dws->lock, flags);
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441 if (res == RK29_RES_OK)
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442 dws->state &= ~RXBUSY;
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444 dev_err(&dws->master->dev, "error:DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);
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446 //copy data from dma to transfer buf
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447 if(dws->cur_transfer && (dws->cur_transfer->rx_buf != NULL))
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449 memcpy(dws->cur_transfer->rx_buf, dws->buffer_rx_dma, dws->cur_transfer->len);
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451 #if defined(PRINT_TRANS_DATA)
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453 printk_transfer_data(dws->cur_transfer->rx_buf, dws->cur_transfer->len);
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457 spin_unlock_irqrestore(&dws->lock, flags);
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459 /* If the other done */
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460 if (!(dws->state & TXBUSY))
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462 //complete(&dws->xfer_completion);
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463 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);
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464 //DMA could not lose intterupt
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465 transfer_complete(dws);
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470 static void rk29_spi_dma_txcb(void *buf_id,
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471 int size, enum rk29_dma_buffresult res)
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473 struct rk29xx_spi *dws = buf_id;
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474 unsigned long flags;
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476 DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);
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478 spin_lock_irqsave(&dws->lock, flags);
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480 if (res == RK29_RES_OK)
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481 dws->state &= ~TXBUSY;
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483 dev_err(&dws->master->dev, "error:DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);
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485 spin_unlock_irqrestore(&dws->lock, flags);
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487 /* If the other done */
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488 if (!(dws->state & RXBUSY))
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490 //complete(&dws->xfer_completion);
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492 DBG("func: %s, line: %d,dma transfer complete\n", __FUNCTION__, __LINE__);
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493 //DMA could not lose intterupt
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494 transfer_complete(dws);
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500 static struct rk29_dma_client rk29_spi_dma_client = {
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501 .name = "rk29xx-spi-dma",
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504 static int acquire_dma(struct rk29xx_spi *dws)
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506 if (dws->dma_inited) {
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510 dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);
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511 if (!dws->buffer_tx_dma)
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513 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");
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517 dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);
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518 if (!dws->buffer_rx_dma)
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520 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");
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524 if(rk29_dma_request(dws->rx_dmach,
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525 &rk29_spi_dma_client, NULL) < 0) {
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526 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);
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530 if (rk29_dma_request(dws->tx_dmach,
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531 &rk29_spi_dma_client, NULL) < 0) {
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532 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);
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533 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);
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538 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {
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539 dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");
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542 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,
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543 dws->sfr_start + SPIM_TXDR)) {
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544 dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");
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550 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {
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551 dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");
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554 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,
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555 dws->sfr_start + SPIM_RXDR)) {
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556 dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");
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561 dws->dma_inited = 1;
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565 static void release_dma(struct rk29xx_spi *dws)
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567 if(!dws && dws->dma_inited) {
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568 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);
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569 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);
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574 * Note: first step is the protocol driver prepares
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575 * a dma-capable memory, and this func just need translate
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576 * the virt addr to physical
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578 static int map_dma_buffers(struct rk29xx_spi *dws)
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580 if (!dws->dma_inited || !dws->cur_chip->enable_dma)
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582 printk("%s:error\n",__func__);
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586 if(dws->cur_transfer->tx_buf)
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588 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);
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591 dws->cur_transfer->tx_dma = dws->tx_dma;
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592 dws->cur_transfer->rx_dma = dws->rx_dma;
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597 /* Caller already set message->status; dma and pio irqs are blocked */
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598 static void giveback(struct rk29xx_spi *dws)
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600 struct spi_transfer *last_transfer;
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601 unsigned long flags;
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602 struct spi_message *msg;
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604 spin_lock_irqsave(&dws->lock, flags);
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605 msg = dws->cur_msg;
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606 dws->cur_msg = NULL;
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607 dws->cur_transfer = NULL;
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608 dws->prev_chip = dws->cur_chip;
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609 dws->cur_chip = NULL;
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610 dws->dma_mapped = 0;
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612 /*it is important to close intterrupt*/
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613 spi_mask_intr(dws, 0xff);
\r
614 rk29xx_writew(dws, SPIM_DMACR, 0);
\r
616 queue_work(dws->workqueue, &dws->pump_messages);
\r
617 spin_unlock_irqrestore(&dws->lock, flags);
\r
619 last_transfer = list_entry(msg->transfers.prev,
\r
620 struct spi_transfer,
\r
623 if (!last_transfer->cs_change && dws->cs_control)
\r
624 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);
\r
628 msg->complete(msg->context);
\r
630 DBG("%s ok\n",__func__);
\r
634 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)
\r
636 /* Stop and reset hw */
\r
638 spi_enable_chip(dws, 0);
\r
640 dev_err(&dws->master->dev, "%s\n", msg);
\r
641 dws->cur_msg->state = ERROR_STATE;
\r
642 tasklet_schedule(&dws->pump_transfers);
\r
645 static void transfer_complete(struct rk29xx_spi *dws)
\r
647 /* Update total byte transfered return count actual bytes read */
\r
648 dws->cur_msg->actual_length += dws->len;
\r
650 /* Move to next transfer */
\r
651 dws->cur_msg->state = next_transfer(dws);
\r
653 /* Handle end of message */
\r
654 if (dws->cur_msg->state == DONE_STATE) {
\r
655 dws->cur_msg->status = 0;
\r
658 tasklet_schedule(&dws->pump_transfers);
\r
661 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)
\r
663 u16 irq_status, irq_mask = 0x1f;
\r
664 u32 int_level = dws->fifo_len / 2;
\r
667 irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;
\r
668 /* Error handling */
\r
669 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
\r
670 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);
\r
671 int_error_stop(dws, "interrupt_transfer: fifo overrun");
\r
672 mutex_unlock(&dws->dma_lock);
\r
673 return IRQ_HANDLED;
\r
676 if (irq_status & SPI_INT_TXEI) {
\r
677 spi_mask_intr(dws, SPI_INT_TXEI);
\r
679 left = (dws->tx_end - dws->tx) / dws->n_bytes;
\r
680 left = (left > int_level) ? int_level : left;
\r
684 wait_till_not_busy(dws);
\r
690 /* Re-enable the IRQ if there is still data left to tx */
\r
691 if (dws->tx_end > dws->tx)
\r
692 spi_umask_intr(dws, SPI_INT_TXEI);
\r
694 transfer_complete(dws);
\r
697 if (irq_status & SPI_INT_RXFI) {
\r
698 spi_mask_intr(dws, SPI_INT_RXFI);
\r
702 /* Re-enable the IRQ if there is still data left to rx */
\r
703 if (dws->rx_end > dws->rx) {
\r
704 left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;
\r
705 left = (left > int_level) ? int_level : left;
\r
707 rk29xx_writew(dws, SPIM_RXFTLR, left);
\r
708 spi_umask_intr(dws, SPI_INT_RXFI);
\r
711 transfer_complete(dws);
\r
716 return IRQ_HANDLED;
\r
719 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)
\r
721 struct rk29xx_spi *dws = dev_id;
\r
723 if (!dws->cur_msg) {
\r
724 spi_mask_intr(dws, SPI_INT_TXEI);
\r
726 return IRQ_HANDLED;
\r
729 return dws->transfer_handler(dws);
\r
732 /* Must be called inside pump_transfers() */
\r
733 static void poll_transfer(struct rk29xx_spi *dws)
\r
735 #if defined(PRINT_TRANS_DATA)
\r
736 DBG("%s\n",__func__);
\r
738 while (dws->write(dws)) {
\r
739 wait_till_not_busy(dws);
\r
742 transfer_complete(dws);
\r
744 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)
\r
746 if(cs >= dws->master->num_chipselect)
\r
749 if (dws->cs_control){
\r
750 dws->cs_control(dws, cs, MRST_SPI_ASSERT);
\r
752 rk29xx_writel(dws, SPIM_SER, 1 << cs);
\r
755 static void pump_transfers(unsigned long data)
\r
757 struct rk29xx_spi *dws = (struct rk29xx_spi *)data;
\r
758 struct spi_message *message = NULL;
\r
759 struct spi_transfer *transfer = NULL;
\r
760 struct spi_transfer *previous = NULL;
\r
761 struct spi_device *spi = NULL;
\r
762 struct chip_data *chip = NULL;
\r
767 u16 txint_level = 0;
\r
768 u16 rxint_level = 0;
\r
773 if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){
\r
778 DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);
\r
780 /* Get current state information */
\r
781 message = dws->cur_msg;
\r
782 transfer = dws->cur_transfer;
\r
783 chip = dws->cur_chip;
\r
784 spi = message->spi;
\r
785 if (unlikely(!chip->clk_div))
\r
786 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
\r
787 if (message->state == ERROR_STATE) {
\r
788 message->status = -EIO;
\r
792 /* Handle end of message */
\r
793 if (message->state == DONE_STATE) {
\r
794 message->status = 0;
\r
798 /* Delay if requested at end of transfer*/
\r
799 if (message->state == RUNNING_STATE) {
\r
800 previous = list_entry(transfer->transfer_list.prev,
\r
801 struct spi_transfer,
\r
803 if (previous->delay_usecs)
\r
804 udelay(previous->delay_usecs);
\r
807 dws->n_bytes = chip->n_bytes;
\r
808 dws->dma_width = chip->dma_width;
\r
809 dws->cs_control = chip->cs_control;
\r
811 //dws->rx_dma = transfer->rx_dma;
\r
812 //dws->tx_dma = transfer->tx_dma;
\r
813 dws->tx = (void *)transfer->tx_buf;
\r
814 dws->tx_end = dws->tx + transfer->len;
\r
815 dws->rx = (void *)transfer->rx_buf;
\r
816 dws->rx_end = dws->rx + transfer->len;
\r
817 dws->write = dws->tx ? chip->write : null_writer;
\r
818 dws->read = dws->rx ? chip->read : null_reader;
\r
819 dws->cs_change = transfer->cs_change;
\r
820 dws->len = dws->cur_transfer->len;
\r
821 if (chip != dws->prev_chip)
\r
826 /* Handle per transfer options for bpw and speed */
\r
827 if (transfer->speed_hz) {
\r
828 speed = chip->speed_hz;
\r
830 if (transfer->speed_hz != speed) {
\r
831 speed = transfer->speed_hz;
\r
832 if (speed > clk_get_rate(dws->clock_spim)) {
\r
833 dev_err(&dws->master->dev, "MRST SPI0: unsupported "
\r
834 "freq: %dHz\n", speed);
\r
835 message->status = -EIO;
\r
839 /* clk_div doesn't support odd number */
\r
840 clk_div = clk_get_rate(dws->clock_spim) / speed;
\r
841 clk_div = (clk_div + 1) & 0xfffe;
\r
843 chip->speed_hz = speed;
\r
844 chip->clk_div = clk_div;
\r
848 if (transfer->bits_per_word) {
\r
849 bits = transfer->bits_per_word;
\r
854 dws->dma_width = 1;
\r
855 dws->read = (dws->read != null_reader) ?
\r
856 u8_reader : null_reader;
\r
857 dws->write = (dws->write != null_writer) ?
\r
858 u8_writer : null_writer;
\r
859 spi_dfs = SPI_DFS_8BIT;
\r
863 dws->dma_width = 2;
\r
864 dws->read = (dws->read != null_reader) ?
\r
865 u16_reader : null_reader;
\r
866 dws->write = (dws->write != null_writer) ?
\r
867 u16_writer : null_writer;
\r
868 spi_dfs = SPI_DFS_16BIT;
\r
871 dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
\r
873 message->status = -EIO;
\r
877 cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
878 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
\r
879 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
\r
880 | (chip->type << SPI_FRF_OFFSET)
\r
881 | (spi->mode << SPI_MODE_OFFSET)
\r
882 | (chip->tmode << SPI_TMOD_OFFSET);
\r
884 message->state = RUNNING_STATE;
\r
887 * Adjust transfer mode if necessary. Requires platform dependent
\r
888 * chipselect mechanism.
\r
890 if (dws->cs_control) {
\r
891 if (dws->rx && dws->tx)
\r
892 chip->tmode = SPI_TMOD_TR;
\r
894 chip->tmode = SPI_TMOD_RO;
\r
896 chip->tmode = SPI_TMOD_TO;
\r
898 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
\r
899 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);
\r
900 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
\r
905 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
\r
907 if (!dws->dma_mapped && !chip->poll_mode) {
\r
910 if (chip->tmode == SPI_TMOD_RO) {
\r
911 templen = dws->len / dws->n_bytes - 1;
\r
912 rxint_level = dws->fifo_len / 2;
\r
913 rxint_level = (templen > rxint_level) ? rxint_level : templen;
\r
914 imask |= SPI_INT_RXFI;
\r
917 templen = dws->len / dws->n_bytes;
\r
918 txint_level = dws->fifo_len / 2;
\r
919 txint_level = (templen > txint_level) ? txint_level : templen;
\r
920 imask |= SPI_INT_TXEI;
\r
922 dws->transfer_handler = interrupt_transfer;
\r
926 * Reprogram registers only if
\r
927 * 1. chip select changes
\r
928 * 2. clk_div is changed
\r
929 * 3. control value changes
\r
931 if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div || imask) {
\r
932 spi_enable_chip(dws, 0);
\r
933 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)
\r
934 rk29xx_writel(dws, SPIM_CTRLR0, cr0);
\r
936 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
\r
937 spi_chip_sel(dws, spi->chip_select);
\r
939 rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);
\r
940 spi_enable_chip(dws, 1);
\r
943 rk29xx_writew(dws, SPIM_TXFTLR, txint_level);
\r
945 rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);
\r
946 /* Set the interrupt mask, for poll mode just diable all int */
\r
947 spi_mask_intr(dws, 0xff);
\r
949 spi_umask_intr(dws, imask);
\r
952 dws->prev_chip = chip;
\r
955 if (chip->poll_mode)
\r
956 poll_transfer(dws);
\r
965 static void dma_transfer(struct rk29xx_spi *dws)
\r
967 struct spi_message *message = NULL;
\r
968 struct spi_transfer *transfer = NULL;
\r
969 struct spi_transfer *previous = NULL;
\r
970 struct spi_device *spi = NULL;
\r
971 struct chip_data *chip = NULL;
\r
972 //unsigned long val;
\r
973 //unsigned long flags;
\r
985 DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);
\r
987 if (acquire_dma(dws)) {
\r
988 dev_err(&dws->master->dev, "acquire dma failed\n");
\r
992 if (map_dma_buffers(dws)) {
\r
993 dev_err(&dws->master->dev, "acquire dma failed\n");
\r
997 /* Get current state information */
\r
998 message = dws->cur_msg;
\r
999 transfer = dws->cur_transfer;
\r
1000 chip = dws->cur_chip;
\r
1001 spi = message->spi;
\r
1002 if (unlikely(!chip->clk_div))
\r
1003 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
\r
1004 if (message->state == ERROR_STATE) {
\r
1005 message->status = -EIO;
\r
1009 /* Handle end of message */
\r
1010 if (message->state == DONE_STATE) {
\r
1011 message->status = 0;
\r
1015 /* Delay if requested at end of transfer*/
\r
1016 if (message->state == RUNNING_STATE) {
\r
1017 previous = list_entry(transfer->transfer_list.prev,
\r
1018 struct spi_transfer,
\r
1020 if (previous->delay_usecs)
\r
1021 udelay(previous->delay_usecs);
\r
1024 dws->n_bytes = chip->n_bytes;
\r
1025 dws->dma_width = chip->dma_width;
\r
1026 dws->cs_control = chip->cs_control;
\r
1028 //dws->rx_dma = transfer->rx_dma;
\r
1029 //dws->tx_dma = transfer->tx_dma;
\r
1030 dws->tx = (void *)transfer->tx_buf;
\r
1031 dws->tx_end = dws->tx + transfer->len;
\r
1032 dws->rx = (void *)transfer->rx_buf;
\r
1033 dws->rx_end = dws->rx + transfer->len;
\r
1034 dws->write = dws->tx ? chip->write : null_writer;
\r
1035 dws->read = dws->rx ? chip->read : null_reader;
\r
1036 dws->cs_change = transfer->cs_change;
\r
1037 dws->len = dws->cur_transfer->len;
\r
1038 if (chip != dws->prev_chip)
\r
1043 /* Handle per transfer options for bpw and speed */
\r
1044 if (transfer->speed_hz) {
\r
1045 speed = chip->speed_hz;
\r
1046 if (transfer->speed_hz != speed) {
\r
1047 speed = transfer->speed_hz;
\r
1048 if (speed > clk_get_rate(dws->clock_spim)) {
\r
1049 dev_err(&dws->master->dev, "MRST SPI0: unsupported "
\r
1050 "freq: %dHz\n", speed);
\r
1051 message->status = -EIO;
\r
1055 /* clk_div doesn't support odd number */
\r
1056 clk_div = clk_get_rate(dws->clock_spim) / speed;
\r
1057 clk_div = (clk_div + 1) & 0xfffe;
\r
1059 chip->speed_hz = speed;
\r
1060 chip->clk_div = clk_div;
\r
1065 if (transfer->bits_per_word) {
\r
1066 bits = transfer->bits_per_word;
\r
1071 dws->dma_width = 1;
\r
1072 spi_dfs = SPI_DFS_8BIT;
\r
1076 dws->dma_width = 2;
\r
1077 spi_dfs = SPI_DFS_16BIT;
\r
1080 dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
\r
1082 message->status = -EIO;
\r
1086 cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
1087 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
\r
1088 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
\r
1089 | (chip->type << SPI_FRF_OFFSET)
\r
1090 | (spi->mode << SPI_MODE_OFFSET)
\r
1091 | (chip->tmode << SPI_TMOD_OFFSET);
\r
1093 message->state = RUNNING_STATE;
\r
1096 * Adjust transfer mode if necessary. Requires platform dependent
\r
1097 * chipselect mechanism.
\r
1099 if (dws->cs_control) {
\r
1100 if (dws->rx && dws->tx)
\r
1101 chip->tmode = SPI_TMOD_TR;
\r
1103 chip->tmode = SPI_TMOD_RO;
\r
1105 chip->tmode = SPI_TMOD_TO;
\r
1107 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
\r
1108 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);
\r
1109 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
\r
1113 * Reprogram registers only if
\r
1114 * 1. chip select changes
\r
1115 * 2. clk_div is changed
\r
1116 * 3. control value changes
\r
1118 if ((rk29xx_readl(dws, SPIM_CTRLR0) != cr0) || cs_change || clk_div) {
\r
1119 spi_enable_chip(dws, 0);
\r
1120 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0) {
\r
1121 rk29xx_writel(dws, SPIM_CTRLR0, cr0);
\r
1123 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
\r
1124 spi_chip_sel(dws, spi->chip_select);
\r
1125 /* Set the interrupt mask, for poll mode just diable all int */
\r
1126 spi_mask_intr(dws, 0xff);
\r
1128 if (transfer->tx_buf != NULL) {
\r
1129 dmacr |= SPI_DMACR_TX_ENABLE;
\r
1130 rk29xx_writew(dws, SPIM_DMATDLR, 0);
\r
1132 if (transfer->rx_buf != NULL) {
\r
1133 dmacr |= SPI_DMACR_RX_ENABLE;
\r
1134 rk29xx_writew(dws, SPIM_DMARDLR, 0);
\r
1135 rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);
\r
1137 rk29xx_writew(dws, SPIM_DMACR, dmacr);
\r
1138 spi_enable_chip(dws, 1);
\r
1140 dws->prev_chip = chip;
\r
1143 //INIT_COMPLETION(dws->xfer_completion);
\r
1145 //spi_dump_regs(dws);
\r
1147 DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, dws->tx_dma: 0x%x,dws->rx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)dws->tx_dma,(unsigned int)dws->rx_dma);
\r
1148 DBG("dws->buffer_tx_dma: 0x%p, dws->buffer_rx_dma: 0x%p,dws->dma_width=%d\n", dws->buffer_tx_dma, dws->buffer_rx_dma,dws->dma_width);
\r
1150 if (transfer->tx_buf != NULL)
\r
1151 dws->state |= TXBUSY;
\r
1152 if (transfer->rx_buf != NULL)
\r
1153 dws->state |= RXBUSY;
\r
1155 if (transfer->tx_buf != NULL) {
\r
1156 DBG("%s:start dma tx,dws->state=0x%x\n",__func__,dws->state);
\r
1157 #if defined(PRINT_TRANS_DATA)
\r
1158 printk("dma tx:");
\r
1159 printk_transfer_data(dws->buffer_tx_dma, dws->cur_transfer->len);
\r
1161 /*if (transfer->len & 0x3) {
\r
1167 if (rk29_dma_config(dws->tx_dmach, burst)) {*/
\r
1168 if (rk29_dma_config(dws->tx_dmach, dws->dma_width, 1)) {//there is not dma burst but bitwide, set it 1 alwayss
\r
1169 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1173 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH);
\r
1175 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,
\r
1176 dws->tx_dma, transfer->len);
\r
1178 dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet,
\r
1179 dws->tx_dmach, (unsigned int)transfer->tx_dma);
\r
1183 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {
\r
1184 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1189 //wait_till_not_busy(dws);
\r
1191 if (transfer->rx_buf != NULL) {
\r
1192 DBG("%s:start dma rx,dws->state=0x%x\n",__func__,dws->state);
\r
1193 if (rk29_dma_config(dws->rx_dmach, dws->dma_width, 1)) {
\r
1194 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1198 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH);
\r
1200 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,
\r
1201 dws->rx_dma, transfer->len);
\r
1203 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1207 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {
\r
1208 dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
\r
1213 //wait_till_not_busy(dws);
\r
1223 static void pump_messages(struct work_struct *work)
\r
1225 struct rk29xx_spi *dws =
\r
1226 container_of(work, struct rk29xx_spi, pump_messages);
\r
1227 unsigned long flags;
\r
1229 DBG(KERN_INFO "pump_messages,line=%d\n",__LINE__);
\r
1231 /* Lock queue and check for queue work */
\r
1232 spin_lock_irqsave(&dws->lock, flags);
\r
1233 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
\r
1235 spin_unlock_irqrestore(&dws->lock, flags);
\r
1236 DBG("%s:line=%d,list_empty\n",__func__,__LINE__);
\r
1240 /* Make sure we are not already running a message */
\r
1241 if (dws->cur_msg) {
\r
1242 spin_unlock_irqrestore(&dws->lock, flags);
\r
1243 DBG("%s:line=%d,dws->cur_msg\n",__func__,__LINE__);
\r
1247 /* Extract head of queue */
\r
1248 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
\r
1249 list_del_init(&dws->cur_msg->queue);
\r
1251 /* Initial message state*/
\r
1252 dws->cur_msg->state = START_STATE;
\r
1253 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
\r
1254 struct spi_transfer,
\r
1256 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
\r
1257 dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj
\r
1260 /* Mark as busy and launch transfers */
\r
1261 tasklet_schedule(&dws->pump_transfers);
\r
1263 spin_unlock_irqrestore(&dws->lock, flags);
\r
1267 #if defined(QUICK_TRANSFER)
\r
1268 static void do_read(struct rk29xx_spi *dws)
\r
1272 spi_enable_chip(dws, 0);
\r
1273 rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);
\r
1274 spi_enable_chip(dws, 1);
\r
1275 rk29xx_writew(dws, SPIM_TXDR, 0);
\r
1277 if (dws->read(dws))
\r
1279 if (count++ == 0x20) {
\r
1280 dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");
\r
1287 static void do_write(struct rk29xx_spi *dws)
\r
1289 while (dws->tx<dws->tx_end) {
\r
1294 /* Caller already set message->status; dma and pio irqs are blocked */
\r
1295 static void msg_giveback(struct rk29xx_spi *dws)
\r
1297 struct spi_transfer *last_transfer;
\r
1298 struct spi_message *msg;
\r
1300 DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1302 msg = dws->cur_msg;
\r
1303 dws->cur_msg = NULL;
\r
1304 dws->cur_transfer = NULL;
\r
1305 dws->prev_chip = dws->cur_chip;
\r
1306 dws->cur_chip = NULL;
\r
1307 dws->dma_mapped = 0;
\r
1310 last_transfer = list_entry(msg->transfers.prev,
\r
1311 struct spi_transfer,
\r
1314 if (!last_transfer->cs_change && dws->cs_control)
\r
1315 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);
\r
1317 msg->state = NULL;
\r
1320 /* Must be called inside pump_transfers() */
\r
1321 static int do_full_transfer(struct rk29xx_spi *dws)
\r
1323 if ((dws->read(dws))) {
\r
1327 while (dws->tx<dws->tx_end){
\r
1332 if (dws->rx < dws->rx_end) {
\r
1338 dws->cur_msg->actual_length += dws->len;
\r
1340 /* Move to next transfer */
\r
1341 dws->cur_msg->state = next_transfer(dws);
\r
1343 if (dws->cur_msg->state == DONE_STATE) {
\r
1344 dws->cur_msg->status = 0;
\r
1345 //msg_giveback(dws);
\r
1355 /* Must be called inside pump_transfers() */
\r
1356 static int do_half_transfer(struct rk29xx_spi *dws)
\r
1362 wait_till_tf_empty(dws);
\r
1363 wait_till_not_busy(dws);
\r
1368 wait_till_tf_empty(dws);
\r
1369 wait_till_not_busy(dws);
\r
1372 dws->cur_msg->actual_length += dws->len;
\r
1374 /* Move to next transfer */
\r
1375 dws->cur_msg->state = next_transfer(dws);
\r
1377 if (dws->cur_msg->state == DONE_STATE) {
\r
1378 dws->cur_msg->status = 0;
\r
1379 //msg_giveback(dws);
\r
1388 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)
\r
1390 struct spi_message *message = NULL;
\r
1391 struct spi_transfer *transfer = NULL;
\r
1392 struct spi_transfer *previous = NULL;
\r
1393 struct spi_device *spi = NULL;
\r
1394 struct chip_data *chip = NULL;
\r
1403 DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1405 /* Get current state information */
\r
1406 message = dws->cur_msg;
\r
1407 transfer = dws->cur_transfer;
\r
1408 chip = dws->cur_chip;
\r
1409 spi = message->spi;
\r
1411 if (unlikely(!chip->clk_div))
\r
1412 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
\r
1413 if (message->state == ERROR_STATE) {
\r
1414 message->status = -EIO;
\r
1418 /* Handle end of message */
\r
1419 if (message->state == DONE_STATE) {
\r
1420 message->status = 0;
\r
1424 /* Delay if requested at end of transfer*/
\r
1425 if (message->state == RUNNING_STATE) {
\r
1426 previous = list_entry(transfer->transfer_list.prev,
\r
1427 struct spi_transfer,
\r
1429 if (previous->delay_usecs)
\r
1430 udelay(previous->delay_usecs);
\r
1433 dws->n_bytes = chip->n_bytes;
\r
1434 dws->dma_width = chip->dma_width;
\r
1435 dws->cs_control = chip->cs_control;
\r
1437 dws->rx_dma = transfer->rx_dma;
\r
1438 dws->tx_dma = transfer->tx_dma;
\r
1439 dws->tx = (void *)transfer->tx_buf;
\r
1440 dws->tx_end = dws->tx + transfer->len;
\r
1441 dws->rx = transfer->rx_buf;
\r
1442 dws->rx_end = dws->rx + transfer->len;
\r
1443 dws->write = dws->tx ? chip->write : null_writer;
\r
1444 dws->read = dws->rx ? chip->read : null_reader;
\r
1445 if (dws->rx && dws->tx) {
\r
1446 int temp_len = transfer->len;
\r
1448 unsigned char *tx_buf;
\r
1449 for (len=0; *tx_buf++ != 0; len++);
\r
1450 dws->tx_end = dws->tx + len;
\r
1451 dws->rx_end = dws->rx + temp_len - len;
\r
1453 dws->cs_change = transfer->cs_change;
\r
1454 dws->len = dws->cur_transfer->len;
\r
1455 if (chip != dws->prev_chip)
\r
1460 /* Handle per transfer options for bpw and speed */
\r
1461 if (transfer->speed_hz) {
\r
1462 speed = chip->speed_hz;
\r
1464 if (transfer->speed_hz != speed) {
\r
1465 speed = transfer->speed_hz;
\r
1466 if (speed > clk_get_rate(dws->clock_spim)) {
\r
1467 dev_err(&dws->master->dev, "MRST SPI0: unsupported"
\r
1468 "freq: %dHz\n", speed);
\r
1469 message->status = -EIO;
\r
1473 /* clk_div doesn't support odd number */
\r
1474 clk_div = clk_get_rate(dws->clock_spim) / speed;
\r
1475 clk_div = (clk_div + 1) & 0xfffe;
\r
1477 chip->speed_hz = speed;
\r
1478 chip->clk_div = clk_div;
\r
1481 if (transfer->bits_per_word) {
\r
1482 bits = transfer->bits_per_word;
\r
1487 dws->dma_width = 1;
\r
1488 dws->read = (dws->read != null_reader) ?
\r
1489 u8_reader : null_reader;
\r
1490 dws->write = (dws->write != null_writer) ?
\r
1491 u8_writer : null_writer;
\r
1492 spi_dfs = SPI_DFS_8BIT;
\r
1496 dws->dma_width = 2;
\r
1497 dws->read = (dws->read != null_reader) ?
\r
1498 u16_reader : null_reader;
\r
1499 dws->write = (dws->write != null_writer) ?
\r
1500 u16_writer : null_writer;
\r
1501 spi_dfs = SPI_DFS_16BIT;
\r
1504 dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
\r
1506 message->status = -EIO;
\r
1510 cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
1511 | (chip->type << SPI_FRF_OFFSET)
\r
1512 | (spi->mode << SPI_MODE_OFFSET)
\r
1513 | (chip->tmode << SPI_TMOD_OFFSET);
\r
1515 message->state = RUNNING_STATE;
\r
1518 * Adjust transfer mode if necessary. Requires platform dependent
\r
1519 * chipselect mechanism.
\r
1521 if (dws->cs_control) {
\r
1522 if (dws->rx && dws->tx)
\r
1523 chip->tmode = SPI_TMOD_TR;
\r
1525 chip->tmode = SPI_TMOD_RO;
\r
1527 chip->tmode = SPI_TMOD_TO;
\r
1529 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
\r
1530 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
\r
1533 /* Check if current transfer is a DMA transaction */
\r
1534 dws->dma_mapped = map_dma_buffers(dws);
\r
1537 * Reprogram registers only if
\r
1538 * 1. chip select changes
\r
1539 * 2. clk_div is changed
\r
1540 * 3. control value changes
\r
1542 spi_enable_chip(dws, 0);
\r
1543 if (rk29xx_readl(dws, SPIM_CTRLR0) != cr0)
\r
1544 rk29xx_writel(dws, SPIM_CTRLR0, cr0);
\r
1546 DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);
\r
1547 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
\r
1548 spi_chip_sel(dws, spi->chip_select);
\r
1549 rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx
\r
1550 if(dws->dma_mapped ) {
\r
1551 dmacr = rk29xx_readw(dws, SPIM_DMACR);
\r
1552 dmacr = dmacr | SPI_DMACR_TX_ENABLE;
\r
1554 dmacr = dmacr | SPI_DMACR_RX_ENABLE;
\r
1555 rk29xx_writew(dws, SPIM_DMACR, dmacr);
\r
1557 spi_enable_chip(dws, 1);
\r
1559 dws->prev_chip = chip;
\r
1562 return do_full_transfer(dws);
\r
1564 return do_half_transfer(dws);
\r
1568 //msg_giveback(dws);
\r
1573 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)
\r
1575 DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1577 while (!acquire_dma(dws))
\r
1580 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
\r
1585 /* Make sure we are not already running a message */
\r
1586 if (dws->cur_msg) {
\r
1590 /* Extract head of queue */
\r
1591 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
\r
1592 list_del_init(&dws->cur_msg->queue);
\r
1594 /* Initial message state*/
\r
1595 dws->cur_msg->state = START_STATE;
\r
1596 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
\r
1597 struct spi_transfer,
\r
1599 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
\r
1600 dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj
\r
1602 /* Mark as busy and launch transfers */
\r
1605 while (rk29xx_pump_transfers(dws, mode)) ;
\r
1608 /* spi_device use this to queue in their spi_msg */
\r
1609 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)
\r
1611 struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);
\r
1612 unsigned long flags;
\r
1613 struct rk29xx_spi_chip *chip_info = spi->controller_data;
\r
1614 struct spi_message *mmsg;
\r
1616 DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);
\r
1618 spin_lock_irqsave(&dws->lock, flags);
\r
1620 if (dws->run == QUEUE_STOPPED) {
\r
1621 spin_unlock_irqrestore(&dws->lock, flags);
\r
1622 return -ESHUTDOWN;
\r
1625 msg->actual_length = 0;
\r
1626 msg->status = -EINPROGRESS;
\r
1627 msg->state = START_STATE;
\r
1629 list_add_tail(&msg->queue, &dws->queue);
\r
1631 if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {
\r
1632 rk29xx_pump_messages(dws,1);
\r
1635 rk29xx_pump_messages(dws,0);
\r
1638 mmsg = dws->cur_msg;
\r
1639 msg_giveback(dws);
\r
1641 spin_unlock_irqrestore(&dws->lock, flags);
\r
1643 if (mmsg->complete)
\r
1644 mmsg->complete(mmsg->context);
\r
1651 /* spi_device use this to queue in their spi_msg */
\r
1652 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
\r
1654 struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);
\r
1655 unsigned long flags;
\r
1657 spin_lock_irqsave(&dws->lock, flags);
\r
1659 if (dws->run == QUEUE_STOPPED) {
\r
1660 spin_unlock_irqrestore(&dws->lock, flags);
\r
1661 return -ESHUTDOWN;
\r
1664 msg->actual_length = 0;
\r
1665 msg->status = -EINPROGRESS;
\r
1666 msg->state = START_STATE;
\r
1668 list_add_tail(&msg->queue, &dws->queue);
\r
1670 if (dws->run == QUEUE_RUNNING && !dws->busy) {
\r
1672 if (dws->cur_transfer || dws->cur_msg)
\r
1673 queue_work(dws->workqueue,
\r
1674 &dws->pump_messages);
\r
1676 /* If no other data transaction in air, just go */
\r
1677 spin_unlock_irqrestore(&dws->lock, flags);
\r
1678 pump_messages(&dws->pump_messages);
\r
1683 spin_unlock_irqrestore(&dws->lock, flags);
\r
1690 /* This may be called twice for each spi dev */
\r
1691 static int rk29xx_spi_setup(struct spi_device *spi)
\r
1693 struct rk29xx_spi_chip *chip_info = NULL;
\r
1694 struct chip_data *chip;
\r
1697 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
\r
1700 /* Only alloc on first setup */
\r
1701 chip = spi_get_ctldata(spi);
\r
1703 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
\r
1707 chip->cs_control = spi_cs_control;
\r
1708 chip->enable_dma = 0; //0;
\r
1712 * Protocol drivers may change the chip settings, so...
\r
1713 * if chip_info exists, use it
\r
1715 chip_info = spi->controller_data;
\r
1717 /* chip_info doesn't always exist */
\r
1719 if (chip_info->cs_control)
\r
1720 chip->cs_control = chip_info->cs_control;
\r
1722 chip->poll_mode = chip_info->poll_mode;
\r
1723 chip->type = chip_info->type;
\r
1725 chip->rx_threshold = 0;
\r
1726 chip->tx_threshold = 0;
\r
1728 chip->enable_dma = chip_info->enable_dma;
\r
1731 if (spi->bits_per_word == 8) {
\r
1732 chip->n_bytes = 1;
\r
1733 chip->dma_width = 1;
\r
1734 chip->read = u8_reader;
\r
1735 chip->write = u8_writer;
\r
1736 spi_dfs = SPI_DFS_8BIT;
\r
1737 } else if (spi->bits_per_word == 16) {
\r
1738 chip->n_bytes = 2;
\r
1739 chip->dma_width = 2;
\r
1740 chip->read = u16_reader;
\r
1741 chip->write = u16_writer;
\r
1742 spi_dfs = SPI_DFS_16BIT;
\r
1744 /* Never take >16b case for MRST SPIC */
\r
1745 dev_err(&spi->dev, "invalid wordsize\n");
\r
1748 chip->bits_per_word = spi->bits_per_word;
\r
1750 if (!spi->max_speed_hz) {
\r
1751 dev_err(&spi->dev, "No max speed HZ parameter\n");
\r
1754 chip->speed_hz = spi->max_speed_hz;
\r
1756 chip->tmode = 0; /* Tx & Rx */
\r
1757 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
\r
1758 chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)
\r
1759 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
\r
1760 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
\r
1761 | (chip->type << SPI_FRF_OFFSET)
\r
1762 | (spi->mode << SPI_MODE_OFFSET)
\r
1763 | (chip->tmode << SPI_TMOD_OFFSET);
\r
1765 spi_set_ctldata(spi, chip);
\r
1769 static void rk29xx_spi_cleanup(struct spi_device *spi)
\r
1771 struct chip_data *chip = spi_get_ctldata(spi);
\r
1775 static int __devinit init_queue(struct rk29xx_spi *dws)
\r
1777 INIT_LIST_HEAD(&dws->queue);
\r
1778 spin_lock_init(&dws->lock);
\r
1780 dws->run = QUEUE_STOPPED;
\r
1783 init_completion(&dws->xfer_completion);
\r
1785 tasklet_init(&dws->pump_transfers,
\r
1786 pump_transfers, (unsigned long)dws);
\r
1788 INIT_WORK(&dws->pump_messages, pump_messages);
\r
1789 dws->workqueue = create_singlethread_workqueue(
\r
1790 dev_name(dws->master->dev.parent));
\r
1791 if (dws->workqueue == NULL)
\r
1798 static int start_queue(struct rk29xx_spi *dws)
\r
1800 unsigned long flags;
\r
1802 spin_lock_irqsave(&dws->lock, flags);
\r
1804 if (dws->run == QUEUE_RUNNING || dws->busy) {
\r
1805 spin_unlock_irqrestore(&dws->lock, flags);
\r
1809 dws->run = QUEUE_RUNNING;
\r
1810 dws->cur_msg = NULL;
\r
1811 dws->cur_transfer = NULL;
\r
1812 dws->cur_chip = NULL;
\r
1813 dws->prev_chip = NULL;
\r
1814 spin_unlock_irqrestore(&dws->lock, flags);
\r
1816 queue_work(dws->workqueue, &dws->pump_messages);
\r
1821 static int stop_queue(struct rk29xx_spi *dws)
\r
1823 unsigned long flags;
\r
1824 unsigned limit = 50;
\r
1827 spin_lock_irqsave(&dws->lock, flags);
\r
1828 dws->run = QUEUE_STOPPED;
\r
1829 while (!list_empty(&dws->queue) && dws->busy && limit--) {
\r
1830 spin_unlock_irqrestore(&dws->lock, flags);
\r
1832 spin_lock_irqsave(&dws->lock, flags);
\r
1835 if (!list_empty(&dws->queue) || dws->busy)
\r
1837 spin_unlock_irqrestore(&dws->lock, flags);
\r
1842 static int destroy_queue(struct rk29xx_spi *dws)
\r
1846 status = stop_queue(dws);
\r
1849 destroy_workqueue(dws->workqueue);
\r
1853 /* Restart the controller, disable all interrupts, clean rx fifo */
\r
1854 static void spi_hw_init(struct rk29xx_spi *dws)
\r
1856 spi_enable_chip(dws, 0);
\r
1857 spi_mask_intr(dws, 0xff);
\r
1860 * Try to detect the FIFO depth if not set by interface driver,
\r
1861 * the depth could be from 2 to 32 from HW spec
\r
1863 if (!dws->fifo_len) {
\r
1865 for (fifo = 2; fifo <= 31; fifo++) {
\r
1866 rk29xx_writew(dws, SPIM_TXFTLR, fifo);
\r
1867 if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))
\r
1871 dws->fifo_len = (fifo == 31) ? 0 : fifo;
\r
1872 rk29xx_writew(dws, SPIM_TXFTLR, 0);
\r
1875 spi_enable_chip(dws, 1);
\r
1879 /* cpufreq driver support */
\r
1880 #ifdef CONFIG_CPU_FREQ
\r
1882 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)
\r
1884 struct rk29xx_spi *info;
\r
1885 unsigned long newclk;
\r
1887 info = container_of(nb, struct rk29xx_spi, freq_transition);
\r
1888 newclk = clk_get_rate(info->clock_spim);
\r
1893 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)
\r
1895 info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;
\r
1897 return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
\r
1900 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)
\r
1902 cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
\r
1906 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)
\r
1911 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)
\r
1915 static int __init rk29xx_spim_probe(struct platform_device *pdev)
\r
1917 struct resource *regs, *dmatx_res, *dmarx_res;
\r
1918 struct rk29xx_spi *dws;
\r
1919 struct spi_master *master;
\r
1922 struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;
\r
1924 if (pdata && pdata->io_init) {
\r
1925 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);
\r
1931 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1934 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
\r
1935 if (dmatx_res == NULL) {
\r
1936 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
\r
1940 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
\r
1941 if (dmarx_res == NULL) {
\r
1942 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
\r
1945 irq = platform_get_irq(pdev, 0);
\r
1948 /* setup spi core then atmel-specific driver state */
\r
1950 master = spi_alloc_master(&pdev->dev, sizeof *dws);
\r
1956 platform_set_drvdata(pdev, master);
\r
1957 dws = spi_master_get_devdata(master);
\r
1958 dws->clock_spim = clk_get(&pdev->dev, "spi");
\r
1959 clk_enable(dws->clock_spim);
\r
1960 if (IS_ERR(dws->clock_spim)) {
\r
1961 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);
\r
1962 return PTR_ERR(dws->clock_spim);
\r
1965 dws->pclk = clk_get(&pdev->dev, "pclk_spi");
\r
1966 clk_enable(dws->pclk);
\r
1968 mutex_init(&dws->dma_lock);
\r
1970 dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
\r
1972 release_mem_region(regs->start, (regs->end - regs->start) + 1);
\r
1975 DBG(KERN_INFO "dws->regs: %p\n", dws->regs);
\r
1977 dws->irq_polarity = IRQF_TRIGGER_NONE;
\r
1978 dws->master = master;
\r
1979 dws->type = SSI_MOTO_SPI;
\r
1980 dws->prev_chip = NULL;
\r
1981 dws->sfr_start = regs->start;
\r
1982 dws->tx_dmach = dmatx_res->start;
\r
1983 dws->rx_dmach = dmarx_res->start;
\r
1984 dws->dma_inited = 0; ///0;
\r
1985 ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
\r
1986 ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,
\r
1987 "rk29xx_spim", dws);
\r
1989 dev_err(&master->dev, "can not get IRQ\n");
\r
1990 goto err_free_master;
\r
1993 master->mode_bits = SPI_CPOL | SPI_CPHA;
\r
1994 master->bus_num = pdev->id;
\r
1995 master->num_chipselect = pdata->num_chipselect;
\r
1996 master->dev.platform_data = pdata;
\r
1997 master->cleanup = rk29xx_spi_cleanup;
\r
1998 master->setup = rk29xx_spi_setup;
\r
1999 #if defined(QUICK_TRANSFER)
\r
2000 master->transfer = rk29xx_spi_quick_transfer;
\r
2002 master->transfer = rk29xx_spi_transfer;
\r
2006 /* Basic HW init */
\r
2009 /* Initial and start queue */
\r
2010 ret = init_queue(dws);
\r
2012 dev_err(&master->dev, "problem initializing queue\n");
\r
2013 goto err_diable_hw;
\r
2016 ret = start_queue(dws);
\r
2018 dev_err(&master->dev, "problem starting queue\n");
\r
2019 goto err_diable_hw;
\r
2022 spi_master_set_devdata(master, dws);
\r
2023 ret = spi_register_master(master);
\r
2025 dev_err(&master->dev, "problem registering spi master\n");
\r
2026 goto err_queue_alloc;
\r
2029 ret =rk29xx_spim_cpufreq_register(dws);
\r
2031 dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");
\r
2032 goto err_queue_alloc;
\r
2034 printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);
\r
2035 mrst_spi_debugfs_init(dws);
\r
2039 destroy_queue(dws);
\r
2041 spi_enable_chip(dws, 0);
\r
2042 free_irq(dws->irq, dws);
\r
2044 spi_master_put(master);
\r
2045 iounmap(dws->regs);
\r
2050 static void __exit rk29xx_spim_remove(struct platform_device *pdev)
\r
2052 struct spi_master *master = platform_get_drvdata(pdev);
\r
2053 struct rk29xx_spi *dws = spi_master_get_devdata(master);
\r
2058 rk29xx_spim_cpufreq_deregister(dws);
\r
2059 mrst_spi_debugfs_remove(dws);
\r
2061 if(dws->buffer_tx_dma)
\r
2062 dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);
\r
2063 if(dws->buffer_rx_dma)
\r
2064 dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);
\r
2067 /* Remove the queue */
\r
2068 status = destroy_queue(dws);
\r
2070 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "
\r
2071 "complete, message memory not freed\n");
\r
2073 clk_disable(dws->clock_spim);
\r
2074 clk_put(dws->clock_spim);
\r
2075 clk_disable(dws->pclk);
\r
2076 clk_put(dws->pclk);
\r
2077 spi_enable_chip(dws, 0);
\r
2079 spi_set_clk(dws, 0);
\r
2080 free_irq(dws->irq, dws);
\r
2082 /* Disconnect from the SPI framework */
\r
2083 spi_unregister_master(dws->master);
\r
2084 iounmap(dws->regs);
\r
2090 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)
\r
2092 struct spi_master *master = platform_get_drvdata(pdev);
\r
2093 struct rk29xx_spi *dws = spi_master_get_devdata(master);
\r
2094 struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;
\r
2098 status = stop_queue(dws);
\r
2101 clk_disable(dws->clock_spim);
\r
2102 if (pdata && pdata->io_fix_leakage_bug)
\r
2104 pdata->io_fix_leakage_bug( );
\r
2106 clk_disable(dws->pclk);
\r
2110 static int rk29xx_spim_resume(struct platform_device *pdev)
\r
2112 struct spi_master *master = platform_get_drvdata(pdev);
\r
2113 struct rk29xx_spi *dws = spi_master_get_devdata(master);
\r
2114 struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;
\r
2117 clk_enable(dws->pclk);
\r
2118 clk_enable(dws->clock_spim);
\r
2120 ret = start_queue(dws);
\r
2122 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
\r
2123 if (pdata && pdata->io_resume_leakage_bug)
\r
2125 pdata->io_resume_leakage_bug( );
\r
2131 #define rk29xx_spim_suspend NULL
\r
2132 #define rk29xx_spim_resume NULL
\r
2135 static struct platform_driver rk29xx_platform_spim_driver = {
\r
2136 .remove = __exit_p(rk29xx_spim_remove),
\r
2138 .name = "rk29xx_spim",
\r
2139 .owner = THIS_MODULE,
\r
2141 .suspend = rk29xx_spim_suspend,
\r
2142 .resume = rk29xx_spim_resume,
\r
2145 static int __init rk29xx_spim_init(void)
\r
2148 ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);
\r
2152 static void __exit rk29xx_spim_exit(void)
\r
2154 platform_driver_unregister(&rk29xx_platform_spim_driver);
\r
2157 arch_initcall_sync(rk29xx_spim_init);
\r
2158 module_exit(rk29xx_spim_exit);
\r
2160 MODULE_AUTHOR("www.rock-chips.com");
\r
2161 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");
\r
2162 MODULE_LICENSE("GPL");;
\r