drivers/spi/rk29_spim.c

   1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device \r
   2  *\r
   3  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   4  *\r
   5  * This software is licensed under the terms of the GNU General Public\r
   6  * License version 2, as published by the Free Software Foundation, and\r
   7  * may be copied, distributed, and modified under those terms.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful,\r
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  12  * GNU General Public License for more details.\r
  13  */\r
  14 \r
  15 #include <linux/dma-mapping.h>\r
  16 #include <linux/interrupt.h>\r
  17 #include <linux/highmem.h>\r
  18 #include <linux/delay.h>\r
  19 #include <linux/slab.h>\r
  20 #include <linux/platform_device.h>\r
  21 #include <linux/clk.h>\r
  22 #include <linux/cpufreq.h>\r
  23 #include <mach/gpio.h>\r
  24 #include <mach/irqs.h>\r
  25 #include <linux/dma-mapping.h>\r
  26 #include <asm/dma.h>\r
  27 #include <linux/preempt.h>\r
  28 #include "rk29_spim.h"\r
  29 #include <linux/spi/spi.h>\r
  30 #include <mach/board.h>\r
  31 \r
  32 #ifdef CONFIG_DEBUG_FS\r
  33 #include <linux/debugfs.h>\r
  34 #endif\r
  35 \r
  36 /*ÔÓÐµÄspiÇý¶¯Ð§ÂÊ±È½ÏµÍ£¬\r
  37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Êä£»\r
  38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Êä£¬Í¬Ê±¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬\r
  39 Ä¬ÈÏÊ¹ÓÃ°ëË«¹¤\r
  40 */\r
  41 \r
  42 //#define QUICK_TRANSFER         \r
  43 \r
  44 #if 0\r
  45 #define DBG   printk\r
  46 #else\r
  47 #define DBG(x...)\r
  48 #endif\r
  49 \r
  50 #define DMA_BUFFER_SIZE PAGE_SIZE\r
  51 #define DMA_MIN_BYTES 32 //>32x16bits FIFO\r
  52 \r
  53 \r
  54 #define START_STATE     ((void *)0)\r
  55 #define RUNNING_STATE   ((void *)1)\r
  56 #define DONE_STATE      ((void *)2)\r
  57 #define ERROR_STATE     ((void *)-1)\r
  58 \r
  59 #define QUEUE_RUNNING   0\r
  60 #define QUEUE_STOPPED   1\r
  61 \r
  62 #define MRST_SPI_DEASSERT       0\r
  63 #define MRST_SPI_ASSERT         1  ///CS0\r
  64 #define MRST_SPI_ASSERT1        2  ///CS1\r
  65 \r
  66 /* Slave spi_dev related */\r
  67 struct chip_data {\r
  68         u16 cr0;\r
  69         u8 cs;                  /* chip select pin */\r
  70         u8 n_bytes;             /* current is a 1/2/4 byte op */\r
  71         u8 tmode;               /* TR/TO/RO/EEPROM */\r
  72         u8 type;                /* SPI/SSP/MicroWire */\r
  73 \r
  74         u8 poll_mode;           /* 1 means use poll mode */\r
  75 \r
  76         u32 dma_width;\r
  77         u32 rx_threshold;\r
  78         u32 tx_threshold;\r
  79         u8 enable_dma:1;\r
  80         u8 bits_per_word;\r
  81         u16 clk_div;            /* baud rate divider */\r
  82         u32 speed_hz;           /* baud rate */\r
  83         int (*write)(struct rk29xx_spi *dws);\r
  84         int (*read)(struct rk29xx_spi *dws);\r
  85         void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);\r
  86 };\r
  87 \r
  88 #define SUSPND    (1<<0)\r
  89 #define SPIBUSY   (1<<1)\r
  90 #define RXBUSY    (1<<2)\r
  91 #define TXBUSY    (1<<3)\r
  92 \r
  93 //\r
  94 #ifdef CONFIG_LCD_USE_SPIM_CONTROL\r
  95 void rk29_lcd_spim_spin_lock(void)\r
  96 {\r
  97 #ifdef CONFIG_LCD_USE_SPI0\r
  98         disable_irq(IRQ_SPI0);\r
  99 #endif\r
 100 \r
 101 #ifdef CONFIG_LCD_USE_SPI1\r
 102         disable_irq(IRQ_SPI1);\r
 103 #endif\r
 104 \r
 105         preempt_disable();\r
 106 }\r
 107 \r
 108 void rk29_lcd_spim_spin_unlock(void)\r
 109 {\r
 110         preempt_enable();\r
 111         \r
 112 #ifdef CONFIG_LCD_USE_SPI0\r
 113         enable_irq(IRQ_SPI0);\r
 114 #endif\r
 115 \r
 116 #ifdef CONFIG_LCD_USE_SPI1\r
 117         enable_irq(IRQ_SPI1);\r
 118 #endif\r
 119 }\r
 120 #else\r
 121 void rk29_lcd_spim_spin_lock(void)\r
 122 {\r
 123      return;\r
 124 }\r
 125 \r
 126 void rk29_lcd_spim_spin_unlock(void)\r
 127 {\r
 128      return;\r
 129 }\r
 130 #endif\r
 131 \r
 132 \r
 133 static void spi_dump_regs(struct rk29xx_spi *dws) {\r
 134         DBG("MRST SPI0 registers:\n");\r
 135         DBG("=================================\n");\r
 136         DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 137         DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 138         DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 139         DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 140         DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 141         DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 142         DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 143         DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 144         DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 145         DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 146         DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 147         DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 148         DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 149         DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 150         DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 151         DBG("=================================\n");\r
 152 \r
 153 }\r
 154 \r
 155 #ifdef CONFIG_DEBUG_FS\r
 156 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 157 {\r
 158         file->private_data = inode->i_private;\r
 159         return 0;\r
 160 }\r
 161 \r
 162 #define SPI_REGS_BUFSIZE        1024\r
 163 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,\r
 164                                 size_t count, loff_t *ppos)\r
 165 {\r
 166         struct rk29xx_spi *dws;\r
 167         char *buf;\r
 168         u32 len = 0;\r
 169         ssize_t ret;\r
 170 \r
 171         dws = file->private_data;\r
 172 \r
 173         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);\r
 174         if (!buf)\r
 175                 return 0;\r
 176 \r
 177         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 178                         "MRST SPI0 registers:\n");\r
 179         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 180                         "=================================\n");\r
 181         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 182                         "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 183         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 184                         "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 185         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 186                         "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 187         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 188                         "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 189         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 190                         "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 191         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 192                         "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 193         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 194                         "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 195         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 196                         "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 197         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 198                         "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 199         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 200                         "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 201         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 202                         "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 203         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 204                         "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 205         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 206                         "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 207         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 208                         "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 209         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 210                         "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 211         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 212                         "=================================\n");\r
 213 \r
 214         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);\r
 215         kfree(buf);\r
 216         return ret;\r
 217 }\r
 218 \r
 219 static const struct file_operations mrst_spi_regs_ops = {\r
 220         .owner          = THIS_MODULE,\r
 221         .open           = spi_show_regs_open,\r
 222         .read           = spi_show_regs,\r
 223 };\r
 224 \r
 225 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 226 {\r
 227         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);\r
 228         if (!dws->debugfs)\r
 229                 return -ENOMEM;\r
 230 \r
 231         debugfs_create_file("registers", S_IFREG | S_IRUGO,\r
 232                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);\r
 233         return 0;\r
 234 }\r
 235 \r
 236 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 237 {\r
 238         if (dws->debugfs)\r
 239                 debugfs_remove_recursive(dws->debugfs);\r
 240 }\r
 241 \r
 242 #else\r
 243 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 244 {\r
 245         return 0;\r
 246 }\r
 247 \r
 248 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 249 {\r
 250 }\r
 251 #endif /* CONFIG_DEBUG_FS */\r
 252 \r
 253 static void dma_transfer(struct rk29xx_spi *dws) ;\r
 254 static void transfer_complete(struct rk29xx_spi *dws);\r
 255 \r
 256 static void wait_till_not_busy(struct rk29xx_spi *dws)\r
 257 {\r
 258         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 259 \r
 260         while (time_before(jiffies, end)) {\r
 261                 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
 262                         return;\r
 263         }\r
 264         dev_err(&dws->master->dev,\r
 265                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 266 }\r
 267 \r
 268 #if defined(QUICK_TRANSFER)\r
 269 static void wait_till_tf_empty(struct rk29xx_spi *dws)\r
 270 {\r
 271         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 272 \r
 273         while (time_before(jiffies, end)) {\r
 274                 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)\r
 275                         return;\r
 276         }\r
 277         dev_err(&dws->master->dev,\r
 278                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 279 }\r
 280 #endif\r
 281 \r
 282 static void flush(struct rk29xx_spi *dws)\r
 283 {\r
 284         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 285                 rk29xx_readw(dws, SPIM_RXDR);\r
 286 \r
 287         wait_till_not_busy(dws);\r
 288 }\r
 289 \r
 290 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 291 {\r
 292         #if 1\r
 293         if (flag)\r
 294                 rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 295         else            \r
 296                 rk29xx_writel(dws, SPIM_SER, 0);\r
 297         return;\r
 298         #else\r
 299         struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
 300         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 301 \r
 302         if (flag == 0) {\r
 303                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
 304         }\r
 305         else {\r
 306                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
 307         }\r
 308         #endif\r
 309 }\r
 310 \r
 311 static int null_writer(struct rk29xx_spi *dws)\r
 312 {\r
 313         u8 n_bytes = dws->n_bytes;\r
 314 \r
 315         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 316                 || (dws->tx == dws->tx_end))\r
 317                 return 0;\r
 318         rk29xx_writew(dws, SPIM_TXDR, 0);\r
 319         dws->tx += n_bytes;\r
 320         //wait_till_not_busy(dws);\r
 321 \r
 322         return 1;\r
 323 }\r
 324 \r
 325 static int null_reader(struct rk29xx_spi *dws)\r
 326 {\r
 327         u8 n_bytes = dws->n_bytes;\r
 328         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 329         while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 330                 && (dws->rx < dws->rx_end)) {\r
 331                 rk29xx_readw(dws, SPIM_RXDR);\r
 332                 dws->rx += n_bytes;\r
 333         }\r
 334         wait_till_not_busy(dws);\r
 335         return dws->rx == dws->rx_end;\r
 336 }\r
 337 \r
 338 static int u8_writer(struct rk29xx_spi *dws)\r
 339 {       \r
 340         spi_dump_regs(dws);\r
 341         DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
 342         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 343                 || (dws->tx == dws->tx_end))\r
 344                 return 0;\r
 345         rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));\r
 346         ++dws->tx;\r
 347         //wait_till_not_busy(dws);\r
 348 \r
 349         return 1;\r
 350 }\r
 351 \r
 352 static int u8_reader(struct rk29xx_spi *dws)\r
 353 {\r
 354     spi_dump_regs(dws);\r
 355         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 356                 && (dws->rx < dws->rx_end)) {\r
 357                 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;\r
 358                 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));\r
 359                 ++dws->rx;\r
 360         }\r
 361 \r
 362         wait_till_not_busy(dws);\r
 363         return dws->rx == dws->rx_end;\r
 364 }\r
 365 \r
 366 static int u16_writer(struct rk29xx_spi *dws)\r
 367 {\r
 368         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 369                 || (dws->tx == dws->tx_end))\r
 370                 return 0;\r
 371 \r
 372         rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));\r
 373         dws->tx += 2;\r
 374         //wait_till_not_busy(dws);\r
 375 \r
 376         return 1;\r
 377 }\r
 378 \r
 379 static int u16_reader(struct rk29xx_spi *dws)\r
 380 {\r
 381         u16 temp;\r
 382 \r
 383         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 384                 && (dws->rx < dws->rx_end)) {\r
 385                 temp = rk29xx_readw(dws, SPIM_RXDR);\r
 386                 *(u16 *)(dws->rx) = temp;\r
 387                 //DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));\r
 388                 dws->rx += 2;\r
 389         }\r
 390 \r
 391         wait_till_not_busy(dws);\r
 392         return dws->rx == dws->rx_end;\r
 393 }\r
 394 \r
 395 static void *next_transfer(struct rk29xx_spi *dws)\r
 396 {\r
 397         struct spi_message *msg = dws->cur_msg;\r
 398         struct spi_transfer *trans = dws->cur_transfer;\r
 399 \r
 400         /* Move to next transfer */\r
 401         if (trans->transfer_list.next != &msg->transfers) {\r
 402                 dws->cur_transfer =\r
 403                         list_entry(trans->transfer_list.next,\r
 404                                         struct spi_transfer,\r
 405                                         transfer_list);\r
 406                 return RUNNING_STATE;\r
 407         } else\r
 408                 return DONE_STATE;\r
 409 }\r
 410 \r
 411 static void rk29_spi_dma_rxcb(void *buf_id,\r
 412                                  int size, enum rk29_dma_buffresult res)\r
 413 {\r
 414         struct rk29xx_spi *dws = buf_id;\r
 415         unsigned long flags;\r
 416 \r
 417         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 418         \r
 419         spin_lock_irqsave(&dws->lock, flags);\r
 420 \r
 421         if (res == RK29_RES_OK)\r
 422                 dws->state &= ~RXBUSY;\r
 423         else\r
 424                 dev_err(&dws->master->dev, "DmaAbrtRx-%d, size: %d,res=%d\n", res, size,res);\r
 425 \r
 426         /* If the other done */\r
 427         //if (!(dws->state & TXBUSY))\r
 428         //      complete(&dws->rx_completion);\r
 429         \r
 430         //DMA could not lose intterupt\r
 431         transfer_complete(dws);\r
 432 \r
 433         spin_unlock_irqrestore(&dws->lock, flags);\r
 434 }\r
 435 \r
 436 static void rk29_spi_dma_txcb(void *buf_id,\r
 437                                  int size, enum rk29_dma_buffresult res)\r
 438 {\r
 439         struct rk29xx_spi *dws = buf_id;\r
 440         unsigned long flags;\r
 441 \r
 442         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 443         \r
 444         spin_lock_irqsave(&dws->lock, flags);\r
 445 \r
 446         if (res == RK29_RES_OK)\r
 447                 dws->state &= ~TXBUSY;\r
 448         else\r
 449                 dev_err(&dws->master->dev, "DmaAbrtTx-%d, size: %d,res=%d \n", res, size,res);\r
 450 \r
 451         /* If the other done */\r
 452         //if (!(dws->state & RXBUSY)) \r
 453         //      complete(&dws->tx_completion);\r
 454 \r
 455         //DMA could not lose intterupt\r
 456         transfer_complete(dws);\r
 457 \r
 458         spin_unlock_irqrestore(&dws->lock, flags);\r
 459 }\r
 460 \r
 461 \r
 462 static struct rk29_dma_client rk29_spi_dma_client = {\r
 463         .name = "rk29xx-spi-dma",\r
 464 };\r
 465 \r
 466 static int acquire_dma(struct rk29xx_spi *dws)\r
 467 {       \r
 468         if (dws->dma_inited) {\r
 469                 return 0;\r
 470         }\r
 471 \r
 472         dws->buffer_tx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->tx_dma, GFP_KERNEL | GFP_DMA);\r
 473         if (!dws->buffer_tx_dma)\r
 474         {\r
 475                 dev_err(&dws->pdev->dev, "fail to dma tx buffer alloc\n");\r
 476                 return -1;\r
 477         }\r
 478 \r
 479         dws->buffer_rx_dma = dma_alloc_coherent(&dws->pdev->dev, DMA_BUFFER_SIZE, &dws->rx_dma, GFP_KERNEL | GFP_DMA);\r
 480         if (!dws->buffer_rx_dma)\r
 481         {\r
 482                 dev_err(&dws->pdev->dev, "fail to dma rx buffer alloc\n");\r
 483                 return -1;\r
 484         }\r
 485 \r
 486         if(rk29_dma_request(dws->rx_dmach, \r
 487                 &rk29_spi_dma_client, NULL) < 0) {\r
 488                 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);\r
 489                 return -1;\r
 490         }\r
 491 \r
 492         if (rk29_dma_request(dws->tx_dmach,\r
 493                                         &rk29_spi_dma_client, NULL) < 0) {\r
 494                 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);\r
 495                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 496                 return -1;\r
 497         }\r
 498 \r
 499         if (dws->tx_dma) {\r
 500                 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {\r
 501                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 502                         return -1;\r
 503                 }\r
 504                 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
 505                                         dws->sfr_start + SPIM_TXDR)) {\r
 506                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 507                         return -1;\r
 508                 }\r
 509         }\r
 510 \r
 511         if (dws->rx_dma) {\r
 512                 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {\r
 513                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 514                         return -1;\r
 515                 }\r
 516                 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
 517                                         dws->sfr_start + SPIM_RXDR)) {\r
 518                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 519                         return -1;\r
 520                 }\r
 521         }\r
 522         \r
 523         dws->dma_inited = 1;\r
 524         return 0;\r
 525 }\r
 526 \r
 527 static void release_dma(struct rk29xx_spi *dws)\r
 528 {\r
 529         if(!dws && dws->dma_inited) {\r
 530                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 531                 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);\r
 532         }\r
 533 }\r
 534 \r
 535 /*\r
 536  * Note: first step is the protocol driver prepares\r
 537  * a dma-capable memory, and this func just need translate\r
 538  * the virt addr to physical\r
 539  */\r
 540 static int map_dma_buffers(struct rk29xx_spi *dws)\r
 541 {\r
 542         if (!dws->dma_inited || !dws->cur_chip->enable_dma)\r
 543         {\r
 544                 printk("%s:error\n",__func__);\r
 545                 return -1;\r
 546         }\r
 547 \r
 548         if(dws->cur_transfer->tx_buf)\r
 549         {\r
 550                 memcpy(dws->buffer_tx_dma,dws->cur_transfer->tx_buf,dws->cur_transfer->len);\r
 551                 dws->cur_transfer->tx_buf = dws->buffer_tx_dma; \r
 552         }\r
 553 \r
 554         if(dws->cur_transfer->rx_buf)\r
 555         {\r
 556                 //memcpy(dws->buffer_rx_dma,dws->cur_transfer->rx_buf,dws->cur_transfer->len);\r
 557                 dws->cur_transfer->rx_buf = dws->buffer_rx_dma; \r
 558         }\r
 559         \r
 560         dws->cur_transfer->tx_dma = dws->tx_dma;\r
 561         dws->cur_transfer->rx_dma = dws->rx_dma;\r
 562         \r
 563         return 0;\r
 564 }\r
 565 \r
 566 /* Caller already set message->status; dma and pio irqs are blocked */\r
 567 static void giveback(struct rk29xx_spi *dws)\r
 568 {\r
 569         struct spi_transfer *last_transfer;\r
 570         unsigned long flags;\r
 571         struct spi_message *msg;\r
 572 \r
 573         spin_lock_irqsave(&dws->lock, flags);\r
 574         msg = dws->cur_msg;\r
 575         dws->cur_msg = NULL;\r
 576         dws->cur_transfer = NULL;\r
 577         dws->prev_chip = dws->cur_chip;\r
 578         dws->cur_chip = NULL;\r
 579         dws->dma_mapped = 0;\r
 580         \r
 581         /*it is important to close intterrupt*/\r
 582         spi_umask_intr(dws, 0);\r
 583         rk29xx_writew(dws, SPIM_DMACR, 0);\r
 584         \r
 585         queue_work(dws->workqueue, &dws->pump_messages);\r
 586         spin_unlock_irqrestore(&dws->lock, flags);\r
 587 \r
 588         last_transfer = list_entry(msg->transfers.prev,\r
 589                                         struct spi_transfer,\r
 590                                         transfer_list);\r
 591 \r
 592         if (!last_transfer->cs_change && dws->cs_control)\r
 593                 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 594 \r
 595         msg->state = NULL;\r
 596         if (msg->complete)\r
 597                 msg->complete(msg->context);\r
 598 \r
 599 }\r
 600 \r
 601 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)\r
 602 {\r
 603         /* Stop and reset hw */\r
 604         flush(dws);\r
 605         spi_enable_chip(dws, 0);\r
 606 \r
 607         dev_err(&dws->master->dev, "%s\n", msg);\r
 608         dws->cur_msg->state = ERROR_STATE;\r
 609         tasklet_schedule(&dws->pump_transfers);\r
 610 }\r
 611 \r
 612 static void transfer_complete(struct rk29xx_spi *dws)\r
 613 {\r
 614         /* Update total byte transfered return count actual bytes read */\r
 615         dws->cur_msg->actual_length += dws->len;\r
 616 \r
 617         /* Move to next transfer */\r
 618         dws->cur_msg->state = next_transfer(dws);\r
 619 \r
 620         /* Handle end of message */\r
 621         if (dws->cur_msg->state == DONE_STATE) {\r
 622                 dws->cur_msg->status = 0;\r
 623                 giveback(dws);\r
 624         } else\r
 625                 tasklet_schedule(&dws->pump_transfers);\r
 626 }\r
 627 \r
 628 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 629 {\r
 630         u16 irq_status, irq_mask = 0x1f;\r
 631         u32 int_level = dws->fifo_len / 2;\r
 632         u32 left;\r
 633 \r
 634         irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;\r
 635         /* Error handling */\r
 636         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {\r
 637                 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);\r
 638                 int_error_stop(dws, "interrupt_transfer: fifo overrun");\r
 639                 mutex_unlock(&dws->dma_lock);   \r
 640                 return IRQ_HANDLED;\r
 641         }\r
 642 \r
 643         if (irq_status & SPI_INT_TXEI) {\r
 644                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 645 \r
 646                 left = (dws->tx_end - dws->tx) / dws->n_bytes;\r
 647                 left = (left > int_level) ? int_level : left;\r
 648 \r
 649                 while (left--) {\r
 650                         dws->write(dws);\r
 651                         wait_till_not_busy(dws);\r
 652                 }\r
 653                 if (dws->rx) {\r
 654                     dws->read(dws);\r
 655                 }\r
 656 \r
 657                 /* Re-enable the IRQ if there is still data left to tx */\r
 658                 if (dws->tx_end > dws->tx)\r
 659                         spi_umask_intr(dws, SPI_INT_TXEI);\r
 660                 else\r
 661                         transfer_complete(dws);\r
 662         }\r
 663 \r
 664         if (irq_status & SPI_INT_RXFI) {\r
 665                 spi_mask_intr(dws, SPI_INT_RXFI);\r
 666                 \r
 667                 dws->read(dws);\r
 668 \r
 669                 /* Re-enable the IRQ if there is still data left to rx */\r
 670                 if (dws->rx_end > dws->rx) {\r
 671                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;\r
 672                     left = (left > int_level) ? int_level : left;\r
 673 \r
 674                         rk29xx_writew(dws, SPIM_RXFTLR, left);\r
 675                         spi_umask_intr(dws, SPI_INT_RXFI);\r
 676                 }\r
 677                 else {\r
 678                         transfer_complete(dws);\r
 679                 }\r
 680                 \r
 681         }       \r
 682 \r
 683         return IRQ_HANDLED;\r
 684 }\r
 685 \r
 686 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)\r
 687 {\r
 688         struct rk29xx_spi *dws = dev_id;\r
 689 \r
 690         if (!dws->cur_msg) {\r
 691                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 692                 /* Never fail */\r
 693                 return IRQ_HANDLED;\r
 694         }\r
 695 \r
 696         return dws->transfer_handler(dws);\r
 697 }\r
 698 \r
 699 /* Must be called inside pump_transfers() */\r
 700 static void poll_transfer(struct rk29xx_spi *dws)\r
 701 {\r
 702         DBG("%s\n",__func__);\r
 703         while (dws->write(dws)) {\r
 704                 wait_till_not_busy(dws);\r
 705                 dws->read(dws);\r
 706         }\r
 707         transfer_complete(dws);\r
 708 }\r
 709 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)\r
 710 {\r
 711     if(cs >= dws->master->num_chipselect)\r
 712                 return;\r
 713 \r
 714         if (dws->cs_control){\r
 715             dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
 716         }\r
 717         rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 718 }\r
 719 \r
 720 static void pump_transfers(unsigned long data)\r
 721 {\r
 722         struct rk29xx_spi *dws = (struct rk29xx_spi *)data;\r
 723         struct spi_message *message = NULL;\r
 724         struct spi_transfer *transfer = NULL;\r
 725         struct spi_transfer *previous = NULL;\r
 726         struct spi_device *spi = NULL;\r
 727         struct chip_data *chip = NULL;\r
 728         u8 bits = 0;\r
 729         u8 spi_dfs = 0;\r
 730         u8 imask = 0;\r
 731         u8 cs_change = 0;\r
 732         u16 txint_level = 0;\r
 733         u16 rxint_level = 0;\r
 734         u16 clk_div = 0;\r
 735         u32 speed = 0;\r
 736         u32 cr0 = 0;\r
 737 \r
 738         if((dws->cur_chip->enable_dma) && (dws->cur_transfer->len > DMA_MIN_BYTES) && (dws->cur_transfer->len < DMA_BUFFER_SIZE)){      \r
 739                 dma_transfer(dws);\r
 740                 return;\r
 741         }       \r
 742         \r
 743         DBG(KERN_INFO "pump_transfers,len=%d\n",dws->cur_transfer->len);\r
 744 \r
 745         /* Get current state information */\r
 746         message = dws->cur_msg;\r
 747         transfer = dws->cur_transfer;\r
 748         chip = dws->cur_chip;\r
 749         spi = message->spi;     \r
 750         if (unlikely(!chip->clk_div))\r
 751                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 752         if (message->state == ERROR_STATE) {\r
 753                 message->status = -EIO;\r
 754                 goto early_exit;\r
 755         }\r
 756 \r
 757         /* Handle end of message */\r
 758         if (message->state == DONE_STATE) {\r
 759                 message->status = 0;\r
 760                 goto early_exit;\r
 761         }\r
 762 \r
 763         /* Delay if requested at end of transfer*/\r
 764         if (message->state == RUNNING_STATE) {\r
 765                 previous = list_entry(transfer->transfer_list.prev,\r
 766                                         struct spi_transfer,\r
 767                                         transfer_list);\r
 768                 if (previous->delay_usecs)\r
 769                         udelay(previous->delay_usecs);\r
 770         }\r
 771 \r
 772         dws->n_bytes = chip->n_bytes;\r
 773         dws->dma_width = chip->dma_width;\r
 774         dws->cs_control = chip->cs_control;\r
 775 \r
 776         //dws->rx_dma = transfer->rx_dma;\r
 777         //dws->tx_dma = transfer->tx_dma;\r
 778         dws->tx = (void *)transfer->tx_buf;\r
 779         dws->tx_end = dws->tx + transfer->len;\r
 780         dws->rx = (void *)transfer->rx_buf;\r
 781         dws->rx_end = dws->rx + transfer->len;\r
 782         dws->write = dws->tx ? chip->write : null_writer;\r
 783         dws->read = dws->rx ? chip->read : null_reader;\r
 784         dws->cs_change = transfer->cs_change;\r
 785         dws->len = dws->cur_transfer->len;\r
 786         if (chip != dws->prev_chip)\r
 787                 cs_change = 1;\r
 788 \r
 789         cr0 = chip->cr0;\r
 790 \r
 791         /* Handle per transfer options for bpw and speed */\r
 792         if (transfer->speed_hz) {\r
 793                 speed = chip->speed_hz;\r
 794 \r
 795                 if (transfer->speed_hz != speed) {\r
 796                         speed = transfer->speed_hz;\r
 797                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 798                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
 799                                         "freq: %dHz\n", speed);\r
 800                                 message->status = -EIO;\r
 801                                 goto early_exit;\r
 802                         }\r
 803 \r
 804                         /* clk_div doesn't support odd number */\r
 805                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 806                         clk_div = (clk_div + 1) & 0xfffe;\r
 807 \r
 808                         chip->speed_hz = speed;\r
 809                         chip->clk_div = clk_div;\r
 810                 }\r
 811         }\r
 812         \r
 813         if (transfer->bits_per_word) {\r
 814                 bits = transfer->bits_per_word;\r
 815 \r
 816                 switch (bits) {\r
 817                 case 8:\r
 818                         dws->n_bytes = 1;\r
 819                         dws->dma_width = 1;\r
 820                         dws->read = (dws->read != null_reader) ?\r
 821                                         u8_reader : null_reader;\r
 822                         dws->write = (dws->write != null_writer) ?\r
 823                                         u8_writer : null_writer;\r
 824                         spi_dfs = SPI_DFS_8BIT;\r
 825                         break;\r
 826                 case 16:\r
 827                         dws->n_bytes = 2;\r
 828                         dws->dma_width = 2;\r
 829                         dws->read = (dws->read != null_reader) ?\r
 830                                         u16_reader : null_reader;\r
 831                         dws->write = (dws->write != null_writer) ?\r
 832                                         u16_writer : null_writer;\r
 833                         spi_dfs = SPI_DFS_16BIT;\r
 834                         break;\r
 835                 default:\r
 836                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 837                                 "%db\n", bits);\r
 838                         message->status = -EIO;\r
 839                         goto early_exit;\r
 840                 }\r
 841 \r
 842                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 843                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 844                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 845                         | (chip->type << SPI_FRF_OFFSET)\r
 846                         | (spi->mode << SPI_MODE_OFFSET)\r
 847                         | (chip->tmode << SPI_TMOD_OFFSET);\r
 848         }\r
 849         message->state = RUNNING_STATE;\r
 850  \r
 851         /*\r
 852          * Adjust transfer mode if necessary. Requires platform dependent\r
 853          * chipselect mechanism.\r
 854          */\r
 855         if (dws->cs_control) {\r
 856                 if (dws->rx && dws->tx)\r
 857                         chip->tmode = SPI_TMOD_TR;\r
 858                 else if (dws->rx)\r
 859                         chip->tmode = SPI_TMOD_RO;\r
 860                 else\r
 861                         chip->tmode = SPI_TMOD_TO;\r
 862 \r
 863                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
 864                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
 865         } \r
 866 \r
 867         /*\r
 868          * Interrupt mode\r
 869          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely\r
 870          */\r
 871         if (!dws->dma_mapped && !chip->poll_mode) {     \r
 872                 int templen ;\r
 873                 \r
 874                 if (chip->tmode == SPI_TMOD_RO) {\r
 875                         templen = dws->len / dws->n_bytes - 1;\r
 876                         rxint_level = dws->fifo_len / 2;\r
 877                         rxint_level = (templen > rxint_level) ? rxint_level : templen;\r
 878                         imask |= SPI_INT_RXFI;\r
 879                 }\r
 880                 else {  \r
 881                         templen = dws->len / dws->n_bytes;\r
 882                         txint_level = dws->fifo_len / 2;\r
 883                         txint_level = (templen > txint_level) ? txint_level : templen;\r
 884                         imask |= SPI_INT_TXEI;\r
 885                 }\r
 886                 dws->transfer_handler = interrupt_transfer;\r
 887         }\r
 888 \r
 889         /*\r
 890          * Reprogram registers only if\r
 891          *      1. chip select changes\r
 892          *      2. clk_div is changed\r
 893          *      3. control value changes\r
 894          */\r
 895         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {\r
 896                 spi_enable_chip(dws, 0);\r
 897                 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)\r
 898                         rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
 899 \r
 900                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
 901                 spi_chip_sel(dws, spi->chip_select);\r
 902 \r
 903         rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
 904                 spi_enable_chip(dws, 1);\r
 905 \r
 906                 if (txint_level)\r
 907                         rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
 908                 if (rxint_level)\r
 909                         rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
 910                 /* Set the interrupt mask, for poll mode just diable all int */\r
 911                 spi_mask_intr(dws, 0xff);\r
 912                 if (imask)\r
 913                         spi_umask_intr(dws, imask);\r
 914                 \r
 915                 if (cs_change)\r
 916                         dws->prev_chip = chip;\r
 917         } \r
 918 \r
 919         if (chip->poll_mode)\r
 920                 poll_transfer(dws);\r
 921 \r
 922         return;\r
 923 \r
 924 early_exit:\r
 925         giveback(dws);\r
 926         return;\r
 927 }\r
 928 \r
 929 static void dma_transfer(struct rk29xx_spi *dws) \r
 930 {\r
 931         struct spi_message *message = NULL;\r
 932         struct spi_transfer *transfer = NULL;\r
 933         struct spi_transfer *previous = NULL;\r
 934         struct spi_device *spi = NULL;\r
 935         struct chip_data *chip = NULL;\r
 936         //unsigned long val;    \r
 937         //unsigned long flags;\r
 938         //int ms;\r
 939         int iRet;\r
 940         //int burst;\r
 941         u8 bits = 0;\r
 942         u8 spi_dfs = 0;\r
 943         u8 cs_change = 0;\r
 944         u16 clk_div = 0;\r
 945         u32 speed = 0;\r
 946         u32 cr0 = 0;\r
 947         u32 dmacr = 0;\r
 948         \r
 949         DBG(KERN_INFO "dma_transfer,len=%d\n",dws->cur_transfer->len);  \r
 950         \r
 951         if (acquire_dma(dws)) {\r
 952                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 953                 goto err_out;\r
 954         }\r
 955 \r
 956         if (map_dma_buffers(dws)) {\r
 957                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 958                 goto err_out;\r
 959         }\r
 960 \r
 961         /* Get current state information */\r
 962         message = dws->cur_msg;\r
 963         transfer = dws->cur_transfer;\r
 964         chip = dws->cur_chip;\r
 965         spi = message->spi;     \r
 966         if (unlikely(!chip->clk_div))\r
 967                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 968         if (message->state == ERROR_STATE) {\r
 969                 message->status = -EIO;\r
 970                 goto err_out;\r
 971         }\r
 972 \r
 973         /* Handle end of message */\r
 974         if (message->state == DONE_STATE) {\r
 975                 message->status = 0;\r
 976                 goto err_out;\r
 977         }\r
 978 \r
 979         /* Delay if requested at end of transfer*/\r
 980         if (message->state == RUNNING_STATE) {\r
 981                 previous = list_entry(transfer->transfer_list.prev,\r
 982                                         struct spi_transfer,\r
 983                                         transfer_list);\r
 984                 if (previous->delay_usecs)\r
 985                         udelay(previous->delay_usecs);\r
 986         }\r
 987 \r
 988         dws->n_bytes = chip->n_bytes;\r
 989         dws->dma_width = chip->dma_width;\r
 990         dws->cs_control = chip->cs_control;\r
 991 \r
 992         //dws->rx_dma = transfer->rx_dma;\r
 993         //dws->tx_dma = transfer->tx_dma;\r
 994         dws->tx = (void *)transfer->tx_buf;\r
 995         dws->tx_end = dws->tx + transfer->len;\r
 996         dws->rx = (void *)transfer->rx_buf;\r
 997         dws->rx_end = dws->rx + transfer->len;\r
 998         dws->write = dws->tx ? chip->write : null_writer;\r
 999         dws->read = dws->rx ? chip->read : null_reader;\r
1000         dws->cs_change = transfer->cs_change;\r
1001         dws->len = dws->cur_transfer->len;\r
1002         if (chip != dws->prev_chip)\r
1003                 cs_change = 1;\r
1004 \r
1005         cr0 = chip->cr0;\r
1006         \r
1007         /* Handle per transfer options for bpw and speed */\r
1008         if (transfer->speed_hz) {\r
1009                 speed = chip->speed_hz;\r
1010                 if (transfer->speed_hz != speed) {\r
1011                         speed = transfer->speed_hz;\r
1012                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1013                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1014                                         "freq: %dHz\n", speed);\r
1015                                 message->status = -EIO;\r
1016                                 goto err_out;\r
1017                         }\r
1018 \r
1019                         /* clk_div doesn't support odd number */\r
1020                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1021                         clk_div = (clk_div + 1) & 0xfffe;\r
1022 \r
1023                         chip->speed_hz = speed;\r
1024                         chip->clk_div = clk_div;\r
1025                 }\r
1026         }\r
1027 \r
1028         \r
1029         if (transfer->bits_per_word) {\r
1030                 bits = transfer->bits_per_word;\r
1031 \r
1032                 switch (bits) {\r
1033                 case 8:\r
1034                         dws->n_bytes = 1;\r
1035                         dws->dma_width = 1;\r
1036                         spi_dfs = SPI_DFS_8BIT;\r
1037                         break;\r
1038                 case 16:\r
1039                         dws->n_bytes = 2;\r
1040                         dws->dma_width = 2;\r
1041                         spi_dfs = SPI_DFS_16BIT;\r
1042                         break;\r
1043                 default:\r
1044                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1045                                 "%db\n", bits);\r
1046                         message->status = -EIO;\r
1047                         goto err_out;\r
1048                 }\r
1049 \r
1050                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1051                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1052                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1053                         | (chip->type << SPI_FRF_OFFSET)\r
1054                         | (spi->mode << SPI_MODE_OFFSET)\r
1055                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1056         }\r
1057         message->state = RUNNING_STATE;\r
1058  \r
1059         /*\r
1060          * Adjust transfer mode if necessary. Requires platform dependent\r
1061          * chipselect mechanism.\r
1062          */\r
1063         if (dws->cs_control) {\r
1064                 if (dws->rx && dws->tx)\r
1065                         chip->tmode = SPI_TMOD_TR;\r
1066                 else if (dws->rx)\r
1067                         chip->tmode = SPI_TMOD_RO;\r
1068                 else\r
1069                         chip->tmode = SPI_TMOD_TO;\r
1070 \r
1071                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1072                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1073         }\r
1074 \r
1075         /*\r
1076          * Reprogram registers only if\r
1077          *      1. chip select changes\r
1078          *      2. clk_div is changed\r
1079          *      3. control value changes\r
1080          */\r
1081         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div) {\r
1082                 spi_enable_chip(dws, 0);\r
1083                 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0) {\r
1084                         rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
1085                 }\r
1086 \r
1087                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1088                 spi_chip_sel(dws, spi->chip_select);\r
1089                 /* Set the interrupt mask, for poll mode just diable all int */\r
1090                 spi_mask_intr(dws, 0xff);\r
1091                 \r
1092                 if (transfer->tx_buf != NULL) {\r
1093                         dmacr |= SPI_DMACR_TX_ENABLE;\r
1094                         rk29xx_writew(dws, SPIM_DMATDLR, 0);\r
1095                 }\r
1096                 if (transfer->rx_buf != NULL) {\r
1097                         dmacr |= SPI_DMACR_RX_ENABLE;\r
1098                         rk29xx_writew(dws, SPIM_DMARDLR, 0);\r
1099                         rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);\r
1100                 }\r
1101                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1102                 spi_enable_chip(dws, 1);\r
1103                 if (cs_change)\r
1104                         dws->prev_chip = chip;\r
1105         } \r
1106 \r
1107         //INIT_COMPLETION(dws->xfer_completion);\r
1108 \r
1109         spi_dump_regs(dws);\r
1110         DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, transfer->tx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)transfer->tx_dma);\r
1111         if (transfer->tx_buf != NULL) {\r
1112                 dws->state |= TXBUSY;\r
1113                 /*if (transfer->len & 0x3) {\r
1114                         burst = 1;\r
1115                 }\r
1116                 else {\r
1117                         burst = 4;\r
1118                 }\r
1119                 if (rk29_dma_config(dws->tx_dmach, burst)) {*/\r
1120                 if (rk29_dma_config(dws->tx_dmach, 1, 1)) {//there is not dma burst but bitwide, set it 1 alwayss\r
1121                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1122                         goto err_out;\r
1123                 }\r
1124                 \r
1125                 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH); \r
1126                 \r
1127                 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,\r
1128                                         transfer->tx_dma, transfer->len);\r
1129                 if (iRet) {\r
1130                         dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet, \r
1131                                 dws->tx_dmach, (unsigned int)transfer->tx_dma);\r
1132                         goto err_out;\r
1133                 }\r
1134                 \r
1135                 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {\r
1136                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1137                         goto err_out;\r
1138                 }\r
1139         }\r
1140 \r
1141         //wait_till_not_busy(dws);\r
1142         \r
1143         if (transfer->rx_buf != NULL) {\r
1144                 dws->state |= RXBUSY;\r
1145                 if (rk29_dma_config(dws->rx_dmach, 1, 1)) {\r
1146                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1147                         goto err_out;\r
1148                 }\r
1149 \r
1150                 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH); \r
1151                 \r
1152                 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,\r
1153                                         transfer->rx_dma, transfer->len);\r
1154                 if (iRet) {\r
1155                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1156                         goto err_out;\r
1157                 }\r
1158                 \r
1159                 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {\r
1160                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1161                         goto err_out;\r
1162                 }\r
1163         }\r
1164         \r
1165         return;\r
1166 \r
1167 err_out:\r
1168         giveback(dws);\r
1169         return;\r
1170 \r
1171 }\r
1172 \r
1173 static void pump_messages(struct work_struct *work)\r
1174 {\r
1175         struct rk29xx_spi *dws =\r
1176                 container_of(work, struct rk29xx_spi, pump_messages);\r
1177         unsigned long flags;\r
1178 \r
1179         DBG(KERN_INFO "pump_messages\n");\r
1180         \r
1181         /* Lock queue and check for queue work */\r
1182         spin_lock_irqsave(&dws->lock, flags);\r
1183         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1184                 dws->busy = 0;\r
1185                 spin_unlock_irqrestore(&dws->lock, flags);\r
1186                 mutex_unlock(&dws->dma_lock);\r
1187                 return;\r
1188         }\r
1189 \r
1190         /* Make sure we are not already running a message */\r
1191         if (dws->cur_msg) {\r
1192                 spin_unlock_irqrestore(&dws->lock, flags);\r
1193                 mutex_unlock(&dws->dma_lock);\r
1194                 return;\r
1195         }\r
1196 \r
1197         /* Extract head of queue */\r
1198         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1199         list_del_init(&dws->cur_msg->queue);\r
1200 \r
1201         /* Initial message state*/\r
1202         dws->cur_msg->state = START_STATE;\r
1203         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1204                                                 struct spi_transfer,\r
1205                                                 transfer_list);\r
1206         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1207         dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1208 \r
1209         /* Mark as busy and launch transfers */\r
1210         tasklet_schedule(&dws->pump_transfers);\r
1211         dws->busy = 1;\r
1212         spin_unlock_irqrestore(&dws->lock, flags);\r
1213         \r
1214 }\r
1215 \r
1216 #if defined(QUICK_TRANSFER)\r
1217 static void do_read(struct rk29xx_spi *dws)\r
1218 {\r
1219         int count = 0;\r
1220 \r
1221         spi_enable_chip(dws, 0);\r
1222         rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);\r
1223         spi_enable_chip(dws, 1);                \r
1224         rk29xx_writew(dws, SPIM_TXDR, 0);\r
1225         while (1) {\r
1226                 if (dws->read(dws))\r
1227                         break;\r
1228                 if (count++ == 0x20) {\r
1229                         dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");\r
1230                         break;\r
1231                 }\r
1232                 \r
1233         }\r
1234 }\r
1235 \r
1236 static void do_write(struct rk29xx_spi *dws)\r
1237 {\r
1238         while (dws->tx<dws->tx_end) {\r
1239                 dws->write(dws);\r
1240         }\r
1241 }\r
1242 \r
1243 /* Caller already set message->status; dma and pio irqs are blocked */\r
1244 static void msg_giveback(struct rk29xx_spi *dws)\r
1245 {\r
1246         struct spi_transfer *last_transfer;\r
1247         struct spi_message *msg;\r
1248 \r
1249         DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1250 \r
1251         msg = dws->cur_msg;\r
1252         dws->cur_msg = NULL;\r
1253         dws->cur_transfer = NULL;\r
1254         dws->prev_chip = dws->cur_chip;\r
1255         dws->cur_chip = NULL;\r
1256         dws->dma_mapped = 0;\r
1257         dws->busy = 0;\r
1258 \r
1259         last_transfer = list_entry(msg->transfers.prev,\r
1260                                         struct spi_transfer,\r
1261                                         transfer_list);\r
1262 \r
1263         if (!last_transfer->cs_change && dws->cs_control)\r
1264                 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
1265 \r
1266         msg->state = NULL;      \r
1267 }\r
1268 \r
1269 /* Must be called inside pump_transfers() */\r
1270 static int do_full_transfer(struct rk29xx_spi *dws)\r
1271 {\r
1272         if ((dws->read(dws))) {\r
1273                 goto comple;\r
1274         }\r
1275         \r
1276         while (dws->tx<dws->tx_end){\r
1277                 dws->write(dws);                \r
1278                 dws->read(dws);\r
1279         }\r
1280         \r
1281         if (dws->rx < dws->rx_end) {\r
1282                 dws->read(dws);\r
1283         }\r
1284 \r
1285 comple:\r
1286         \r
1287         dws->cur_msg->actual_length += dws->len;\r
1288         \r
1289         /* Move to next transfer */\r
1290         dws->cur_msg->state = next_transfer(dws);\r
1291                                         \r
1292         if (dws->cur_msg->state == DONE_STATE) {\r
1293                 dws->cur_msg->status = 0;\r
1294                 //msg_giveback(dws);\r
1295                 return 0;\r
1296         }\r
1297         else {\r
1298                 return -1;\r
1299         }\r
1300         \r
1301 }\r
1302 \r
1303 \r
1304 /* Must be called inside pump_transfers() */\r
1305 static int do_half_transfer(struct rk29xx_spi *dws)\r
1306 {\r
1307         if (dws->rx) {\r
1308                 if (dws->tx) {\r
1309                         do_write(dws);\r
1310                 }\r
1311                 wait_till_tf_empty(dws);\r
1312                 wait_till_not_busy(dws);\r
1313                 do_read(dws);\r
1314         }\r
1315         else {\r
1316                 do_write(dws);\r
1317                 wait_till_tf_empty(dws);\r
1318                 wait_till_not_busy(dws);\r
1319         }\r
1320         \r
1321         dws->cur_msg->actual_length += dws->len;\r
1322         \r
1323         /* Move to next transfer */\r
1324         dws->cur_msg->state = next_transfer(dws);\r
1325                                         \r
1326         if (dws->cur_msg->state == DONE_STATE) {\r
1327                 dws->cur_msg->status = 0;\r
1328                 //msg_giveback(dws);\r
1329                 return 0;\r
1330         }\r
1331         else {\r
1332                 return -1;\r
1333         }\r
1334 }\r
1335 \r
1336 \r
1337 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)\r
1338 {\r
1339         struct spi_message *message = NULL;\r
1340         struct spi_transfer *transfer = NULL;\r
1341         struct spi_transfer *previous = NULL;\r
1342         struct spi_device *spi = NULL;\r
1343         struct chip_data *chip = NULL;\r
1344         u8 bits = 0;\r
1345         u8 spi_dfs = 0;\r
1346         u8 cs_change = 0;\r
1347         u16 clk_div = 0;\r
1348         u32 speed = 0;\r
1349         u32 cr0 = 0;\r
1350         u32 dmacr = 0;\r
1351         \r
1352         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1353 \r
1354         /* Get current state information */\r
1355         message = dws->cur_msg;\r
1356         transfer = dws->cur_transfer;\r
1357         chip = dws->cur_chip;\r
1358         spi = message->spi;     \r
1359 \r
1360         if (unlikely(!chip->clk_div))\r
1361                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;\r
1362         if (message->state == ERROR_STATE) {\r
1363                 message->status = -EIO;\r
1364                 goto early_exit;\r
1365         }\r
1366 \r
1367         /* Handle end of message */\r
1368         if (message->state == DONE_STATE) {\r
1369                 message->status = 0;\r
1370                 goto early_exit;\r
1371         }\r
1372 \r
1373         /* Delay if requested at end of transfer*/\r
1374         if (message->state == RUNNING_STATE) {\r
1375                 previous = list_entry(transfer->transfer_list.prev,\r
1376                                         struct spi_transfer,\r
1377                                         transfer_list);\r
1378                 if (previous->delay_usecs)\r
1379                         udelay(previous->delay_usecs);\r
1380         }\r
1381 \r
1382         dws->n_bytes = chip->n_bytes;\r
1383         dws->dma_width = chip->dma_width;\r
1384         dws->cs_control = chip->cs_control;\r
1385 \r
1386         dws->rx_dma = transfer->rx_dma;\r
1387         dws->tx_dma = transfer->tx_dma;\r
1388         dws->tx = (void *)transfer->tx_buf;\r
1389         dws->tx_end = dws->tx + transfer->len;\r
1390         dws->rx = transfer->rx_buf;\r
1391         dws->rx_end = dws->rx + transfer->len;\r
1392         dws->write = dws->tx ? chip->write : null_writer;\r
1393         dws->read = dws->rx ? chip->read : null_reader;\r
1394         if (dws->rx && dws->tx) {\r
1395                 int temp_len = transfer->len;\r
1396                 int len;\r
1397                 unsigned char *tx_buf;\r
1398                 for (len=0; *tx_buf++ != 0; len++);\r
1399                 dws->tx_end = dws->tx + len;\r
1400                 dws->rx_end = dws->rx + temp_len - len;\r
1401         }\r
1402         dws->cs_change = transfer->cs_change;\r
1403         dws->len = dws->cur_transfer->len;\r
1404         if (chip != dws->prev_chip)\r
1405                 cs_change = 1;\r
1406 \r
1407         cr0 = chip->cr0;\r
1408 \r
1409         /* Handle per transfer options for bpw and speed */\r
1410         if (transfer->speed_hz) {\r
1411                 speed = chip->speed_hz;\r
1412 \r
1413                 if (transfer->speed_hz != speed) {\r
1414                         speed = transfer->speed_hz;\r
1415                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1416                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1417                                         "freq: %dHz\n", speed);\r
1418                                 message->status = -EIO;\r
1419                                 goto early_exit;\r
1420                         }\r
1421 \r
1422                         /* clk_div doesn't support odd number */\r
1423                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1424                         clk_div = (clk_div + 1) & 0xfffe;\r
1425 \r
1426                         chip->speed_hz = speed;\r
1427                         chip->clk_div = clk_div;\r
1428                 }\r
1429         }\r
1430         if (transfer->bits_per_word) {\r
1431                 bits = transfer->bits_per_word;\r
1432 \r
1433                 switch (bits) {\r
1434                 case 8:\r
1435                         dws->n_bytes = 1;\r
1436                         dws->dma_width = 1;\r
1437                         dws->read = (dws->read != null_reader) ?\r
1438                                         u8_reader : null_reader;\r
1439                         dws->write = (dws->write != null_writer) ?\r
1440                                         u8_writer : null_writer;\r
1441                         spi_dfs = SPI_DFS_8BIT;\r
1442                         break;\r
1443                 case 16:\r
1444                         dws->n_bytes = 2;\r
1445                         dws->dma_width = 2;\r
1446                         dws->read = (dws->read != null_reader) ?\r
1447                                         u16_reader : null_reader;\r
1448                         dws->write = (dws->write != null_writer) ?\r
1449                                         u16_writer : null_writer;\r
1450                         spi_dfs = SPI_DFS_16BIT;\r
1451                         break;\r
1452                 default:\r
1453                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1454                                 "%db\n", bits);\r
1455                         message->status = -EIO;\r
1456                         goto early_exit;\r
1457                 }\r
1458 \r
1459                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1460                         | (chip->type << SPI_FRF_OFFSET)\r
1461                         | (spi->mode << SPI_MODE_OFFSET)\r
1462                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1463         }\r
1464         message->state = RUNNING_STATE;\r
1465  \r
1466         /*\r
1467          * Adjust transfer mode if necessary. Requires platform dependent\r
1468          * chipselect mechanism.\r
1469          */\r
1470         if (dws->cs_control) {\r
1471                 if (dws->rx && dws->tx)\r
1472                         chip->tmode = SPI_TMOD_TR;\r
1473                 else if (dws->rx)\r
1474                         chip->tmode = SPI_TMOD_RO;\r
1475                 else\r
1476                         chip->tmode = SPI_TMOD_TO;\r
1477 \r
1478                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1479                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1480         }\r
1481         \r
1482         /* Check if current transfer is a DMA transaction */\r
1483         dws->dma_mapped = map_dma_buffers(dws);\r
1484 \r
1485         /*\r
1486          * Reprogram registers only if\r
1487          *      1. chip select changes\r
1488          *      2. clk_div is changed\r
1489          *      3. control value changes\r
1490          */\r
1491         spi_enable_chip(dws, 0);\r
1492         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)\r
1493                 rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
1494 \r
1495     DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);\r
1496         spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1497         spi_chip_sel(dws, spi->chip_select);            \r
1498         rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx\r
1499         if(dws->dma_mapped ) {\r
1500                 dmacr = rk29xx_readw(dws, SPIM_DMACR);\r
1501                 dmacr = dmacr | SPI_DMACR_TX_ENABLE;\r
1502                 if (mode) \r
1503                         dmacr = dmacr | SPI_DMACR_RX_ENABLE;\r
1504                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1505         }\r
1506         spi_enable_chip(dws, 1);\r
1507         if (cs_change)\r
1508                 dws->prev_chip = chip;\r
1509         \r
1510         if (mode)\r
1511                 return do_full_transfer(dws);\r
1512         else\r
1513                 return do_half_transfer(dws);   \r
1514         \r
1515 early_exit:\r
1516         \r
1517         //msg_giveback(dws);\r
1518         \r
1519         return 0;\r
1520 }\r
1521 \r
1522 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)\r
1523 {\r
1524         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1525         \r
1526         while (!acquire_dma(dws))\r
1527                         msleep(10);\r
1528 \r
1529         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1530                 dws->busy = 0;\r
1531                 return;\r
1532         }\r
1533 \r
1534         /* Make sure we are not already running a message */\r
1535         if (dws->cur_msg) {\r
1536                 return;\r
1537         }\r
1538 \r
1539         /* Extract head of queue */\r
1540         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1541         list_del_init(&dws->cur_msg->queue);\r
1542 \r
1543         /* Initial message state*/\r
1544         dws->cur_msg->state = START_STATE;\r
1545         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1546                                                 struct spi_transfer,\r
1547                                                 transfer_list);\r
1548         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1549     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1550     \r
1551         /* Mark as busy and launch transfers */\r
1552         dws->busy = 1;\r
1553 \r
1554         while (rk29xx_pump_transfers(dws, mode)) ;\r
1555 }\r
1556 \r
1557 /* spi_device use this to queue in their spi_msg */\r
1558 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)\r
1559 {\r
1560         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1561         unsigned long flags;\r
1562         struct rk29xx_spi_chip *chip_info = spi->controller_data;\r
1563         struct spi_message *mmsg;\r
1564         \r
1565         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1566         \r
1567         spin_lock_irqsave(&dws->lock, flags);\r
1568 \r
1569         if (dws->run == QUEUE_STOPPED) {\r
1570                 spin_unlock_irqrestore(&dws->lock, flags);\r
1571                 return -ESHUTDOWN;\r
1572         }\r
1573 \r
1574         msg->actual_length = 0;\r
1575         msg->status = -EINPROGRESS;\r
1576         msg->state = START_STATE;\r
1577 \r
1578         list_add_tail(&msg->queue, &dws->queue);\r
1579 \r
1580         if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {\r
1581                 rk29xx_pump_messages(dws,1);\r
1582         }\r
1583         else {          \r
1584                 rk29xx_pump_messages(dws,0);\r
1585         }\r
1586 \r
1587         mmsg = dws->cur_msg;\r
1588         msg_giveback(dws);\r
1589         \r
1590         spin_unlock_irqrestore(&dws->lock, flags);\r
1591 \r
1592         if (mmsg->complete)\r
1593                 mmsg->complete(mmsg->context);\r
1594         \r
1595         return 0;\r
1596 }\r
1597 \r
1598 #else\r
1599 \r
1600 /* spi_device use this to queue in their spi_msg */\r
1601 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)\r
1602 {\r
1603         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1604         unsigned long flags;\r
1605 \r
1606         spin_lock_irqsave(&dws->lock, flags);\r
1607 \r
1608         if (dws->run == QUEUE_STOPPED) {\r
1609                 spin_unlock_irqrestore(&dws->lock, flags);\r
1610                 return -ESHUTDOWN;\r
1611         }\r
1612 \r
1613         msg->actual_length = 0;\r
1614         msg->status = -EINPROGRESS;\r
1615         msg->state = START_STATE;\r
1616 \r
1617         list_add_tail(&msg->queue, &dws->queue);\r
1618 \r
1619         if (dws->run == QUEUE_RUNNING && !dws->busy) {\r
1620 \r
1621                 if (dws->cur_transfer || dws->cur_msg)\r
1622                         queue_work(dws->workqueue,\r
1623                                         &dws->pump_messages);\r
1624                 else {\r
1625                         /* If no other data transaction in air, just go */\r
1626                         spin_unlock_irqrestore(&dws->lock, flags);\r
1627                         pump_messages(&dws->pump_messages);                     \r
1628                         return 0;\r
1629                 }\r
1630         }\r
1631 \r
1632         spin_unlock_irqrestore(&dws->lock, flags);\r
1633         \r
1634         return 0;\r
1635 }\r
1636 \r
1637 #endif\r
1638 \r
1639 /* This may be called twice for each spi dev */\r
1640 static int rk29xx_spi_setup(struct spi_device *spi)\r
1641 {\r
1642         struct rk29xx_spi_chip *chip_info = NULL;\r
1643         struct chip_data *chip;\r
1644         u8 spi_dfs = 0;\r
1645 \r
1646         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)\r
1647                 return -EINVAL;\r
1648 \r
1649         /* Only alloc on first setup */\r
1650         chip = spi_get_ctldata(spi);\r
1651         if (!chip) {\r
1652                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\r
1653                 if (!chip)\r
1654                         return -ENOMEM;\r
1655 \r
1656                 chip->cs_control = spi_cs_control;\r
1657                 chip->enable_dma = 0;  //0;\r
1658         }\r
1659 \r
1660         /*\r
1661          * Protocol drivers may change the chip settings, so...\r
1662          * if chip_info exists, use it\r
1663          */\r
1664         chip_info = spi->controller_data;\r
1665 \r
1666         /* chip_info doesn't always exist */\r
1667         if (chip_info) {\r
1668                 if (chip_info->cs_control)\r
1669                         chip->cs_control = chip_info->cs_control;\r
1670 \r
1671                 chip->poll_mode = chip_info->poll_mode;\r
1672                 chip->type = chip_info->type;\r
1673 \r
1674                 chip->rx_threshold = 0;\r
1675                 chip->tx_threshold = 0;\r
1676 \r
1677                 chip->enable_dma = chip_info->enable_dma;\r
1678         }\r
1679 \r
1680         if (spi->bits_per_word == 8) {\r
1681                 chip->n_bytes = 1;\r
1682                 chip->dma_width = 1;\r
1683                 chip->read = u8_reader;\r
1684                 chip->write = u8_writer;\r
1685                 spi_dfs = SPI_DFS_8BIT;\r
1686         } else if (spi->bits_per_word == 16) {\r
1687                 chip->n_bytes = 2;\r
1688                 chip->dma_width = 2;\r
1689                 chip->read = u16_reader;\r
1690                 chip->write = u16_writer;\r
1691                 spi_dfs = SPI_DFS_16BIT;\r
1692         } else {\r
1693                 /* Never take >16b case for MRST SPIC */\r
1694                 dev_err(&spi->dev, "invalid wordsize\n");\r
1695                 return -EINVAL;\r
1696         }\r
1697         chip->bits_per_word = spi->bits_per_word;\r
1698 \r
1699         if (!spi->max_speed_hz) {\r
1700                 dev_err(&spi->dev, "No max speed HZ parameter\n");\r
1701                 return -EINVAL;\r
1702         }\r
1703         chip->speed_hz = spi->max_speed_hz;\r
1704 \r
1705         chip->tmode = 0; /* Tx & Rx */\r
1706         /* Default SPI mode is SCPOL = 0, SCPH = 0 */\r
1707         chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1708                 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1709                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1710                         | (chip->type << SPI_FRF_OFFSET)\r
1711                         | (spi->mode  << SPI_MODE_OFFSET)\r
1712                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1713 \r
1714         spi_set_ctldata(spi, chip);\r
1715         return 0;\r
1716 }\r
1717 \r
1718 static void rk29xx_spi_cleanup(struct spi_device *spi)\r
1719 {\r
1720         struct chip_data *chip = spi_get_ctldata(spi);\r
1721         kfree(chip);\r
1722 }\r
1723 \r
1724 static int __devinit init_queue(struct rk29xx_spi *dws)\r
1725 {\r
1726         INIT_LIST_HEAD(&dws->queue);\r
1727         spin_lock_init(&dws->lock);\r
1728 \r
1729         dws->run = QUEUE_STOPPED;\r
1730         dws->busy = 0;\r
1731 \r
1732         init_completion(&dws->xfer_completion);\r
1733 \r
1734         tasklet_init(&dws->pump_transfers,\r
1735                         pump_transfers, (unsigned long)dws);\r
1736 \r
1737         INIT_WORK(&dws->pump_messages, pump_messages);\r
1738         dws->workqueue = create_singlethread_workqueue(\r
1739                                         dev_name(dws->master->dev.parent));\r
1740         if (dws->workqueue == NULL)\r
1741                 return -EBUSY;\r
1742 \r
1743 \r
1744         return 0;\r
1745 }\r
1746 \r
1747 static int start_queue(struct rk29xx_spi *dws)\r
1748 {\r
1749         unsigned long flags;\r
1750 \r
1751         spin_lock_irqsave(&dws->lock, flags);\r
1752 \r
1753         if (dws->run == QUEUE_RUNNING || dws->busy) {\r
1754                 spin_unlock_irqrestore(&dws->lock, flags);\r
1755                 return -EBUSY;\r
1756         }\r
1757 \r
1758         dws->run = QUEUE_RUNNING;\r
1759         dws->cur_msg = NULL;\r
1760         dws->cur_transfer = NULL;\r
1761         dws->cur_chip = NULL;\r
1762         dws->prev_chip = NULL;\r
1763         spin_unlock_irqrestore(&dws->lock, flags);\r
1764 \r
1765         queue_work(dws->workqueue, &dws->pump_messages);\r
1766 \r
1767         return 0;\r
1768 }\r
1769 \r
1770 static int stop_queue(struct rk29xx_spi *dws)\r
1771 {\r
1772         unsigned long flags;\r
1773         unsigned limit = 50;\r
1774         int status = 0;\r
1775 \r
1776         spin_lock_irqsave(&dws->lock, flags);\r
1777         dws->run = QUEUE_STOPPED;\r
1778         while (!list_empty(&dws->queue) && dws->busy && limit--) {\r
1779                 spin_unlock_irqrestore(&dws->lock, flags);\r
1780                 msleep(10);\r
1781                 spin_lock_irqsave(&dws->lock, flags);\r
1782         }\r
1783 \r
1784         if (!list_empty(&dws->queue) || dws->busy)\r
1785                 status = -EBUSY;\r
1786         spin_unlock_irqrestore(&dws->lock, flags);\r
1787 \r
1788         return status;\r
1789 }\r
1790 \r
1791 static int destroy_queue(struct rk29xx_spi *dws)\r
1792 {\r
1793         int status;\r
1794 \r
1795         status = stop_queue(dws);\r
1796         if (status != 0)\r
1797                 return status;\r
1798         destroy_workqueue(dws->workqueue);\r
1799         return 0;\r
1800 }\r
1801 \r
1802 /* Restart the controller, disable all interrupts, clean rx fifo */\r
1803 static void spi_hw_init(struct rk29xx_spi *dws)\r
1804 {\r
1805         spi_enable_chip(dws, 0);\r
1806         spi_mask_intr(dws, 0xff);\r
1807         \r
1808         /*\r
1809          * Try to detect the FIFO depth if not set by interface driver,\r
1810          * the depth could be from 2 to 32 from HW spec\r
1811          */\r
1812         if (!dws->fifo_len) {\r
1813                 u32 fifo;\r
1814                 for (fifo = 2; fifo <= 31; fifo++) {\r
1815                         rk29xx_writew(dws, SPIM_TXFTLR, fifo);\r
1816                         if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))\r
1817                                 break;\r
1818                 }\r
1819 \r
1820                 dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
1821                 rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
1822         }\r
1823         \r
1824         spi_enable_chip(dws, 1);\r
1825         //flush(dws);\r
1826 }\r
1827 \r
1828 /* cpufreq driver support */\r
1829 #ifdef CONFIG_CPU_FREQ\r
1830 \r
1831 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)\r
1832 {\r
1833         struct rk29xx_spi *info;\r
1834         unsigned long newclk;\r
1835 \r
1836         info = container_of(nb, struct rk29xx_spi, freq_transition);\r
1837         newclk = clk_get_rate(info->clock_spim);\r
1838 \r
1839         return 0;\r
1840 }\r
1841 \r
1842 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1843 {\r
1844         info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;\r
1845 \r
1846         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1847 }\r
1848 \r
1849 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1850 {\r
1851         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1852 }\r
1853 \r
1854 #else\r
1855 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1856 {\r
1857         return 0;\r
1858 }\r
1859 \r
1860 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1861 {\r
1862 }\r
1863 #endif\r
1864 static int __init rk29xx_spim_probe(struct platform_device *pdev)\r
1865 {\r
1866         struct resource         *regs, *dmatx_res, *dmarx_res;\r
1867         struct rk29xx_spi   *dws;\r
1868         struct spi_master   *master;\r
1869         int                     irq; \r
1870         int ret;\r
1871         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
1872 \r
1873         if (pdata && pdata->io_init) {\r
1874                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
1875                 if (ret) {                      \r
1876                         return -ENXIO;  \r
1877                 }\r
1878         }\r
1879         \r
1880         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1881         if (!regs)\r
1882                 return -ENXIO;\r
1883         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);\r
1884         if (dmatx_res == NULL) {\r
1885                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");\r
1886                 return -ENXIO;\r
1887         }\r
1888 \r
1889         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);\r
1890         if (dmarx_res == NULL) {\r
1891                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");\r
1892                 return -ENXIO;\r
1893         }\r
1894         irq = platform_get_irq(pdev, 0);\r
1895         if (irq < 0)\r
1896                 return irq;                     \r
1897         /* setup spi core then atmel-specific driver state */\r
1898         ret = -ENOMEM;  \r
1899         master = spi_alloc_master(&pdev->dev, sizeof *dws);\r
1900         if (!master) {\r
1901                 ret = -ENOMEM;\r
1902                 goto exit;\r
1903         }\r
1904 \r
1905         platform_set_drvdata(pdev, master);\r
1906         dws = spi_master_get_devdata(master);\r
1907         dws->clock_spim = clk_get(&pdev->dev, "spi");\r
1908         clk_enable(dws->clock_spim);\r
1909         if (IS_ERR(dws->clock_spim)) {\r
1910                 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
1911                 return PTR_ERR(dws->clock_spim);\r
1912         }\r
1913         \r
1914         mutex_init(&dws->dma_lock);\r
1915         \r
1916         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);\r
1917         if (!dws->regs){\r
1918         release_mem_region(regs->start, (regs->end - regs->start) + 1);\r
1919                 return -EBUSY;\r
1920         }\r
1921         DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
1922         dws->irq = irq;\r
1923         dws->irq_polarity = IRQF_TRIGGER_NONE;\r
1924         dws->master = master;\r
1925         dws->type = SSI_MOTO_SPI;\r
1926         dws->prev_chip = NULL;\r
1927         dws->sfr_start = regs->start;\r
1928         dws->tx_dmach = dmatx_res->start;\r
1929         dws->rx_dmach = dmarx_res->start;\r
1930         dws->dma_inited = 0;  ///0;\r
1931         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);\r
1932         ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,\r
1933                         "rk29xx_spim", dws);\r
1934         if (ret < 0) {\r
1935                 dev_err(&master->dev, "can not get IRQ\n");\r
1936                 goto err_free_master;\r
1937         }\r
1938 \r
1939         master->mode_bits = SPI_CPOL | SPI_CPHA;\r
1940         master->bus_num = pdev->id;\r
1941         master->num_chipselect = pdata->num_chipselect;\r
1942         master->dev.platform_data = pdata;\r
1943         master->cleanup = rk29xx_spi_cleanup;\r
1944         master->setup = rk29xx_spi_setup;\r
1945         #if defined(QUICK_TRANSFER)\r
1946         master->transfer = rk29xx_spi_quick_transfer;\r
1947         #else\r
1948         master->transfer = rk29xx_spi_transfer;\r
1949         #endif\r
1950         \r
1951         dws->pdev = pdev;\r
1952         /* Basic HW init */\r
1953         spi_hw_init(dws);\r
1954         flush(dws);\r
1955         /* Initial and start queue */\r
1956         ret = init_queue(dws);\r
1957         if (ret) {\r
1958                 dev_err(&master->dev, "problem initializing queue\n");\r
1959                 goto err_diable_hw;\r
1960         }\r
1961 \r
1962         ret = start_queue(dws);\r
1963         if (ret) {\r
1964                 dev_err(&master->dev, "problem starting queue\n");\r
1965                 goto err_diable_hw;\r
1966         }\r
1967 \r
1968         spi_master_set_devdata(master, dws);\r
1969         ret = spi_register_master(master);\r
1970         if (ret) {\r
1971                 dev_err(&master->dev, "problem registering spi master\n");\r
1972                 goto err_queue_alloc;\r
1973         }\r
1974 \r
1975     ret =rk29xx_spim_cpufreq_register(dws);\r
1976     if (ret < 0) {\r
1977         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
1978         goto err_queue_alloc;\r
1979     }\r
1980         printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);\r
1981         mrst_spi_debugfs_init(dws);\r
1982         return 0;\r
1983 \r
1984 err_queue_alloc:\r
1985         destroy_queue(dws);\r
1986 err_diable_hw:\r
1987         spi_enable_chip(dws, 0);\r
1988         free_irq(dws->irq, dws);\r
1989 err_free_master:\r
1990         spi_master_put(master);\r
1991         iounmap(dws->regs);\r
1992 exit:\r
1993         return ret;\r
1994 }\r
1995 \r
1996 static void __exit rk29xx_spim_remove(struct platform_device *pdev)\r
1997 {\r
1998         struct spi_master *master = platform_get_drvdata(pdev);\r
1999         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2000         int status = 0;\r
2001 \r
2002         if (!dws)\r
2003                 return;\r
2004         rk29xx_spim_cpufreq_deregister(dws);\r
2005         mrst_spi_debugfs_remove(dws);\r
2006 \r
2007         if(dws->buffer_tx_dma)\r
2008         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_tx_dma, dws->tx_dma);\r
2009         if(dws->buffer_rx_dma)\r
2010         dma_free_coherent(&pdev->dev, DMA_BUFFER_SIZE, dws->buffer_rx_dma, dws->rx_dma);\r
2011         release_dma(dws);\r
2012 \r
2013         /* Remove the queue */\r
2014         status = destroy_queue(dws);\r
2015         if (status != 0)\r
2016                 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "\r
2017                         "complete, message memory not freed\n");\r
2018         clk_put(dws->clock_spim);\r
2019         clk_disable(dws->clock_spim);\r
2020         spi_enable_chip(dws, 0);\r
2021         /* Disable clk */\r
2022         spi_set_clk(dws, 0);\r
2023         free_irq(dws->irq, dws);\r
2024 \r
2025         /* Disconnect from the SPI framework */\r
2026         spi_unregister_master(dws->master);\r
2027         iounmap(dws->regs);\r
2028 }\r
2029 \r
2030 \r
2031 #ifdef  CONFIG_PM\r
2032 \r
2033 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)\r
2034 {\r
2035         struct spi_master *master = platform_get_drvdata(pdev);\r
2036         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2037         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2038         int status;\r
2039         \r
2040         flush(dws);\r
2041         status = stop_queue(dws);\r
2042         if (status != 0)\r
2043                 return status;\r
2044         clk_disable(dws->clock_spim);\r
2045         if (pdata && pdata->io_fix_leakage_bug)\r
2046         {\r
2047                 pdata->io_fix_leakage_bug( );\r
2048         }\r
2049         return 0;\r
2050 }\r
2051 \r
2052 static int rk29xx_spim_resume(struct platform_device *pdev)\r
2053 {\r
2054         struct spi_master *master = platform_get_drvdata(pdev);\r
2055         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2056         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2057         int ret;\r
2058         \r
2059         clk_enable(dws->clock_spim);    \r
2060         spi_hw_init(dws);\r
2061         ret = start_queue(dws);\r
2062         if (ret)\r
2063                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);\r
2064         if (pdata && pdata->io_resume_leakage_bug)\r
2065         {\r
2066                 pdata->io_resume_leakage_bug( ); \r
2067         }\r
2068         return ret;\r
2069 }\r
2070 \r
2071 #else\r
2072 #define rk29xx_spim_suspend     NULL\r
2073 #define rk29xx_spim_resume      NULL\r
2074 #endif\r
2075 \r
2076 static struct platform_driver rk29xx_platform_spim_driver = {\r
2077         .remove         = __exit_p(rk29xx_spim_remove),\r
2078         .driver         = {\r
2079                 .name   = "rk29xx_spim",\r
2080                 .owner  = THIS_MODULE,\r
2081         },\r
2082         .suspend        = rk29xx_spim_suspend,\r
2083         .resume         = rk29xx_spim_resume,\r
2084 };\r
2085 \r
2086 static int __init rk29xx_spim_init(void)\r
2087 {\r
2088         int ret;\r
2089         ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);   \r
2090         return ret;\r
2091 }\r
2092 \r
2093 static void __exit rk29xx_spim_exit(void)\r
2094 {\r
2095         platform_driver_unregister(&rk29xx_platform_spim_driver);\r
2096 }\r
2097 \r
2098 arch_initcall_sync(rk29xx_spim_init);\r
2099 module_exit(rk29xx_spim_exit);\r
2100 \r
2101 MODULE_AUTHOR("www.rock-chips.com");\r
2102 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");\r
2103 MODULE_LICENSE("GPL");;\r
2104 \r