drivers/spi/rk29_spim.c

   1 /*drivers/serial/rk29xx_spim.c - driver for rk29xx spim device \r
   2  *\r
   3  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   4  *\r
   5  * This software is licensed under the terms of the GNU General Public\r
   6  * License version 2, as published by the Free Software Foundation, and\r
   7  * may be copied, distributed, and modified under those terms.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful,\r
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  12  * GNU General Public License for more details.\r
  13  */\r
  14 \r
  15 #include <linux/dma-mapping.h>\r
  16 #include <linux/interrupt.h>\r
  17 #include <linux/highmem.h>\r
  18 #include <linux/delay.h>\r
  19 #include <linux/slab.h>\r
  20 #include <linux/platform_device.h>\r
  21 #include <linux/clk.h>\r
  22 #include <linux/cpufreq.h>\r
  23 #include <mach/gpio.h>\r
  24 #include <mach/irqs.h>\r
  25 #include <linux/dma-mapping.h>\r
  26 #include <asm/dma.h>\r
  27 #include <linux/preempt.h>\r
  28 #include "rk29_spim.h"\r
  29 #include <linux/spi/spi.h>\r
  30 #include <mach/board.h>\r
  31 \r
  32 #ifdef CONFIG_DEBUG_FS\r
  33 #include <linux/debugfs.h>\r
  34 #endif\r
  35 \r
  36 /*ÔÓÐµÄspiÇý¶¯Ð§ÂÊ±È½ÏµÍ£¬\r
  37 ÎÞ·¨Âú×ã´óÊý¾ÝÁ¿µÄ´«Êä£»\r
  38 QUICK_TRANSFERÓÃÓÚ¿ìËÙ´«Êä£¬Í¬Ê±¿ÉÖ¸¶¨°ëË«¹¤»òÈ«Ë«¹¤£¬\r
  39 Ä¬ÈÏÊ¹ÓÃ°ëË«¹¤\r
  40 */\r
  41 \r
  42 //#define QUICK_TRANSFER         \r
  43 \r
  44 #if 0\r
  45 #define DBG   printk\r
  46 #else\r
  47 #define DBG(x...)\r
  48 #endif\r
  49 \r
  50 #define DMA_MIN_BYTES 8\r
  51 \r
  52 \r
  53 #define START_STATE     ((void *)0)\r
  54 #define RUNNING_STATE   ((void *)1)\r
  55 #define DONE_STATE      ((void *)2)\r
  56 #define ERROR_STATE     ((void *)-1)\r
  57 \r
  58 #define QUEUE_RUNNING   0\r
  59 #define QUEUE_STOPPED   1\r
  60 \r
  61 #define MRST_SPI_DEASSERT       0\r
  62 #define MRST_SPI_ASSERT         1  ///CS0\r
  63 #define MRST_SPI_ASSERT1        2  ///CS1\r
  64 \r
  65 /* Slave spi_dev related */\r
  66 struct chip_data {\r
  67         u16 cr0;\r
  68         u8 cs;                  /* chip select pin */\r
  69         u8 n_bytes;             /* current is a 1/2/4 byte op */\r
  70         u8 tmode;               /* TR/TO/RO/EEPROM */\r
  71         u8 type;                /* SPI/SSP/MicroWire */\r
  72 \r
  73         u8 poll_mode;           /* 1 means use poll mode */\r
  74 \r
  75         u32 dma_width;\r
  76         u32 rx_threshold;\r
  77         u32 tx_threshold;\r
  78         u8 enable_dma:1;\r
  79         u8 bits_per_word;\r
  80         u16 clk_div;            /* baud rate divider */\r
  81         u32 speed_hz;           /* baud rate */\r
  82         int (*write)(struct rk29xx_spi *dws);\r
  83         int (*read)(struct rk29xx_spi *dws);\r
  84         void (*cs_control)(struct rk29xx_spi *dws, u32 cs, u8 flag);\r
  85 };\r
  86 \r
  87 #define SUSPND    (1<<0)\r
  88 #define SPIBUSY   (1<<1)\r
  89 #define RXBUSY    (1<<2)\r
  90 #define TXBUSY    (1<<3)\r
  91 \r
  92 //\r
  93 #ifdef CONFIG_LCD_USE_SPIM_CONTROL\r
  94 void rk29_lcd_spim_spin_lock(void)\r
  95 {\r
  96 #ifdef CONFIG_LCD_USE_SPI0\r
  97         disable_irq(IRQ_SPI0);\r
  98 #endif\r
  99 \r
 100 #ifdef CONFIG_LCD_USE_SPI1\r
 101         disable_irq(IRQ_SPI1);\r
 102 #endif\r
 103 \r
 104         preempt_disable();\r
 105 }\r
 106 \r
 107 void rk29_lcd_spim_spin_unlock(void)\r
 108 {\r
 109         preempt_enable();\r
 110         \r
 111 #ifdef CONFIG_LCD_USE_SPI0\r
 112         enable_irq(IRQ_SPI0);\r
 113 #endif\r
 114 \r
 115 #ifdef CONFIG_LCD_USE_SPI1\r
 116         enable_irq(IRQ_SPI1);\r
 117 #endif\r
 118 }\r
 119 #else\r
 120 void rk29_lcd_spim_spin_lock(void)\r
 121 {\r
 122      return;\r
 123 }\r
 124 \r
 125 void rk29_lcd_spim_spin_unlock(void)\r
 126 {\r
 127      return;\r
 128 }\r
 129 #endif\r
 130 \r
 131 \r
 132 static void spi_dump_regs(struct rk29xx_spi *dws) {\r
 133         DBG("MRST SPI0 registers:\n");\r
 134         DBG("=================================\n");\r
 135         DBG("CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 136         DBG("CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 137         DBG("SSIENR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 138         DBG("SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 139         DBG("BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 140         DBG("TXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 141         DBG("RXFTLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 142         DBG("TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 143         DBG("RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 144         DBG("SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 145         DBG("IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 146         DBG("ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 147         DBG("DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 148         DBG("DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 149         DBG("DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 150         DBG("=================================\n");\r
 151 \r
 152 }\r
 153 \r
 154 #ifdef CONFIG_DEBUG_FS\r
 155 static int spi_show_regs_open(struct inode *inode, struct file *file)\r
 156 {\r
 157         file->private_data = inode->i_private;\r
 158         return 0;\r
 159 }\r
 160 \r
 161 #define SPI_REGS_BUFSIZE        1024\r
 162 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,\r
 163                                 size_t count, loff_t *ppos)\r
 164 {\r
 165         struct rk29xx_spi *dws;\r
 166         char *buf;\r
 167         u32 len = 0;\r
 168         ssize_t ret;\r
 169 \r
 170         dws = file->private_data;\r
 171 \r
 172         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);\r
 173         if (!buf)\r
 174                 return 0;\r
 175 \r
 176         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 177                         "MRST SPI0 registers:\n");\r
 178         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 179                         "=================================\n");\r
 180         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 181                         "CTRL0: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR0));\r
 182         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 183                         "CTRL1: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_CTRLR1));\r
 184         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 185                         "SSIENR: \t0x%08x\n", rk29xx_readl(dws, SPIM_ENR));\r
 186         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 187                         "SER: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SER));\r
 188         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 189                         "BAUDR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_BAUDR));\r
 190         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 191                         "TXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_TXFTLR));\r
 192         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 193                         "RXFTLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_RXFTLR));\r
 194         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 195                         "TXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_TXFLR));\r
 196         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 197                         "RXFLR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_RXFLR));\r
 198         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 199                         "SR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_SR));\r
 200         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 201                         "IMR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_IMR));\r
 202         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 203                         "ISR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_ISR));\r
 204         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 205                         "DMACR: \t\t0x%08x\n", rk29xx_readl(dws, SPIM_DMACR));\r
 206         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 207                         "DMATDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMATDLR));\r
 208         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 209                         "DMARDLR: \t0x%08x\n", rk29xx_readl(dws, SPIM_DMARDLR));\r
 210         len += printk(buf + len, SPI_REGS_BUFSIZE - len,\r
 211                         "=================================\n");\r
 212 \r
 213         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);\r
 214         kfree(buf);\r
 215         return ret;\r
 216 }\r
 217 \r
 218 static const struct file_operations mrst_spi_regs_ops = {\r
 219         .owner          = THIS_MODULE,\r
 220         .open           = spi_show_regs_open,\r
 221         .read           = spi_show_regs,\r
 222 };\r
 223 \r
 224 static int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 225 {\r
 226         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);\r
 227         if (!dws->debugfs)\r
 228                 return -ENOMEM;\r
 229 \r
 230         debugfs_create_file("registers", S_IFREG | S_IRUGO,\r
 231                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);\r
 232         return 0;\r
 233 }\r
 234 \r
 235 static void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 236 {\r
 237         if (dws->debugfs)\r
 238                 debugfs_remove_recursive(dws->debugfs);\r
 239 }\r
 240 \r
 241 #else\r
 242 static inline int mrst_spi_debugfs_init(struct rk29xx_spi *dws)\r
 243 {\r
 244         return 0;\r
 245 }\r
 246 \r
 247 static inline void mrst_spi_debugfs_remove(struct rk29xx_spi *dws)\r
 248 {\r
 249 }\r
 250 #endif /* CONFIG_DEBUG_FS */\r
 251 \r
 252 static void wait_till_not_busy(struct rk29xx_spi *dws)\r
 253 {\r
 254         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 255 \r
 256         while (time_before(jiffies, end)) {\r
 257                 if (!(rk29xx_readw(dws, SPIM_SR) & SR_BUSY))\r
 258                         return;\r
 259         }\r
 260         dev_err(&dws->master->dev,\r
 261                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 262 }\r
 263 \r
 264 #if defined(QUICK_TRANSFER)\r
 265 static void wait_till_tf_empty(struct rk29xx_spi *dws)\r
 266 {\r
 267         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);\r
 268 \r
 269         while (time_before(jiffies, end)) {\r
 270                 if (rk29xx_readw(dws, SPIM_SR) & SR_TF_EMPT)\r
 271                         return;\r
 272         }\r
 273         dev_err(&dws->master->dev,\r
 274                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");\r
 275 }\r
 276 #endif\r
 277 \r
 278 static void flush(struct rk29xx_spi *dws)\r
 279 {\r
 280         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 281                 rk29xx_readw(dws, SPIM_RXDR);\r
 282 \r
 283         wait_till_not_busy(dws);\r
 284 }\r
 285 \r
 286 static void spi_cs_control(struct rk29xx_spi *dws, u32 cs, u8 flag)\r
 287 {\r
 288         #if 1\r
 289         if (flag)\r
 290                 rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 291         else            \r
 292                 rk29xx_writel(dws, SPIM_SER, 0);\r
 293         return;\r
 294         #else\r
 295         struct rk29xx_spi_platform_data *pdata = dws->master->dev.platform_data;\r
 296         struct spi_cs_gpio *cs_gpios = pdata->chipselect_gpios;\r
 297 \r
 298         if (flag == 0) {\r
 299                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_HIGH);\r
 300         }\r
 301         else {\r
 302                 gpio_direction_output(cs_gpios[cs].cs_gpio, GPIO_LOW);\r
 303         }\r
 304         #endif\r
 305 }\r
 306 \r
 307 static int null_writer(struct rk29xx_spi *dws)\r
 308 {\r
 309         u8 n_bytes = dws->n_bytes;\r
 310 \r
 311         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 312                 || (dws->tx == dws->tx_end))\r
 313                 return 0;\r
 314         rk29xx_writew(dws, SPIM_TXDR, 0);\r
 315         dws->tx += n_bytes;\r
 316         //wait_till_not_busy(dws);\r
 317 \r
 318         return 1;\r
 319 }\r
 320 \r
 321 static int null_reader(struct rk29xx_spi *dws)\r
 322 {\r
 323         u8 n_bytes = dws->n_bytes;\r
 324         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 325         while ((!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT))\r
 326                 && (dws->rx < dws->rx_end)) {\r
 327                 rk29xx_readw(dws, SPIM_RXDR);\r
 328                 dws->rx += n_bytes;\r
 329         }\r
 330         wait_till_not_busy(dws);\r
 331         return dws->rx == dws->rx_end;\r
 332 }\r
 333 \r
 334 static int u8_writer(struct rk29xx_spi *dws)\r
 335 {       \r
 336         spi_dump_regs(dws);\r
 337         DBG("tx: 0x%02x\n", *(u8 *)(dws->tx));\r
 338         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 339                 || (dws->tx == dws->tx_end))\r
 340                 return 0;\r
 341         rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));\r
 342         ++dws->tx;\r
 343         //wait_till_not_busy(dws);\r
 344 \r
 345         return 1;\r
 346 }\r
 347 \r
 348 static int u8_reader(struct rk29xx_spi *dws)\r
 349 {\r
 350     spi_dump_regs(dws);\r
 351         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 352                 && (dws->rx < dws->rx_end)) {\r
 353                 *(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;\r
 354                 DBG("rx: 0x%02x\n", *(u8 *)(dws->rx));\r
 355                 ++dws->rx;\r
 356         }\r
 357 \r
 358         wait_till_not_busy(dws);\r
 359         return dws->rx == dws->rx_end;\r
 360 }\r
 361 \r
 362 static int u16_writer(struct rk29xx_spi *dws)\r
 363 {\r
 364         if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)\r
 365                 || (dws->tx == dws->tx_end))\r
 366                 return 0;\r
 367 \r
 368         rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));\r
 369         dws->tx += 2;\r
 370         //wait_till_not_busy(dws);\r
 371 \r
 372         return 1;\r
 373 }\r
 374 \r
 375 static int u16_reader(struct rk29xx_spi *dws)\r
 376 {\r
 377         u16 temp;\r
 378 \r
 379         while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)\r
 380                 && (dws->rx < dws->rx_end)) {\r
 381                 temp = rk29xx_readw(dws, SPIM_RXDR);\r
 382                 *(u16 *)(dws->rx) = temp;\r
 383                 //DBG("rx: 0x%04x\n", *(u16 *)(dws->rx));\r
 384                 dws->rx += 2;\r
 385         }\r
 386 \r
 387         wait_till_not_busy(dws);\r
 388         return dws->rx == dws->rx_end;\r
 389 }\r
 390 \r
 391 static void *next_transfer(struct rk29xx_spi *dws)\r
 392 {\r
 393         struct spi_message *msg = dws->cur_msg;\r
 394         struct spi_transfer *trans = dws->cur_transfer;\r
 395 \r
 396         /* Move to next transfer */\r
 397         if (trans->transfer_list.next != &msg->transfers) {\r
 398                 dws->cur_transfer =\r
 399                         list_entry(trans->transfer_list.next,\r
 400                                         struct spi_transfer,\r
 401                                         transfer_list);\r
 402                 return RUNNING_STATE;\r
 403         } else\r
 404                 return DONE_STATE;\r
 405 }\r
 406 \r
 407 static void rk29_spi_dma_rxcb(void *buf_id,\r
 408                                  int size, enum rk29_dma_buffresult res)\r
 409 {\r
 410         struct rk29xx_spi *dws = buf_id;\r
 411         unsigned long flags;\r
 412 \r
 413         spin_lock_irqsave(&dws->lock, flags);\r
 414 \r
 415         if (res == RK29_RES_OK)\r
 416                 dws->state &= ~RXBUSY;\r
 417         else\r
 418                 dev_err(&dws->master->dev, "DmaAbrtRx-%d, size: %d\n", res, size);\r
 419 \r
 420         /* If the other done */\r
 421         if (!(dws->state & TXBUSY))\r
 422                 complete(&dws->xfer_completion);\r
 423 \r
 424         spin_unlock_irqrestore(&dws->lock, flags);\r
 425 }\r
 426 \r
 427 static void rk29_spi_dma_txcb(void *buf_id,\r
 428                                  int size, enum rk29_dma_buffresult res)\r
 429 {\r
 430         struct rk29xx_spi *dws = buf_id;\r
 431         unsigned long flags;\r
 432 \r
 433         DBG("func: %s, line: %d\n", __FUNCTION__, __LINE__);\r
 434 \r
 435         spin_lock_irqsave(&dws->lock, flags);\r
 436 \r
 437         if (res == RK29_RES_OK)\r
 438                 dws->state &= ~TXBUSY;\r
 439         else\r
 440                 dev_err(&dws->master->dev, "DmaAbrtTx-%d, size: %d \n", res, size);\r
 441 \r
 442         /* If the other done */\r
 443         if (!(dws->state & RXBUSY)) \r
 444                 complete(&dws->xfer_completion);\r
 445 \r
 446         spin_unlock_irqrestore(&dws->lock, flags);\r
 447 }\r
 448 \r
 449 \r
 450 static struct rk29_dma_client rk29_spi_dma_client = {\r
 451         .name = "rk29xx-spi-dma",\r
 452 };\r
 453 \r
 454 static int acquire_dma(struct rk29xx_spi *dws)\r
 455 {       \r
 456         if (dws->dma_inited) {\r
 457                 return 0;\r
 458         }\r
 459 \r
 460         if(rk29_dma_request(dws->rx_dmach, \r
 461                 &rk29_spi_dma_client, NULL) < 0) {\r
 462                 dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);\r
 463                 return -1;\r
 464         }\r
 465 \r
 466         if (rk29_dma_request(dws->tx_dmach,\r
 467                                         &rk29_spi_dma_client, NULL) < 0) {\r
 468                 dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);\r
 469                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 470                 return -1;\r
 471         }\r
 472         \r
 473     dws->dma_inited = 1;\r
 474         return 0;\r
 475 }\r
 476 \r
 477 static void release_dma(struct rk29xx_spi *dws)\r
 478 {\r
 479         if(!dws && dws->dma_inited) {\r
 480                 rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);\r
 481                 rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);\r
 482         }\r
 483 }\r
 484 \r
 485 /*\r
 486  * Note: first step is the protocol driver prepares\r
 487  * a dma-capable memory, and this func just need translate\r
 488  * the virt addr to physical\r
 489  */\r
 490 static int map_dma_buffers(struct rk29xx_spi *dws)\r
 491 {\r
 492         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited\r
 493                 || !dws->cur_chip->enable_dma)\r
 494                 return -1;\r
 495 \r
 496         if (dws->cur_transfer->tx_dma) {\r
 497                 dws->tx_dma = dws->cur_transfer->tx_dma;\r
 498                 if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {\r
 499                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 500                         return -1;\r
 501                 }\r
 502                 if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,\r
 503                                         dws->sfr_start + SPIM_TXDR)) {\r
 504                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 505                         return -1;\r
 506                 }\r
 507         }\r
 508 \r
 509         if (dws->cur_transfer->rx_dma) {\r
 510                 dws->rx_dma = dws->cur_transfer->rx_dma;\r
 511                 if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {\r
 512                         dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");\r
 513                         return -1;\r
 514                 }\r
 515                 if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,\r
 516                                         dws->sfr_start + SPIM_RXDR)) {\r
 517                         dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");\r
 518                         return -1;\r
 519                 }\r
 520         }\r
 521 \r
 522         return 0;\r
 523 }\r
 524 \r
 525 /* Caller already set message->status; dma and pio irqs are blocked */\r
 526 static void giveback(struct rk29xx_spi *dws)\r
 527 {\r
 528         struct spi_transfer *last_transfer;\r
 529         unsigned long flags;\r
 530         struct spi_message *msg;\r
 531 \r
 532         spin_lock_irqsave(&dws->lock, flags);\r
 533         msg = dws->cur_msg;\r
 534         dws->cur_msg = NULL;\r
 535         dws->cur_transfer = NULL;\r
 536         dws->prev_chip = dws->cur_chip;\r
 537         dws->cur_chip = NULL;\r
 538         dws->dma_mapped = 0;\r
 539         queue_work(dws->workqueue, &dws->pump_messages);\r
 540         spin_unlock_irqrestore(&dws->lock, flags);\r
 541 \r
 542         last_transfer = list_entry(msg->transfers.prev,\r
 543                                         struct spi_transfer,\r
 544                                         transfer_list);\r
 545 \r
 546         if (!last_transfer->cs_change && dws->cs_control)\r
 547                 dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);\r
 548 \r
 549         msg->state = NULL;\r
 550         if (msg->complete)\r
 551                 msg->complete(msg->context);\r
 552 }\r
 553 \r
 554 static void int_error_stop(struct rk29xx_spi *dws, const char *msg)\r
 555 {\r
 556         /* Stop and reset hw */\r
 557         flush(dws);\r
 558         spi_enable_chip(dws, 0);\r
 559 \r
 560         dev_err(&dws->master->dev, "%s\n", msg);\r
 561         dws->cur_msg->state = ERROR_STATE;\r
 562         tasklet_schedule(&dws->pump_transfers);\r
 563 }\r
 564 \r
 565 static void transfer_complete(struct rk29xx_spi *dws)\r
 566 {\r
 567         /* Update total byte transfered return count actual bytes read */\r
 568         dws->cur_msg->actual_length += dws->len;\r
 569 \r
 570         /* Move to next transfer */\r
 571         dws->cur_msg->state = next_transfer(dws);\r
 572 \r
 573         /* Handle end of message */\r
 574         if (dws->cur_msg->state == DONE_STATE) {\r
 575                 dws->cur_msg->status = 0;\r
 576                 giveback(dws);\r
 577         } else\r
 578                 tasklet_schedule(&dws->pump_transfers);\r
 579 }\r
 580 \r
 581 static irqreturn_t interrupt_transfer(struct rk29xx_spi *dws)\r
 582 {\r
 583         u16 irq_status, irq_mask = 0x1f;\r
 584         u32 int_level = dws->fifo_len / 2;\r
 585         u32 left;\r
 586         \r
 587         irq_status = rk29xx_readw(dws, SPIM_ISR) & irq_mask;\r
 588         /* Error handling */\r
 589         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {\r
 590                 rk29xx_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);\r
 591                 int_error_stop(dws, "interrupt_transfer: fifo overrun");\r
 592                 return IRQ_HANDLED;\r
 593         }\r
 594 \r
 595         if (irq_status & SPI_INT_TXEI) {\r
 596                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 597 \r
 598                 left = (dws->tx_end - dws->tx) / dws->n_bytes;\r
 599                 left = (left > int_level) ? int_level : left;\r
 600 \r
 601                 while (left--) {\r
 602                         dws->write(dws);\r
 603                         wait_till_not_busy(dws);\r
 604                 }\r
 605                 if (dws->rx) {\r
 606                     dws->read(dws);\r
 607                 }\r
 608 \r
 609                 /* Re-enable the IRQ if there is still data left to tx */\r
 610                 if (dws->tx_end > dws->tx)\r
 611                         spi_umask_intr(dws, SPI_INT_TXEI);\r
 612                 else\r
 613                         transfer_complete(dws);\r
 614         }\r
 615 \r
 616         if (irq_status & SPI_INT_RXFI) {\r
 617                 spi_mask_intr(dws, SPI_INT_RXFI);\r
 618                 \r
 619                 dws->read(dws);\r
 620 \r
 621                 /* Re-enable the IRQ if there is still data left to rx */\r
 622                 if (dws->rx_end > dws->rx) {\r
 623                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;\r
 624                     left = (left > int_level) ? int_level : left;\r
 625 \r
 626                         rk29xx_writew(dws, SPIM_RXFTLR, left);\r
 627                         spi_umask_intr(dws, SPI_INT_RXFI);\r
 628                 }\r
 629                 else {\r
 630                         transfer_complete(dws);\r
 631                 }\r
 632         }\r
 633 \r
 634         return IRQ_HANDLED;\r
 635 }\r
 636 \r
 637 static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)\r
 638 {\r
 639         struct rk29xx_spi *dws = dev_id;\r
 640 \r
 641         if (!dws->cur_msg) {\r
 642                 spi_mask_intr(dws, SPI_INT_TXEI);\r
 643                 /* Never fail */\r
 644                 return IRQ_HANDLED;\r
 645         }\r
 646 \r
 647         return dws->transfer_handler(dws);\r
 648 }\r
 649 \r
 650 /* Must be called inside pump_transfers() */\r
 651 static void poll_transfer(struct rk29xx_spi *dws)\r
 652 {\r
 653         while (dws->write(dws)) {\r
 654                 wait_till_not_busy(dws);\r
 655                 dws->read(dws);\r
 656         }\r
 657         transfer_complete(dws);\r
 658 }\r
 659 static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)\r
 660 {\r
 661     if(cs >= dws->master->num_chipselect)\r
 662                 return;\r
 663 \r
 664         if (dws->cs_control){\r
 665             dws->cs_control(dws, cs, MRST_SPI_ASSERT);\r
 666         }\r
 667         rk29xx_writel(dws, SPIM_SER, 1 << cs);\r
 668 }\r
 669 \r
 670 static void pump_transfers(unsigned long data)\r
 671 {\r
 672         struct rk29xx_spi *dws = (struct rk29xx_spi *)data;\r
 673         struct spi_message *message = NULL;\r
 674         struct spi_transfer *transfer = NULL;\r
 675         struct spi_transfer *previous = NULL;\r
 676         struct spi_device *spi = NULL;\r
 677         struct chip_data *chip = NULL;\r
 678         u8 bits = 0;\r
 679         u8 spi_dfs = 0;\r
 680         u8 imask = 0;\r
 681         u8 cs_change = 0;\r
 682         u16 txint_level = 0;\r
 683         u16 rxint_level = 0;\r
 684         u16 clk_div = 0;\r
 685         u32 speed = 0;\r
 686         u32 cr0 = 0;\r
 687 \r
 688         DBG(KERN_INFO "pump_transfers\n");\r
 689 \r
 690         /* Get current state information */\r
 691         message = dws->cur_msg;\r
 692         transfer = dws->cur_transfer;\r
 693         chip = dws->cur_chip;\r
 694         spi = message->spi;     \r
 695         if (unlikely(!chip->clk_div))\r
 696                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 697         if (message->state == ERROR_STATE) {\r
 698                 message->status = -EIO;\r
 699                 goto early_exit;\r
 700         }\r
 701 \r
 702         /* Handle end of message */\r
 703         if (message->state == DONE_STATE) {\r
 704                 message->status = 0;\r
 705                 goto early_exit;\r
 706         }\r
 707 \r
 708         /* Delay if requested at end of transfer*/\r
 709         if (message->state == RUNNING_STATE) {\r
 710                 previous = list_entry(transfer->transfer_list.prev,\r
 711                                         struct spi_transfer,\r
 712                                         transfer_list);\r
 713                 if (previous->delay_usecs)\r
 714                         udelay(previous->delay_usecs);\r
 715         }\r
 716 \r
 717         dws->n_bytes = chip->n_bytes;\r
 718         dws->dma_width = chip->dma_width;\r
 719         dws->cs_control = chip->cs_control;\r
 720 \r
 721         dws->rx_dma = transfer->rx_dma;\r
 722         dws->tx_dma = transfer->tx_dma;\r
 723         dws->tx = (void *)transfer->tx_buf;\r
 724         dws->tx_end = dws->tx + transfer->len;\r
 725         dws->rx = transfer->rx_buf;\r
 726         dws->rx_end = dws->rx + transfer->len;\r
 727         dws->write = dws->tx ? chip->write : null_writer;\r
 728         dws->read = dws->rx ? chip->read : null_reader;\r
 729         dws->cs_change = transfer->cs_change;\r
 730         dws->len = dws->cur_transfer->len;\r
 731         if (chip != dws->prev_chip)\r
 732                 cs_change = 1;\r
 733 \r
 734         cr0 = chip->cr0;\r
 735 \r
 736         /* Handle per transfer options for bpw and speed */\r
 737         if (transfer->speed_hz) {\r
 738                 speed = chip->speed_hz;\r
 739 \r
 740                 if (transfer->speed_hz != speed) {\r
 741                         speed = transfer->speed_hz;\r
 742                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 743                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
 744                                         "freq: %dHz\n", speed);\r
 745                                 message->status = -EIO;\r
 746                                 goto early_exit;\r
 747                         }\r
 748 \r
 749                         /* clk_div doesn't support odd number */\r
 750                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 751                         clk_div = (clk_div + 1) & 0xfffe;\r
 752 \r
 753                         chip->speed_hz = speed;\r
 754                         chip->clk_div = clk_div;\r
 755                 }\r
 756         }\r
 757         \r
 758         if (transfer->bits_per_word) {\r
 759                 bits = transfer->bits_per_word;\r
 760 \r
 761                 switch (bits) {\r
 762                 case 8:\r
 763                         dws->n_bytes = 1;\r
 764                         dws->dma_width = 1;\r
 765                         dws->read = (dws->read != null_reader) ?\r
 766                                         u8_reader : null_reader;\r
 767                         dws->write = (dws->write != null_writer) ?\r
 768                                         u8_writer : null_writer;\r
 769                         spi_dfs = SPI_DFS_8BIT;\r
 770                         break;\r
 771                 case 16:\r
 772                         dws->n_bytes = 2;\r
 773                         dws->dma_width = 2;\r
 774                         dws->read = (dws->read != null_reader) ?\r
 775                                         u16_reader : null_reader;\r
 776                         dws->write = (dws->write != null_writer) ?\r
 777                                         u16_writer : null_writer;\r
 778                         spi_dfs = SPI_DFS_16BIT;\r
 779                         break;\r
 780                 default:\r
 781                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 782                                 "%db\n", bits);\r
 783                         message->status = -EIO;\r
 784                         goto early_exit;\r
 785                 }\r
 786 \r
 787                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 788                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 789                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 790                         | (chip->type << SPI_FRF_OFFSET)\r
 791                         | (spi->mode << SPI_MODE_OFFSET)\r
 792                         | (chip->tmode << SPI_TMOD_OFFSET);\r
 793         }\r
 794         message->state = RUNNING_STATE;\r
 795  \r
 796         /*\r
 797          * Adjust transfer mode if necessary. Requires platform dependent\r
 798          * chipselect mechanism.\r
 799          */\r
 800         if (dws->cs_control) {\r
 801                 if (dws->rx && dws->tx)\r
 802                         chip->tmode = SPI_TMOD_TR;\r
 803                 else if (dws->rx)\r
 804                         chip->tmode = SPI_TMOD_RO;\r
 805                 else\r
 806                         chip->tmode = SPI_TMOD_TO;\r
 807 \r
 808                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
 809                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
 810         } \r
 811 \r
 812         /*\r
 813          * Interrupt mode\r
 814          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely\r
 815          */\r
 816         if (!dws->dma_mapped && !chip->poll_mode) {\r
 817                 int templen ;\r
 818                 \r
 819                 if (chip->tmode == SPI_TMOD_RO) {\r
 820                         templen = dws->len / dws->n_bytes - 1;\r
 821                         rxint_level = dws->fifo_len / 2;\r
 822                         rxint_level = (templen > rxint_level) ? rxint_level : templen;\r
 823                         imask |= SPI_INT_RXFI;\r
 824                 }\r
 825                 else {  \r
 826                         templen = dws->len / dws->n_bytes;\r
 827                         txint_level = dws->fifo_len / 2;\r
 828                         txint_level = (templen > txint_level) ? txint_level : templen;\r
 829                         imask |= SPI_INT_TXEI;\r
 830                 }\r
 831                 dws->transfer_handler = interrupt_transfer;\r
 832         }\r
 833 \r
 834         /*\r
 835          * Reprogram registers only if\r
 836          *      1. chip select changes\r
 837          *      2. clk_div is changed\r
 838          *      3. control value changes\r
 839          */\r
 840         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask) {\r
 841                 spi_enable_chip(dws, 0);\r
 842                 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)\r
 843                         rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
 844 \r
 845                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
 846                 spi_chip_sel(dws, spi->chip_select);\r
 847 \r
 848         rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);\r
 849                 spi_enable_chip(dws, 1);\r
 850 \r
 851                 if (txint_level)\r
 852                         rk29xx_writew(dws, SPIM_TXFTLR, txint_level);\r
 853                 if (rxint_level)\r
 854                         rk29xx_writew(dws, SPIM_RXFTLR, rxint_level);\r
 855                 /* Set the interrupt mask, for poll mode just diable all int */\r
 856                 spi_mask_intr(dws, 0xff);\r
 857                 if (imask)\r
 858                         spi_umask_intr(dws, imask);\r
 859                 \r
 860                 if (cs_change)\r
 861                         dws->prev_chip = chip;\r
 862         } \r
 863 \r
 864         if (chip->poll_mode)\r
 865                 poll_transfer(dws);\r
 866 \r
 867         return;\r
 868 \r
 869 early_exit:\r
 870         giveback(dws);\r
 871         return;\r
 872 }\r
 873 \r
 874 static void dma_transfer(struct rk29xx_spi *dws) //int cs_change)\r
 875 {\r
 876         struct spi_message *message = NULL;\r
 877         struct spi_transfer *transfer = NULL;\r
 878         struct spi_transfer *previous = NULL;\r
 879         struct spi_device *spi = NULL;\r
 880         struct chip_data *chip = NULL;\r
 881         unsigned long val;\r
 882         int ms;\r
 883         int iRet;\r
 884         int burst;\r
 885         u8 bits = 0;\r
 886         u8 spi_dfs = 0;\r
 887         u8 cs_change = 0;\r
 888         u16 clk_div = 0;\r
 889         u32 speed = 0;\r
 890         u32 cr0 = 0;\r
 891         u32 dmacr = 0;\r
 892 \r
 893         DBG(KERN_INFO "dma_transfer\n");\r
 894 \r
 895         if (acquire_dma(dws)) {\r
 896                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 897                 goto err_out;\r
 898         }\r
 899 \r
 900         if (map_dma_buffers(dws)) {\r
 901                 dev_err(&dws->master->dev, "acquire dma failed\n");\r
 902                 goto err_out;\r
 903         }\r
 904 \r
 905         /* Get current state information */\r
 906         message = dws->cur_msg;\r
 907         transfer = dws->cur_transfer;\r
 908         chip = dws->cur_chip;\r
 909         spi = message->spi;     \r
 910         if (unlikely(!chip->clk_div))\r
 911                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz; \r
 912         if (message->state == ERROR_STATE) {\r
 913                 message->status = -EIO;\r
 914                 goto err_out;\r
 915         }\r
 916 \r
 917         /* Handle end of message */\r
 918         if (message->state == DONE_STATE) {\r
 919                 message->status = 0;\r
 920                 goto err_out;\r
 921         }\r
 922 \r
 923         /* Delay if requested at end of transfer*/\r
 924         if (message->state == RUNNING_STATE) {\r
 925                 previous = list_entry(transfer->transfer_list.prev,\r
 926                                         struct spi_transfer,\r
 927                                         transfer_list);\r
 928                 if (previous->delay_usecs)\r
 929                         udelay(previous->delay_usecs);\r
 930         }\r
 931 \r
 932         dws->n_bytes = chip->n_bytes;\r
 933         dws->dma_width = chip->dma_width;\r
 934         dws->cs_control = chip->cs_control;\r
 935 \r
 936         dws->rx_dma = transfer->rx_dma;\r
 937         dws->tx_dma = transfer->tx_dma;\r
 938         dws->tx = (void *)transfer->tx_buf;\r
 939         dws->tx_end = dws->tx + transfer->len;\r
 940         dws->rx = transfer->rx_buf;\r
 941         dws->rx_end = dws->rx + transfer->len;\r
 942         dws->write = dws->tx ? chip->write : null_writer;\r
 943         dws->read = dws->rx ? chip->read : null_reader;\r
 944         dws->cs_change = transfer->cs_change;\r
 945         dws->len = dws->cur_transfer->len;\r
 946         if (chip != dws->prev_chip)\r
 947                 cs_change = 1;\r
 948 \r
 949         cr0 = chip->cr0;\r
 950 \r
 951         /* Handle per transfer options for bpw and speed */\r
 952         if (transfer->speed_hz) {\r
 953                 speed = chip->speed_hz;\r
 954 \r
 955                 if (transfer->speed_hz != speed) {\r
 956                         speed = transfer->speed_hz;\r
 957                         if (speed > clk_get_rate(dws->clock_spim)) {\r
 958                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
 959                                         "freq: %dHz\n", speed);\r
 960                                 message->status = -EIO;\r
 961                                 goto err_out;\r
 962                         }\r
 963 \r
 964                         /* clk_div doesn't support odd number */\r
 965                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
 966                         clk_div = (clk_div + 1) & 0xfffe;\r
 967 \r
 968                         chip->speed_hz = speed;\r
 969                         chip->clk_div = clk_div;\r
 970                 }\r
 971         }\r
 972 \r
 973         if (transfer->bits_per_word) {\r
 974                 bits = transfer->bits_per_word;\r
 975 \r
 976                 switch (bits) {\r
 977                 case 8:\r
 978                         dws->n_bytes = 1;\r
 979                         dws->dma_width = 1;\r
 980                         spi_dfs = SPI_DFS_8BIT;\r
 981                         break;\r
 982                 case 16:\r
 983                         dws->n_bytes = 2;\r
 984                         dws->dma_width = 2;\r
 985                         spi_dfs = SPI_DFS_16BIT;\r
 986                         break;\r
 987                 default:\r
 988                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
 989                                 "%db\n", bits);\r
 990                         message->status = -EIO;\r
 991                         goto err_out;\r
 992                 }\r
 993 \r
 994                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
 995                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
 996                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
 997                         | (chip->type << SPI_FRF_OFFSET)\r
 998                         | (spi->mode << SPI_MODE_OFFSET)\r
 999                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1000         }\r
1001         message->state = RUNNING_STATE;\r
1002  \r
1003         /*\r
1004          * Adjust transfer mode if necessary. Requires platform dependent\r
1005          * chipselect mechanism.\r
1006          */\r
1007         if (dws->cs_control) {\r
1008                 if (dws->rx && dws->tx)\r
1009                         chip->tmode = SPI_TMOD_TR;\r
1010                 else if (dws->rx)\r
1011                         chip->tmode = SPI_TMOD_RO;\r
1012                 else\r
1013                         chip->tmode = SPI_TMOD_TO;\r
1014 \r
1015                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1016                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1017         }\r
1018 \r
1019         /*\r
1020          * Reprogram registers only if\r
1021          *      1. chip select changes\r
1022          *      2. clk_div is changed\r
1023          *      3. control value changes\r
1024          */\r
1025         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div) {\r
1026                 spi_enable_chip(dws, 0);\r
1027                 if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0) {\r
1028                         rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
1029                 }\r
1030 \r
1031                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1032                 spi_chip_sel(dws, spi->chip_select);\r
1033                 /* Set the interrupt mask, for poll mode just diable all int */\r
1034                 spi_mask_intr(dws, 0xff);\r
1035                 \r
1036                 if (transfer->tx_buf != NULL) {\r
1037                         dmacr |= SPI_DMACR_TX_ENABLE;\r
1038                         rk29xx_writew(dws, SPIM_DMATDLR, 0);\r
1039                 }\r
1040                 if (transfer->rx_buf != NULL) {\r
1041                         dmacr |= SPI_DMACR_RX_ENABLE;\r
1042                         rk29xx_writew(dws, SPIM_DMARDLR, 0);\r
1043                         rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);\r
1044                 }\r
1045                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1046                 spi_enable_chip(dws, 1);\r
1047                 if (cs_change)\r
1048                         dws->prev_chip = chip;\r
1049         } \r
1050 \r
1051         INIT_COMPLETION(dws->xfer_completion);\r
1052 \r
1053         spi_dump_regs(dws);\r
1054         DBG("dws->tx_dmach: %d, dws->rx_dmach: %d, transfer->tx_dma: 0x%x\n", dws->tx_dmach, dws->rx_dmach, (unsigned int)transfer->tx_dma);\r
1055         if (transfer->tx_buf != NULL) {\r
1056                 dws->state |= TXBUSY;\r
1057                 /*if (transfer->len & 0x3) {\r
1058                         burst = 1;\r
1059                 }\r
1060                 else {\r
1061                         burst = 4;\r
1062                 }\r
1063                 if (rk29_dma_config(dws->tx_dmach, burst)) {*/\r
1064                 if (rk29_dma_config(dws->tx_dmach, 1, 1)) {//there is not dma burst but bitwide, set it 1 alwayss\r
1065                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1066                         goto err_out;\r
1067                 }\r
1068                 \r
1069                 rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH); \r
1070                 \r
1071                 iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,\r
1072                                         transfer->tx_dma, transfer->len);\r
1073                 if (iRet) {\r
1074                         dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet, \r
1075                                 dws->tx_dmach, (unsigned int)transfer->tx_dma);\r
1076                         goto err_out;\r
1077                 }\r
1078                 \r
1079                 if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {\r
1080                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1081                         goto err_out;\r
1082                 }\r
1083         }\r
1084 \r
1085         wait_till_not_busy(dws);\r
1086 \r
1087         if (transfer->rx_buf != NULL) {\r
1088                 dws->state |= RXBUSY;\r
1089                 if (rk29_dma_config(dws->rx_dmach, 1, 1)) {\r
1090                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1091                         goto err_out;\r
1092                 }\r
1093 \r
1094                 rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH); \r
1095                 \r
1096                 iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,\r
1097                                         transfer->rx_dma, transfer->len);\r
1098                 if (iRet) {\r
1099                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1100                         goto err_out;\r
1101                 }\r
1102                 \r
1103                 if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {\r
1104                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1105                         goto err_out;\r
1106                 }\r
1107         }\r
1108 \r
1109         /* millisecs to xfer 'len' bytes @ 'cur_speed' */\r
1110         ms = transfer->len * 8 / dws->cur_chip->speed_hz;\r
1111         ms += 10; \r
1112 \r
1113         val = msecs_to_jiffies(ms) + 10;\r
1114         if (!wait_for_completion_timeout(&dws->xfer_completion, val)) {\r
1115                 if (transfer->rx_buf != NULL && (dws->state & RXBUSY)) {\r
1116                         rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH);\r
1117                         dws->state &= ~RXBUSY;\r
1118                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1119                         goto NEXT_TRANSFER;\r
1120                 }\r
1121                 if (transfer->tx_buf != NULL && (dws->state & TXBUSY)) {\r
1122                         rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH);\r
1123                         dws->state &= ~TXBUSY;\r
1124                         dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);\r
1125                         goto NEXT_TRANSFER;\r
1126                 }\r
1127         }\r
1128 \r
1129         wait_till_not_busy(dws);\r
1130 \r
1131 NEXT_TRANSFER:\r
1132         /* Update total byte transfered return count actual bytes read */\r
1133         dws->cur_msg->actual_length += dws->len;\r
1134 \r
1135         /* Move to next transfer */\r
1136         dws->cur_msg->state = next_transfer(dws);\r
1137 \r
1138         /* Handle end of message */\r
1139         if (dws->cur_msg->state == DONE_STATE) {\r
1140                 dws->cur_msg->status = 0;\r
1141                 giveback(dws);\r
1142         } else\r
1143                 dma_transfer(dws);\r
1144         \r
1145         return;\r
1146 \r
1147 err_out:\r
1148         giveback(dws);\r
1149         return;\r
1150 \r
1151 }\r
1152 \r
1153 static void pump_messages(struct work_struct *work)\r
1154 {\r
1155         struct rk29xx_spi *dws =\r
1156                 container_of(work, struct rk29xx_spi, pump_messages);\r
1157         unsigned long flags;\r
1158 \r
1159         DBG(KERN_INFO "pump_messages\n");\r
1160 \r
1161         /* Lock queue and check for queue work */\r
1162         spin_lock_irqsave(&dws->lock, flags);\r
1163         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1164                 dws->busy = 0;\r
1165                 spin_unlock_irqrestore(&dws->lock, flags);\r
1166                 return;\r
1167         }\r
1168 \r
1169         /* Make sure we are not already running a message */\r
1170         if (dws->cur_msg) {\r
1171                 spin_unlock_irqrestore(&dws->lock, flags);\r
1172                 return;\r
1173         }\r
1174 \r
1175         /* Extract head of queue */\r
1176         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1177         list_del_init(&dws->cur_msg->queue);\r
1178 \r
1179         /* Initial message state*/\r
1180         dws->cur_msg->state = START_STATE;\r
1181         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1182                                                 struct spi_transfer,\r
1183                                                 transfer_list);\r
1184         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1185     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1186     \r
1187         /* Mark as busy and launch transfers */\r
1188         if(dws->cur_msg->is_dma_mapped /*&& dws->cur_transfer->len > DMA_MIN_BYTES*/) {\r
1189                 dws->busy = 1;\r
1190             spin_unlock_irqrestore(&dws->lock, flags);\r
1191                 dma_transfer(dws);\r
1192                 return;\r
1193         }\r
1194         else {\r
1195                 tasklet_schedule(&dws->pump_transfers);\r
1196         }\r
1197 \r
1198         dws->busy = 1;\r
1199         spin_unlock_irqrestore(&dws->lock, flags);\r
1200 }\r
1201 \r
1202 #if defined(QUICK_TRANSFER)\r
1203 static void do_read(struct rk29xx_spi *dws)\r
1204 {\r
1205         int count = 0;\r
1206 \r
1207         spi_enable_chip(dws, 0);\r
1208         rk29xx_writew(dws, SPIM_CTRLR1, dws->rx_end-dws->rx-1);\r
1209         spi_enable_chip(dws, 1);                \r
1210         rk29xx_writew(dws, SPIM_TXDR, 0);\r
1211         while (1) {\r
1212                 if (dws->read(dws))\r
1213                         break;\r
1214                 if (count++ == 0x20) {\r
1215                         dev_err(&dws->master->dev, "+++++++++++spi receive data time out+++++++++++++\n");\r
1216                         break;\r
1217                 }\r
1218                 \r
1219         }\r
1220 }\r
1221 \r
1222 static void do_write(struct rk29xx_spi *dws)\r
1223 {\r
1224         while (dws->tx<dws->tx_end) {\r
1225                 dws->write(dws);\r
1226         }\r
1227 }\r
1228 \r
1229 /* Caller already set message->status; dma and pio irqs are blocked */\r
1230 static void msg_giveback(struct rk29xx_spi *dws)\r
1231 {\r
1232         struct spi_transfer *last_transfer;\r
1233         struct spi_message *msg;\r
1234 \r
1235         DBG("+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1236 \r
1237         msg = dws->cur_msg;\r
1238         dws->cur_msg = NULL;\r
1239         dws->cur_transfer = NULL;\r
1240         dws->prev_chip = dws->cur_chip;\r
1241         dws->cur_chip = NULL;\r
1242         dws->dma_mapped = 0;\r
1243         dws->busy = 0;\r
1244 \r
1245         last_transfer = list_entry(msg->transfers.prev,\r
1246                                         struct spi_transfer,\r
1247                                         transfer_list);\r
1248 \r
1249         if (!last_transfer->cs_change && dws->cs_control)\r
1250                 dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);\r
1251 \r
1252         msg->state = NULL;      \r
1253 }\r
1254 \r
1255 /* Must be called inside pump_transfers() */\r
1256 static int do_full_transfer(struct rk29xx_spi *dws)\r
1257 {\r
1258         if ((dws->read(dws))) {\r
1259                 goto comple;\r
1260         }\r
1261         \r
1262         while (dws->tx<dws->tx_end){\r
1263                 dws->write(dws);                \r
1264                 dws->read(dws);\r
1265         }\r
1266         \r
1267         if (dws->rx < dws->rx_end) {\r
1268                 dws->read(dws);\r
1269         }\r
1270 \r
1271 comple:\r
1272         \r
1273         dws->cur_msg->actual_length += dws->len;\r
1274         \r
1275         /* Move to next transfer */\r
1276         dws->cur_msg->state = next_transfer(dws);\r
1277                                         \r
1278         if (dws->cur_msg->state == DONE_STATE) {\r
1279                 dws->cur_msg->status = 0;\r
1280                 //msg_giveback(dws);\r
1281                 return 0;\r
1282         }\r
1283         else {\r
1284                 return -1;\r
1285         }\r
1286         \r
1287 }\r
1288 \r
1289 \r
1290 /* Must be called inside pump_transfers() */\r
1291 static int do_half_transfer(struct rk29xx_spi *dws)\r
1292 {\r
1293         if (dws->rx) {\r
1294                 if (dws->tx) {\r
1295                         do_write(dws);\r
1296                 }\r
1297                 wait_till_tf_empty(dws);\r
1298                 wait_till_not_busy(dws);\r
1299                 do_read(dws);\r
1300         }\r
1301         else {\r
1302                 do_write(dws);\r
1303                 wait_till_tf_empty(dws);\r
1304                 wait_till_not_busy(dws);\r
1305         }\r
1306         \r
1307         dws->cur_msg->actual_length += dws->len;\r
1308         \r
1309         /* Move to next transfer */\r
1310         dws->cur_msg->state = next_transfer(dws);\r
1311                                         \r
1312         if (dws->cur_msg->state == DONE_STATE) {\r
1313                 dws->cur_msg->status = 0;\r
1314                 //msg_giveback(dws);\r
1315                 return 0;\r
1316         }\r
1317         else {\r
1318                 return -1;\r
1319         }\r
1320 }\r
1321 \r
1322 \r
1323 static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)\r
1324 {\r
1325         struct spi_message *message = NULL;\r
1326         struct spi_transfer *transfer = NULL;\r
1327         struct spi_transfer *previous = NULL;\r
1328         struct spi_device *spi = NULL;\r
1329         struct chip_data *chip = NULL;\r
1330         u8 bits = 0;\r
1331         u8 spi_dfs = 0;\r
1332         u8 cs_change = 0;\r
1333         u16 clk_div = 0;\r
1334         u32 speed = 0;\r
1335         u32 cr0 = 0;\r
1336         u32 dmacr = 0;\r
1337         \r
1338         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1339 \r
1340         /* Get current state information */\r
1341         message = dws->cur_msg;\r
1342         transfer = dws->cur_transfer;\r
1343         chip = dws->cur_chip;\r
1344         spi = message->spi;     \r
1345 \r
1346         if (unlikely(!chip->clk_div))\r
1347                 chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;\r
1348         if (message->state == ERROR_STATE) {\r
1349                 message->status = -EIO;\r
1350                 goto early_exit;\r
1351         }\r
1352 \r
1353         /* Handle end of message */\r
1354         if (message->state == DONE_STATE) {\r
1355                 message->status = 0;\r
1356                 goto early_exit;\r
1357         }\r
1358 \r
1359         /* Delay if requested at end of transfer*/\r
1360         if (message->state == RUNNING_STATE) {\r
1361                 previous = list_entry(transfer->transfer_list.prev,\r
1362                                         struct spi_transfer,\r
1363                                         transfer_list);\r
1364                 if (previous->delay_usecs)\r
1365                         udelay(previous->delay_usecs);\r
1366         }\r
1367 \r
1368         dws->n_bytes = chip->n_bytes;\r
1369         dws->dma_width = chip->dma_width;\r
1370         dws->cs_control = chip->cs_control;\r
1371 \r
1372         dws->rx_dma = transfer->rx_dma;\r
1373         dws->tx_dma = transfer->tx_dma;\r
1374         dws->tx = (void *)transfer->tx_buf;\r
1375         dws->tx_end = dws->tx + transfer->len;\r
1376         dws->rx = transfer->rx_buf;\r
1377         dws->rx_end = dws->rx + transfer->len;\r
1378         dws->write = dws->tx ? chip->write : null_writer;\r
1379         dws->read = dws->rx ? chip->read : null_reader;\r
1380         if (dws->rx && dws->tx) {\r
1381                 int temp_len = transfer->len;\r
1382                 int len;\r
1383                 unsigned char *tx_buf;\r
1384                 for (len=0; *tx_buf++ != 0; len++);\r
1385                 dws->tx_end = dws->tx + len;\r
1386                 dws->rx_end = dws->rx + temp_len - len;\r
1387         }\r
1388         dws->cs_change = transfer->cs_change;\r
1389         dws->len = dws->cur_transfer->len;\r
1390         if (chip != dws->prev_chip)\r
1391                 cs_change = 1;\r
1392 \r
1393         cr0 = chip->cr0;\r
1394 \r
1395         /* Handle per transfer options for bpw and speed */\r
1396         if (transfer->speed_hz) {\r
1397                 speed = chip->speed_hz;\r
1398 \r
1399                 if (transfer->speed_hz != speed) {\r
1400                         speed = transfer->speed_hz;\r
1401                         if (speed > clk_get_rate(dws->clock_spim)) {\r
1402                                 dev_err(&dws->master->dev, "MRST SPI0: unsupported"\r
1403                                         "freq: %dHz\n", speed);\r
1404                                 message->status = -EIO;\r
1405                                 goto early_exit;\r
1406                         }\r
1407 \r
1408                         /* clk_div doesn't support odd number */\r
1409                         clk_div = clk_get_rate(dws->clock_spim) / speed;\r
1410                         clk_div = (clk_div + 1) & 0xfffe;\r
1411 \r
1412                         chip->speed_hz = speed;\r
1413                         chip->clk_div = clk_div;\r
1414                 }\r
1415         }\r
1416         if (transfer->bits_per_word) {\r
1417                 bits = transfer->bits_per_word;\r
1418 \r
1419                 switch (bits) {\r
1420                 case 8:\r
1421                         dws->n_bytes = 1;\r
1422                         dws->dma_width = 1;\r
1423                         dws->read = (dws->read != null_reader) ?\r
1424                                         u8_reader : null_reader;\r
1425                         dws->write = (dws->write != null_writer) ?\r
1426                                         u8_writer : null_writer;\r
1427                         spi_dfs = SPI_DFS_8BIT;\r
1428                         break;\r
1429                 case 16:\r
1430                         dws->n_bytes = 2;\r
1431                         dws->dma_width = 2;\r
1432                         dws->read = (dws->read != null_reader) ?\r
1433                                         u16_reader : null_reader;\r
1434                         dws->write = (dws->write != null_writer) ?\r
1435                                         u16_writer : null_writer;\r
1436                         spi_dfs = SPI_DFS_16BIT;\r
1437                         break;\r
1438                 default:\r
1439                         dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"\r
1440                                 "%db\n", bits);\r
1441                         message->status = -EIO;\r
1442                         goto early_exit;\r
1443                 }\r
1444 \r
1445                 cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1446                         | (chip->type << SPI_FRF_OFFSET)\r
1447                         | (spi->mode << SPI_MODE_OFFSET)\r
1448                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1449         }\r
1450         message->state = RUNNING_STATE;\r
1451  \r
1452         /*\r
1453          * Adjust transfer mode if necessary. Requires platform dependent\r
1454          * chipselect mechanism.\r
1455          */\r
1456         if (dws->cs_control) {\r
1457                 if (dws->rx && dws->tx)\r
1458                         chip->tmode = SPI_TMOD_TR;\r
1459                 else if (dws->rx)\r
1460                         chip->tmode = SPI_TMOD_RO;\r
1461                 else\r
1462                         chip->tmode = SPI_TMOD_TO;\r
1463 \r
1464                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);\r
1465                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);\r
1466         }\r
1467         \r
1468         /* Check if current transfer is a DMA transaction */\r
1469         dws->dma_mapped = map_dma_buffers(dws);\r
1470 \r
1471         /*\r
1472          * Reprogram registers only if\r
1473          *      1. chip select changes\r
1474          *      2. clk_div is changed\r
1475          *      3. control value changes\r
1476          */\r
1477         spi_enable_chip(dws, 0);\r
1478         if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0)\r
1479                 rk29xx_writew(dws, SPIM_CTRLR0, cr0);\r
1480 \r
1481     DBG(KERN_INFO "clk_div: 0x%x, chip->clk_div: 0x%x\n", clk_div, chip->clk_div);\r
1482         spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);            \r
1483         spi_chip_sel(dws, spi->chip_select);            \r
1484         rk29xx_writew(dws, SPIM_CTRLR1, 0);//add by lyx\r
1485         if(dws->dma_mapped ) {\r
1486                 dmacr = rk29xx_readw(dws, SPIM_DMACR);\r
1487                 dmacr = dmacr | SPI_DMACR_TX_ENABLE;\r
1488                 if (mode) \r
1489                         dmacr = dmacr | SPI_DMACR_RX_ENABLE;\r
1490                 rk29xx_writew(dws, SPIM_DMACR, dmacr);\r
1491         }\r
1492         spi_enable_chip(dws, 1);\r
1493         if (cs_change)\r
1494                 dws->prev_chip = chip;\r
1495         \r
1496         if (mode)\r
1497                 return do_full_transfer(dws);\r
1498         else\r
1499                 return do_half_transfer(dws);   \r
1500         \r
1501 early_exit:\r
1502         \r
1503         //msg_giveback(dws);\r
1504         \r
1505         return 0;\r
1506 }\r
1507 \r
1508 static void rk29xx_pump_messages(struct rk29xx_spi *dws, int mode)\r
1509 {\r
1510         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1511         \r
1512         while (!acquire_dma(dws))\r
1513                         msleep(10);\r
1514 \r
1515         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {\r
1516                 dws->busy = 0;\r
1517                 return;\r
1518         }\r
1519 \r
1520         /* Make sure we are not already running a message */\r
1521         if (dws->cur_msg) {\r
1522                 return;\r
1523         }\r
1524 \r
1525         /* Extract head of queue */\r
1526         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);\r
1527         list_del_init(&dws->cur_msg->queue);\r
1528 \r
1529         /* Initial message state*/\r
1530         dws->cur_msg->state = START_STATE;\r
1531         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,\r
1532                                                 struct spi_transfer,\r
1533                                                 transfer_list);\r
1534         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);\r
1535     dws->prev_chip = NULL; //Ã¿¸öpump messageÊ±Ç¿ÖÆ¸üÐÂcs dxj\r
1536     \r
1537         /* Mark as busy and launch transfers */\r
1538         dws->busy = 1;\r
1539 \r
1540         while (rk29xx_pump_transfers(dws, mode)) ;\r
1541 }\r
1542 \r
1543 /* spi_device use this to queue in their spi_msg */\r
1544 static int rk29xx_spi_quick_transfer(struct spi_device *spi, struct spi_message *msg)\r
1545 {\r
1546         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1547         unsigned long flags;\r
1548         struct rk29xx_spi_chip *chip_info = spi->controller_data;\r
1549         struct spi_message *mmsg;\r
1550         \r
1551         DBG(KERN_INFO "+++++++++++++++enter %s++++++++++++++++++\n", __func__);\r
1552         \r
1553         spin_lock_irqsave(&dws->lock, flags);\r
1554 \r
1555         if (dws->run == QUEUE_STOPPED) {\r
1556                 spin_unlock_irqrestore(&dws->lock, flags);\r
1557                 return -ESHUTDOWN;\r
1558         }\r
1559 \r
1560         msg->actual_length = 0;\r
1561         msg->status = -EINPROGRESS;\r
1562         msg->state = START_STATE;\r
1563 \r
1564         list_add_tail(&msg->queue, &dws->queue);\r
1565 \r
1566         if (chip_info && (chip_info->transfer_mode == rk29xx_SPI_FULL_DUPLEX)) {\r
1567                 rk29xx_pump_messages(dws,1);\r
1568         }\r
1569         else {          \r
1570                 rk29xx_pump_messages(dws,0);\r
1571         }\r
1572 \r
1573         mmsg = dws->cur_msg;\r
1574         msg_giveback(dws);\r
1575         \r
1576         spin_unlock_irqrestore(&dws->lock, flags);\r
1577 \r
1578         if (mmsg->complete)\r
1579                 mmsg->complete(mmsg->context);\r
1580         \r
1581         return 0;\r
1582 }\r
1583 \r
1584 #else\r
1585 \r
1586 /* spi_device use this to queue in their spi_msg */\r
1587 static int rk29xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)\r
1588 {\r
1589         struct rk29xx_spi *dws = spi_master_get_devdata(spi->master);\r
1590         unsigned long flags;\r
1591 \r
1592         spin_lock_irqsave(&dws->lock, flags);\r
1593 \r
1594         if (dws->run == QUEUE_STOPPED) {\r
1595                 spin_unlock_irqrestore(&dws->lock, flags);\r
1596                 return -ESHUTDOWN;\r
1597         }\r
1598 \r
1599         msg->actual_length = 0;\r
1600         msg->status = -EINPROGRESS;\r
1601         msg->state = START_STATE;\r
1602 \r
1603         list_add_tail(&msg->queue, &dws->queue);\r
1604 \r
1605         if (dws->run == QUEUE_RUNNING && !dws->busy) {\r
1606 \r
1607                 if (dws->cur_transfer || dws->cur_msg)\r
1608                         queue_work(dws->workqueue,\r
1609                                         &dws->pump_messages);\r
1610                 else {\r
1611                         /* If no other data transaction in air, just go */\r
1612                         spin_unlock_irqrestore(&dws->lock, flags);\r
1613                         pump_messages(&dws->pump_messages);\r
1614                         return 0;\r
1615                 }\r
1616         }\r
1617 \r
1618         spin_unlock_irqrestore(&dws->lock, flags);\r
1619         \r
1620         return 0;\r
1621 }\r
1622 \r
1623 #endif\r
1624 \r
1625 /* This may be called twice for each spi dev */\r
1626 static int rk29xx_spi_setup(struct spi_device *spi)\r
1627 {\r
1628         struct rk29xx_spi_chip *chip_info = NULL;\r
1629         struct chip_data *chip;\r
1630         u8 spi_dfs = 0;\r
1631 \r
1632         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)\r
1633                 return -EINVAL;\r
1634 \r
1635         /* Only alloc on first setup */\r
1636         chip = spi_get_ctldata(spi);\r
1637         if (!chip) {\r
1638                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);\r
1639                 if (!chip)\r
1640                         return -ENOMEM;\r
1641 \r
1642                 chip->cs_control = spi_cs_control;\r
1643                 chip->enable_dma = 1;  //0;\r
1644         }\r
1645 \r
1646         /*\r
1647          * Protocol drivers may change the chip settings, so...\r
1648          * if chip_info exists, use it\r
1649          */\r
1650         chip_info = spi->controller_data;\r
1651 \r
1652         /* chip_info doesn't always exist */\r
1653         if (chip_info) {\r
1654                 if (chip_info->cs_control)\r
1655                         chip->cs_control = chip_info->cs_control;\r
1656 \r
1657                 chip->poll_mode = chip_info->poll_mode;\r
1658                 chip->type = chip_info->type;\r
1659 \r
1660                 chip->rx_threshold = 0;\r
1661                 chip->tx_threshold = 0;\r
1662 \r
1663                 chip->enable_dma = chip_info->enable_dma;\r
1664         }\r
1665 \r
1666         if (spi->bits_per_word == 8) {\r
1667                 chip->n_bytes = 1;\r
1668                 chip->dma_width = 1;\r
1669                 chip->read = u8_reader;\r
1670                 chip->write = u8_writer;\r
1671                 spi_dfs = SPI_DFS_8BIT;\r
1672         } else if (spi->bits_per_word == 16) {\r
1673                 chip->n_bytes = 2;\r
1674                 chip->dma_width = 2;\r
1675                 chip->read = u16_reader;\r
1676                 chip->write = u16_writer;\r
1677                 spi_dfs = SPI_DFS_16BIT;\r
1678         } else {\r
1679                 /* Never take >16b case for MRST SPIC */\r
1680                 dev_err(&spi->dev, "invalid wordsize\n");\r
1681                 return -EINVAL;\r
1682         }\r
1683         chip->bits_per_word = spi->bits_per_word;\r
1684 \r
1685         if (!spi->max_speed_hz) {\r
1686                 dev_err(&spi->dev, "No max speed HZ parameter\n");\r
1687                 return -EINVAL;\r
1688         }\r
1689         chip->speed_hz = spi->max_speed_hz;\r
1690 \r
1691         chip->tmode = 0; /* Tx & Rx */\r
1692         /* Default SPI mode is SCPOL = 0, SCPH = 0 */\r
1693         chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)\r
1694                 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)\r
1695                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)\r
1696                         | (chip->type << SPI_FRF_OFFSET)\r
1697                         | (spi->mode  << SPI_MODE_OFFSET)\r
1698                         | (chip->tmode << SPI_TMOD_OFFSET);\r
1699 \r
1700         spi_set_ctldata(spi, chip);\r
1701         return 0;\r
1702 }\r
1703 \r
1704 static void rk29xx_spi_cleanup(struct spi_device *spi)\r
1705 {\r
1706         struct chip_data *chip = spi_get_ctldata(spi);\r
1707         kfree(chip);\r
1708 }\r
1709 \r
1710 static int __devinit init_queue(struct rk29xx_spi *dws)\r
1711 {\r
1712         INIT_LIST_HEAD(&dws->queue);\r
1713         spin_lock_init(&dws->lock);\r
1714 \r
1715         dws->run = QUEUE_STOPPED;\r
1716         dws->busy = 0;\r
1717 \r
1718         init_completion(&dws->xfer_completion);\r
1719 \r
1720         tasklet_init(&dws->pump_transfers,\r
1721                         pump_transfers, (unsigned long)dws);\r
1722 \r
1723         INIT_WORK(&dws->pump_messages, pump_messages);\r
1724         dws->workqueue = create_singlethread_workqueue(\r
1725                                         dev_name(dws->master->dev.parent));\r
1726         if (dws->workqueue == NULL)\r
1727                 return -EBUSY;\r
1728 \r
1729         return 0;\r
1730 }\r
1731 \r
1732 static int start_queue(struct rk29xx_spi *dws)\r
1733 {\r
1734         unsigned long flags;\r
1735 \r
1736         spin_lock_irqsave(&dws->lock, flags);\r
1737 \r
1738         if (dws->run == QUEUE_RUNNING || dws->busy) {\r
1739                 spin_unlock_irqrestore(&dws->lock, flags);\r
1740                 return -EBUSY;\r
1741         }\r
1742 \r
1743         dws->run = QUEUE_RUNNING;\r
1744         dws->cur_msg = NULL;\r
1745         dws->cur_transfer = NULL;\r
1746         dws->cur_chip = NULL;\r
1747         dws->prev_chip = NULL;\r
1748         spin_unlock_irqrestore(&dws->lock, flags);\r
1749 \r
1750         queue_work(dws->workqueue, &dws->pump_messages);\r
1751 \r
1752         return 0;\r
1753 }\r
1754 \r
1755 static int stop_queue(struct rk29xx_spi *dws)\r
1756 {\r
1757         unsigned long flags;\r
1758         unsigned limit = 50;\r
1759         int status = 0;\r
1760 \r
1761         spin_lock_irqsave(&dws->lock, flags);\r
1762         dws->run = QUEUE_STOPPED;\r
1763         while (!list_empty(&dws->queue) && dws->busy && limit--) {\r
1764                 spin_unlock_irqrestore(&dws->lock, flags);\r
1765                 msleep(10);\r
1766                 spin_lock_irqsave(&dws->lock, flags);\r
1767         }\r
1768 \r
1769         if (!list_empty(&dws->queue) || dws->busy)\r
1770                 status = -EBUSY;\r
1771         spin_unlock_irqrestore(&dws->lock, flags);\r
1772 \r
1773         return status;\r
1774 }\r
1775 \r
1776 static int destroy_queue(struct rk29xx_spi *dws)\r
1777 {\r
1778         int status;\r
1779 \r
1780         status = stop_queue(dws);\r
1781         if (status != 0)\r
1782                 return status;\r
1783         destroy_workqueue(dws->workqueue);\r
1784         return 0;\r
1785 }\r
1786 \r
1787 /* Restart the controller, disable all interrupts, clean rx fifo */\r
1788 static void spi_hw_init(struct rk29xx_spi *dws)\r
1789 {\r
1790         spi_enable_chip(dws, 0);\r
1791         spi_mask_intr(dws, 0xff);\r
1792         \r
1793         /*\r
1794          * Try to detect the FIFO depth if not set by interface driver,\r
1795          * the depth could be from 2 to 32 from HW spec\r
1796          */\r
1797         if (!dws->fifo_len) {\r
1798                 u32 fifo;\r
1799                 for (fifo = 2; fifo <= 31; fifo++) {\r
1800                         rk29xx_writew(dws, SPIM_TXFTLR, fifo);\r
1801                         if (fifo != rk29xx_readw(dws, SPIM_TXFTLR))\r
1802                                 break;\r
1803                 }\r
1804 \r
1805                 dws->fifo_len = (fifo == 31) ? 0 : fifo;\r
1806                 rk29xx_writew(dws, SPIM_TXFTLR, 0);\r
1807         }\r
1808         \r
1809         spi_enable_chip(dws, 1);\r
1810         //flush(dws);\r
1811 }\r
1812 \r
1813 /* cpufreq driver support */\r
1814 #ifdef CONFIG_CPU_FREQ\r
1815 \r
1816 static int rk29xx_spim_cpufreq_transition(struct notifier_block *nb, unsigned long val, void *data)\r
1817 {\r
1818         struct rk29xx_spi *info;\r
1819         unsigned long newclk;\r
1820 \r
1821         info = container_of(nb, struct rk29xx_spi, freq_transition);\r
1822         newclk = clk_get_rate(info->clock_spim);\r
1823 \r
1824         return 0;\r
1825 }\r
1826 \r
1827 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1828 {\r
1829         info->freq_transition.notifier_call = rk29xx_spim_cpufreq_transition;\r
1830 \r
1831         return cpufreq_register_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1832 }\r
1833 \r
1834 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1835 {\r
1836         cpufreq_unregister_notifier(&info->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);\r
1837 }\r
1838 \r
1839 #else\r
1840 static inline int rk29xx_spim_cpufreq_register(struct rk29xx_spi *info)\r
1841 {\r
1842         return 0;\r
1843 }\r
1844 \r
1845 static inline void rk29xx_spim_cpufreq_deregister(struct rk29xx_spi *info)\r
1846 {\r
1847 }\r
1848 #endif\r
1849 static int __init rk29xx_spim_probe(struct platform_device *pdev)\r
1850 {\r
1851         struct resource         *regs, *dmatx_res, *dmarx_res;\r
1852         struct rk29xx_spi   *dws;\r
1853         struct spi_master   *master;\r
1854         int                     irq; \r
1855         int ret;\r
1856         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
1857 \r
1858         if (pdata && pdata->io_init) {\r
1859                 ret = pdata->io_init(pdata->chipselect_gpios, pdata->num_chipselect);\r
1860                 if (ret) {                      \r
1861                         return -ENXIO;  \r
1862                 }\r
1863         }\r
1864         \r
1865         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1866         if (!regs)\r
1867                 return -ENXIO;\r
1868         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);\r
1869         if (dmatx_res == NULL) {\r
1870                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");\r
1871                 return -ENXIO;\r
1872         }\r
1873 \r
1874         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);\r
1875         if (dmarx_res == NULL) {\r
1876                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");\r
1877                 return -ENXIO;\r
1878         }\r
1879         irq = platform_get_irq(pdev, 0);\r
1880         if (irq < 0)\r
1881                 return irq;                     \r
1882         /* setup spi core then atmel-specific driver state */\r
1883         ret = -ENOMEM;  \r
1884         master = spi_alloc_master(&pdev->dev, sizeof *dws);\r
1885         if (!master) {\r
1886                 ret = -ENOMEM;\r
1887                 goto exit;\r
1888         }\r
1889 \r
1890         platform_set_drvdata(pdev, master);\r
1891         dws = spi_master_get_devdata(master);\r
1892         dws->clock_spim = clk_get(&pdev->dev, "spi");\r
1893         clk_enable(dws->clock_spim);\r
1894         if (IS_ERR(dws->clock_spim)) {\r
1895                 dev_err(&pdev->dev, "clk_get for spi fail(%p)\n", dws->clock_spim);\r
1896                 return PTR_ERR(dws->clock_spim);\r
1897         }\r
1898         \r
1899         dws->regs = ioremap(regs->start, (regs->end - regs->start) + 1);\r
1900         if (!dws->regs){\r
1901         release_mem_region(regs->start, (regs->end - regs->start) + 1);\r
1902                 return -EBUSY;\r
1903         }\r
1904         DBG(KERN_INFO "dws->regs: %p\n", dws->regs);\r
1905         dws->irq = irq;\r
1906         dws->irq_polarity = IRQF_TRIGGER_NONE;\r
1907         dws->master = master;\r
1908         dws->type = SSI_MOTO_SPI;\r
1909         dws->prev_chip = NULL;\r
1910         dws->sfr_start = regs->start;\r
1911         dws->tx_dmach = dmatx_res->start;\r
1912         dws->rx_dmach = dmarx_res->start;\r
1913         dws->dma_inited = 0;  ///0;\r
1914         ///dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);\r
1915         ret = request_irq(dws->irq, rk29xx_spi_irq, dws->irq_polarity,\r
1916                         "rk29xx_spim", dws);\r
1917         if (ret < 0) {\r
1918                 dev_err(&master->dev, "can not get IRQ\n");\r
1919                 goto err_free_master;\r
1920         }\r
1921 \r
1922         master->mode_bits = SPI_CPOL | SPI_CPHA;\r
1923         master->bus_num = pdev->id;\r
1924         master->num_chipselect = pdata->num_chipselect;\r
1925         master->dev.platform_data = pdata;\r
1926         master->cleanup = rk29xx_spi_cleanup;\r
1927         master->setup = rk29xx_spi_setup;\r
1928         #if defined(QUICK_TRANSFER)\r
1929         master->transfer = rk29xx_spi_quick_transfer;\r
1930         #else\r
1931         master->transfer = rk29xx_spi_transfer;\r
1932         #endif\r
1933         \r
1934         dws->pdev = pdev;\r
1935         /* Basic HW init */\r
1936         spi_hw_init(dws);\r
1937         flush(dws);\r
1938         /* Initial and start queue */\r
1939         ret = init_queue(dws);\r
1940         if (ret) {\r
1941                 dev_err(&master->dev, "problem initializing queue\n");\r
1942                 goto err_diable_hw;\r
1943         }\r
1944 \r
1945         ret = start_queue(dws);\r
1946         if (ret) {\r
1947                 dev_err(&master->dev, "problem starting queue\n");\r
1948                 goto err_diable_hw;\r
1949         }\r
1950 \r
1951         spi_master_set_devdata(master, dws);\r
1952         ret = spi_register_master(master);\r
1953         if (ret) {\r
1954                 dev_err(&master->dev, "problem registering spi master\n");\r
1955                 goto err_queue_alloc;\r
1956         }\r
1957 \r
1958     ret =rk29xx_spim_cpufreq_register(dws);\r
1959     if (ret < 0) {\r
1960         dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");\r
1961         goto err_queue_alloc;\r
1962     }\r
1963         printk(KERN_INFO "rk29xx_spim: driver initialized, fifo_len=%d,bus_num=%d\n", dws->fifo_len,master->bus_num);\r
1964         mrst_spi_debugfs_init(dws);\r
1965         return 0;\r
1966 \r
1967 err_queue_alloc:\r
1968         destroy_queue(dws);\r
1969 err_diable_hw:\r
1970         spi_enable_chip(dws, 0);\r
1971         free_irq(dws->irq, dws);\r
1972 err_free_master:\r
1973         spi_master_put(master);\r
1974         iounmap(dws->regs);\r
1975 exit:\r
1976         return ret;\r
1977 }\r
1978 \r
1979 static void __exit rk29xx_spim_remove(struct platform_device *pdev)\r
1980 {\r
1981         struct spi_master *master = platform_get_drvdata(pdev);\r
1982         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
1983         int status = 0;\r
1984 \r
1985         if (!dws)\r
1986                 return;\r
1987         rk29xx_spim_cpufreq_deregister(dws);\r
1988         mrst_spi_debugfs_remove(dws);\r
1989 \r
1990         release_dma(dws);\r
1991 \r
1992         /* Remove the queue */\r
1993         status = destroy_queue(dws);\r
1994         if (status != 0)\r
1995                 dev_err(&dws->master->dev, "rk29xx_spi_remove: workqueue will not "\r
1996                         "complete, message memory not freed\n");\r
1997         clk_put(dws->clock_spim);\r
1998         clk_disable(dws->clock_spim);\r
1999         spi_enable_chip(dws, 0);\r
2000         /* Disable clk */\r
2001         spi_set_clk(dws, 0);\r
2002         free_irq(dws->irq, dws);\r
2003 \r
2004         /* Disconnect from the SPI framework */\r
2005         spi_unregister_master(dws->master);\r
2006         iounmap(dws->regs);\r
2007 }\r
2008 \r
2009 \r
2010 #ifdef  CONFIG_PM\r
2011 \r
2012 static int rk29xx_spim_suspend(struct platform_device *pdev, pm_message_t mesg)\r
2013 {\r
2014         struct spi_master *master = platform_get_drvdata(pdev);\r
2015         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2016         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2017         int status;\r
2018         \r
2019         flush(dws);\r
2020         status = stop_queue(dws);\r
2021         if (status != 0)\r
2022                 return status;\r
2023         clk_disable(dws->clock_spim);\r
2024         if (pdata && pdata->io_fix_leakage_bug)\r
2025         {\r
2026                 pdata->io_fix_leakage_bug( );\r
2027         }\r
2028         return 0;\r
2029 }\r
2030 \r
2031 static int rk29xx_spim_resume(struct platform_device *pdev)\r
2032 {\r
2033         struct spi_master *master = platform_get_drvdata(pdev);\r
2034         struct rk29xx_spi *dws = spi_master_get_devdata(master);\r
2035         struct rk29xx_spi_platform_data *pdata = pdev->dev.platform_data;\r
2036         int ret;\r
2037         \r
2038         clk_enable(dws->clock_spim);    \r
2039         spi_hw_init(dws);\r
2040         ret = start_queue(dws);\r
2041         if (ret)\r
2042                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);\r
2043         if (pdata && pdata->io_resume_leakage_bug)\r
2044         {\r
2045                 pdata->io_resume_leakage_bug( ); \r
2046         }\r
2047         return ret;\r
2048 }\r
2049 \r
2050 #else\r
2051 #define rk29xx_spim_suspend     NULL\r
2052 #define rk29xx_spim_resume      NULL\r
2053 #endif\r
2054 \r
2055 static struct platform_driver rk29xx_platform_spim_driver = {\r
2056         .remove         = __exit_p(rk29xx_spim_remove),\r
2057         .driver         = {\r
2058                 .name   = "rk29xx_spim",\r
2059                 .owner  = THIS_MODULE,\r
2060         },\r
2061         .suspend        = rk29xx_spim_suspend,\r
2062         .resume         = rk29xx_spim_resume,\r
2063 };\r
2064 \r
2065 static int __init rk29xx_spim_init(void)\r
2066 {\r
2067         int ret;\r
2068         ret = platform_driver_probe(&rk29xx_platform_spim_driver, rk29xx_spim_probe);   \r
2069         return ret;\r
2070 }\r
2071 \r
2072 static void __exit rk29xx_spim_exit(void)\r
2073 {\r
2074         platform_driver_unregister(&rk29xx_platform_spim_driver);\r
2075 }\r
2076 \r
2077 arch_initcall_sync(rk29xx_spim_init);\r
2078 module_exit(rk29xx_spim_exit);\r
2079 \r
2080 MODULE_AUTHOR("www.rock-chips.com");\r
2081 MODULE_DESCRIPTION("Rockchip RK29xx spim port driver");\r
2082 MODULE_LICENSE("GPL");;\r
2083 \r