2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/atmel.h>
23 #include <linux/platform_data/dma-atmel.h>
27 #include <linux/gpio.h>
28 #include <linux/pinctrl/consumer.h>
30 /* SPI register offsets */
33 #define SPI_RDR 0x0008
34 #define SPI_TDR 0x000c
36 #define SPI_IER 0x0014
37 #define SPI_IDR 0x0018
38 #define SPI_IMR 0x001c
39 #define SPI_CSR0 0x0030
40 #define SPI_CSR1 0x0034
41 #define SPI_CSR2 0x0038
42 #define SPI_CSR3 0x003c
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
66 #define SPI_MSTR_OFFSET 0
67 #define SPI_MSTR_SIZE 1
68 #define SPI_PS_OFFSET 1
70 #define SPI_PCSDEC_OFFSET 2
71 #define SPI_PCSDEC_SIZE 1
72 #define SPI_FDIV_OFFSET 3
73 #define SPI_FDIV_SIZE 1
74 #define SPI_MODFDIS_OFFSET 4
75 #define SPI_MODFDIS_SIZE 1
76 #define SPI_WDRBT_OFFSET 5
77 #define SPI_WDRBT_SIZE 1
78 #define SPI_LLB_OFFSET 7
79 #define SPI_LLB_SIZE 1
80 #define SPI_PCS_OFFSET 16
81 #define SPI_PCS_SIZE 4
82 #define SPI_DLYBCS_OFFSET 24
83 #define SPI_DLYBCS_SIZE 8
85 /* Bitfields in RDR */
86 #define SPI_RD_OFFSET 0
87 #define SPI_RD_SIZE 16
89 /* Bitfields in TDR */
90 #define SPI_TD_OFFSET 0
91 #define SPI_TD_SIZE 16
94 #define SPI_RDRF_OFFSET 0
95 #define SPI_RDRF_SIZE 1
96 #define SPI_TDRE_OFFSET 1
97 #define SPI_TDRE_SIZE 1
98 #define SPI_MODF_OFFSET 2
99 #define SPI_MODF_SIZE 1
100 #define SPI_OVRES_OFFSET 3
101 #define SPI_OVRES_SIZE 1
102 #define SPI_ENDRX_OFFSET 4
103 #define SPI_ENDRX_SIZE 1
104 #define SPI_ENDTX_OFFSET 5
105 #define SPI_ENDTX_SIZE 1
106 #define SPI_RXBUFF_OFFSET 6
107 #define SPI_RXBUFF_SIZE 1
108 #define SPI_TXBUFE_OFFSET 7
109 #define SPI_TXBUFE_SIZE 1
110 #define SPI_NSSR_OFFSET 8
111 #define SPI_NSSR_SIZE 1
112 #define SPI_TXEMPTY_OFFSET 9
113 #define SPI_TXEMPTY_SIZE 1
114 #define SPI_SPIENS_OFFSET 16
115 #define SPI_SPIENS_SIZE 1
117 /* Bitfields in CSR0 */
118 #define SPI_CPOL_OFFSET 0
119 #define SPI_CPOL_SIZE 1
120 #define SPI_NCPHA_OFFSET 1
121 #define SPI_NCPHA_SIZE 1
122 #define SPI_CSAAT_OFFSET 3
123 #define SPI_CSAAT_SIZE 1
124 #define SPI_BITS_OFFSET 4
125 #define SPI_BITS_SIZE 4
126 #define SPI_SCBR_OFFSET 8
127 #define SPI_SCBR_SIZE 8
128 #define SPI_DLYBS_OFFSET 16
129 #define SPI_DLYBS_SIZE 8
130 #define SPI_DLYBCT_OFFSET 24
131 #define SPI_DLYBCT_SIZE 8
133 /* Bitfields in RCR */
134 #define SPI_RXCTR_OFFSET 0
135 #define SPI_RXCTR_SIZE 16
137 /* Bitfields in TCR */
138 #define SPI_TXCTR_OFFSET 0
139 #define SPI_TXCTR_SIZE 16
141 /* Bitfields in RNCR */
142 #define SPI_RXNCR_OFFSET 0
143 #define SPI_RXNCR_SIZE 16
145 /* Bitfields in TNCR */
146 #define SPI_TXNCR_OFFSET 0
147 #define SPI_TXNCR_SIZE 16
149 /* Bitfields in PTCR */
150 #define SPI_RXTEN_OFFSET 0
151 #define SPI_RXTEN_SIZE 1
152 #define SPI_RXTDIS_OFFSET 1
153 #define SPI_RXTDIS_SIZE 1
154 #define SPI_TXTEN_OFFSET 8
155 #define SPI_TXTEN_SIZE 1
156 #define SPI_TXTDIS_OFFSET 9
157 #define SPI_TXTDIS_SIZE 1
159 /* Constants for BITS */
160 #define SPI_BITS_8_BPT 0
161 #define SPI_BITS_9_BPT 1
162 #define SPI_BITS_10_BPT 2
163 #define SPI_BITS_11_BPT 3
164 #define SPI_BITS_12_BPT 4
165 #define SPI_BITS_13_BPT 5
166 #define SPI_BITS_14_BPT 6
167 #define SPI_BITS_15_BPT 7
168 #define SPI_BITS_16_BPT 8
170 /* Bit manipulation macros */
171 #define SPI_BIT(name) \
172 (1 << SPI_##name##_OFFSET)
173 #define SPI_BF(name, value) \
174 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
175 #define SPI_BFEXT(name, value) \
176 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
177 #define SPI_BFINS(name, value, old) \
178 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
179 | SPI_BF(name, value))
181 /* Register access macros */
182 #define spi_readl(port, reg) \
183 __raw_readl((port)->regs + SPI_##reg)
184 #define spi_writel(port, reg, value) \
185 __raw_writel((value), (port)->regs + SPI_##reg)
187 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
188 * cache operations; better heuristics consider wordsize and bitrate.
190 #define DMA_MIN_BYTES 16
192 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
194 struct atmel_spi_dma {
195 struct dma_chan *chan_rx;
196 struct dma_chan *chan_tx;
197 struct scatterlist sgrx;
198 struct scatterlist sgtx;
199 struct dma_async_tx_descriptor *data_desc_rx;
200 struct dma_async_tx_descriptor *data_desc_tx;
202 struct at_dma_slave dma_slave;
205 struct atmel_spi_caps {
208 bool has_dma_support;
212 * The core SPI transfer engine just talks to a register bank to set up
213 * DMA transfers; transfer queue progress is driven by IRQs. The clock
214 * framework provides the base clock, subdivided for each spi_device.
224 struct platform_device *pdev;
226 struct spi_transfer *current_transfer;
227 int current_remaining_bytes;
230 struct completion xfer_completion;
234 dma_addr_t buffer_dma;
236 struct atmel_spi_caps caps;
241 struct atmel_spi_dma dma;
247 /* Controller-specific per-slave state */
248 struct atmel_spi_device {
249 unsigned int npcs_pin;
253 #define BUFFER_SIZE PAGE_SIZE
254 #define INVALID_DMA_ADDRESS 0xffffffff
257 * Version 2 of the SPI controller has
259 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
260 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
262 * - SPI_CSRx.SBCR allows faster clocking
264 static bool atmel_spi_is_v2(struct atmel_spi *as)
266 return as->caps.is_spi2;
270 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
271 * they assume that spi slave device state will not change on deselect, so
272 * that automagic deselection is OK. ("NPCSx rises if no data is to be
273 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
274 * controllers have CSAAT and friends.
276 * Since the CSAAT functionality is a bit weird on newer controllers as
277 * well, we use GPIO to control nCSx pins on all controllers, updating
278 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
279 * support active-high chipselects despite the controller's belief that
280 * only active-low devices/systems exists.
282 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
283 * right when driven with GPIO. ("Mode Fault does not allow more than one
284 * Master on Chip Select 0.") No workaround exists for that ... so for
285 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
286 * and (c) will trigger that first erratum in some cases.
289 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
291 struct atmel_spi_device *asd = spi->controller_state;
292 unsigned active = spi->mode & SPI_CS_HIGH;
295 if (atmel_spi_is_v2(as)) {
296 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
297 /* For the low SPI version, there is a issue that PDC transfer
298 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
300 spi_writel(as, CSR0, asd->csr);
301 if (as->caps.has_wdrbt) {
303 SPI_BF(PCS, ~(0x01 << spi->chip_select))
309 SPI_BF(PCS, ~(0x01 << spi->chip_select))
314 mr = spi_readl(as, MR);
315 gpio_set_value(asd->npcs_pin, active);
317 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
321 /* Make sure clock polarity is correct */
322 for (i = 0; i < spi->master->num_chipselect; i++) {
323 csr = spi_readl(as, CSR0 + 4 * i);
324 if ((csr ^ cpol) & SPI_BIT(CPOL))
325 spi_writel(as, CSR0 + 4 * i,
326 csr ^ SPI_BIT(CPOL));
329 mr = spi_readl(as, MR);
330 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
331 if (spi->chip_select != 0)
332 gpio_set_value(asd->npcs_pin, active);
333 spi_writel(as, MR, mr);
336 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
337 asd->npcs_pin, active ? " (high)" : "",
341 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
343 struct atmel_spi_device *asd = spi->controller_state;
344 unsigned active = spi->mode & SPI_CS_HIGH;
347 /* only deactivate *this* device; sometimes transfers to
348 * another device may be active when this routine is called.
350 mr = spi_readl(as, MR);
351 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
352 mr = SPI_BFINS(PCS, 0xf, mr);
353 spi_writel(as, MR, mr);
356 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
357 asd->npcs_pin, active ? " (low)" : "",
360 if (atmel_spi_is_v2(as) || spi->chip_select != 0)
361 gpio_set_value(asd->npcs_pin, !active);
364 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
366 spin_lock_irqsave(&as->lock, as->flags);
369 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
371 spin_unlock_irqrestore(&as->lock, as->flags);
374 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
375 struct spi_transfer *xfer)
377 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
380 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
381 struct dma_slave_config *slave_config,
386 if (bits_per_word > 8) {
387 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
388 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
390 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
391 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
394 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
395 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
396 slave_config->src_maxburst = 1;
397 slave_config->dst_maxburst = 1;
398 slave_config->device_fc = false;
400 slave_config->direction = DMA_MEM_TO_DEV;
401 if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
402 dev_err(&as->pdev->dev,
403 "failed to configure tx dma channel\n");
407 slave_config->direction = DMA_DEV_TO_MEM;
408 if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
409 dev_err(&as->pdev->dev,
410 "failed to configure rx dma channel\n");
417 static bool filter(struct dma_chan *chan, void *pdata)
419 struct atmel_spi_dma *sl_pdata = pdata;
420 struct at_dma_slave *sl;
425 sl = &sl_pdata->dma_slave;
426 if (sl->dma_dev == chan->device->dev) {
434 static int atmel_spi_configure_dma(struct atmel_spi *as)
436 struct dma_slave_config slave_config;
437 struct device *dev = &as->pdev->dev;
442 dma_cap_set(DMA_SLAVE, mask);
444 as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
447 if (!as->dma.chan_tx) {
449 "DMA TX channel not available, SPI unable to use DMA\n");
454 as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
458 if (!as->dma.chan_rx) {
460 "DMA RX channel not available, SPI unable to use DMA\n");
465 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
469 dev_info(&as->pdev->dev,
470 "Using %s (tx) and %s (rx) for DMA transfers\n",
471 dma_chan_name(as->dma.chan_tx),
472 dma_chan_name(as->dma.chan_rx));
476 dma_release_channel(as->dma.chan_rx);
478 dma_release_channel(as->dma.chan_tx);
482 static void atmel_spi_stop_dma(struct atmel_spi *as)
485 as->dma.chan_rx->device->device_control(as->dma.chan_rx,
486 DMA_TERMINATE_ALL, 0);
488 as->dma.chan_tx->device->device_control(as->dma.chan_tx,
489 DMA_TERMINATE_ALL, 0);
492 static void atmel_spi_release_dma(struct atmel_spi *as)
495 dma_release_channel(as->dma.chan_rx);
497 dma_release_channel(as->dma.chan_tx);
500 /* This function is called by the DMA driver from tasklet context */
501 static void dma_callback(void *data)
503 struct spi_master *master = data;
504 struct atmel_spi *as = spi_master_get_devdata(master);
506 complete(&as->xfer_completion);
510 * Next transfer using PIO.
512 static void atmel_spi_next_xfer_pio(struct spi_master *master,
513 struct spi_transfer *xfer)
515 struct atmel_spi *as = spi_master_get_devdata(master);
516 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
518 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
520 /* Make sure data is not remaining in RDR */
522 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
528 if (xfer->bits_per_word > 8)
529 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
531 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
533 spi_writel(as, TDR, 0);
536 dev_dbg(master->dev.parent,
537 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
538 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
539 xfer->bits_per_word);
541 /* Enable relevant interrupts */
542 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
546 * Submit next transfer for DMA.
548 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
549 struct spi_transfer *xfer,
552 struct atmel_spi *as = spi_master_get_devdata(master);
553 struct dma_chan *rxchan = as->dma.chan_rx;
554 struct dma_chan *txchan = as->dma.chan_tx;
555 struct dma_async_tx_descriptor *rxdesc;
556 struct dma_async_tx_descriptor *txdesc;
557 struct dma_slave_config slave_config;
561 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
563 /* Check that the channels are available */
564 if (!rxchan || !txchan)
567 /* release lock for DMA operations */
568 atmel_spi_unlock(as);
570 /* prepare the RX dma transfer */
571 sg_init_table(&as->dma.sgrx, 1);
573 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
575 as->dma.sgrx.dma_address = as->buffer_dma;
576 if (len > BUFFER_SIZE)
580 /* prepare the TX dma transfer */
581 sg_init_table(&as->dma.sgtx, 1);
583 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
585 as->dma.sgtx.dma_address = as->buffer_dma;
586 if (len > BUFFER_SIZE)
588 memset(as->buffer, 0, len);
591 sg_dma_len(&as->dma.sgtx) = len;
592 sg_dma_len(&as->dma.sgrx) = len;
596 if (atmel_spi_dma_slave_config(as, &slave_config, 8))
599 /* Send both scatterlists */
600 rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
602 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
606 txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
608 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
612 dev_dbg(master->dev.parent,
613 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
614 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
615 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
617 /* Enable relevant interrupts */
618 spi_writel(as, IER, SPI_BIT(OVRES));
620 /* Put the callback on the RX transfer only, that should finish last */
621 rxdesc->callback = dma_callback;
622 rxdesc->callback_param = master;
624 /* Submit and fire RX and TX with TX last so we're ready to read! */
625 cookie = rxdesc->tx_submit(rxdesc);
626 if (dma_submit_error(cookie))
628 cookie = txdesc->tx_submit(txdesc);
629 if (dma_submit_error(cookie))
631 rxchan->device->device_issue_pending(rxchan);
632 txchan->device->device_issue_pending(txchan);
639 spi_writel(as, IDR, SPI_BIT(OVRES));
640 atmel_spi_stop_dma(as);
646 static void atmel_spi_next_xfer_data(struct spi_master *master,
647 struct spi_transfer *xfer,
652 struct atmel_spi *as = spi_master_get_devdata(master);
655 /* use scratch buffer only when rx or tx data is unspecified */
657 *rx_dma = xfer->rx_dma + xfer->len - *plen;
659 *rx_dma = as->buffer_dma;
660 if (len > BUFFER_SIZE)
665 *tx_dma = xfer->tx_dma + xfer->len - *plen;
667 *tx_dma = as->buffer_dma;
668 if (len > BUFFER_SIZE)
670 memset(as->buffer, 0, len);
671 dma_sync_single_for_device(&as->pdev->dev,
672 as->buffer_dma, len, DMA_TO_DEVICE);
678 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
679 struct spi_device *spi,
680 struct spi_transfer *xfer)
683 unsigned long bus_hz;
685 /* v1 chips start out at half the peripheral bus speed. */
686 bus_hz = clk_get_rate(as->clk);
687 if (!atmel_spi_is_v2(as))
691 * Calculate the lowest divider that satisfies the
692 * constraint, assuming div32/fdiv/mbz == 0.
695 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
698 * This can happend if max_speed is null.
699 * In this case, we set the lowest possible speed
704 * If the resulting divider doesn't fit into the
705 * register bitfield, we can't satisfy the constraint.
707 if (scbr >= (1 << SPI_SCBR_SIZE)) {
709 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
710 xfer->speed_hz, scbr, bus_hz/255);
715 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
716 xfer->speed_hz, scbr, bus_hz);
719 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
720 csr = SPI_BFINS(SCBR, scbr, csr);
721 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
727 * Submit next transfer for PDC.
728 * lock is held, spi irq is blocked
730 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
731 struct spi_message *msg,
732 struct spi_transfer *xfer)
734 struct atmel_spi *as = spi_master_get_devdata(master);
736 dma_addr_t tx_dma, rx_dma;
738 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
740 len = as->current_remaining_bytes;
741 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
742 as->current_remaining_bytes -= len;
744 spi_writel(as, RPR, rx_dma);
745 spi_writel(as, TPR, tx_dma);
747 if (msg->spi->bits_per_word > 8)
749 spi_writel(as, RCR, len);
750 spi_writel(as, TCR, len);
752 dev_dbg(&msg->spi->dev,
753 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
754 xfer, xfer->len, xfer->tx_buf,
755 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
756 (unsigned long long)xfer->rx_dma);
758 if (as->current_remaining_bytes) {
759 len = as->current_remaining_bytes;
760 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
761 as->current_remaining_bytes -= len;
763 spi_writel(as, RNPR, rx_dma);
764 spi_writel(as, TNPR, tx_dma);
766 if (msg->spi->bits_per_word > 8)
768 spi_writel(as, RNCR, len);
769 spi_writel(as, TNCR, len);
771 dev_dbg(&msg->spi->dev,
772 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
773 xfer, xfer->len, xfer->tx_buf,
774 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
775 (unsigned long long)xfer->rx_dma);
778 /* REVISIT: We're waiting for ENDRX before we start the next
779 * transfer because we need to handle some difficult timing
780 * issues otherwise. If we wait for ENDTX in one transfer and
781 * then starts waiting for ENDRX in the next, it's difficult
782 * to tell the difference between the ENDRX interrupt we're
783 * actually waiting for and the ENDRX interrupt of the
786 * It should be doable, though. Just not now...
788 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
789 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
793 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
794 * - The buffer is either valid for CPU access, else NULL
795 * - If the buffer is valid, so is its DMA address
797 * This driver manages the dma address unless message->is_dma_mapped.
800 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
802 struct device *dev = &as->pdev->dev;
804 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
806 /* tx_buf is a const void* where we need a void * for the dma
808 void *nonconst_tx = (void *)xfer->tx_buf;
810 xfer->tx_dma = dma_map_single(dev,
811 nonconst_tx, xfer->len,
813 if (dma_mapping_error(dev, xfer->tx_dma))
817 xfer->rx_dma = dma_map_single(dev,
818 xfer->rx_buf, xfer->len,
820 if (dma_mapping_error(dev, xfer->rx_dma)) {
822 dma_unmap_single(dev,
823 xfer->tx_dma, xfer->len,
831 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
832 struct spi_transfer *xfer)
834 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
835 dma_unmap_single(master->dev.parent, xfer->tx_dma,
836 xfer->len, DMA_TO_DEVICE);
837 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
838 dma_unmap_single(master->dev.parent, xfer->rx_dma,
839 xfer->len, DMA_FROM_DEVICE);
842 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
844 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
849 * Must update "current_remaining_bytes" to keep track of data
853 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
857 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
860 if (xfer->bits_per_word > 8) {
861 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
862 *rxp16 = spi_readl(as, RDR);
864 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
865 *rxp = spi_readl(as, RDR);
870 if (xfer->bits_per_word > 8) {
871 if (as->current_remaining_bytes > 2)
872 as->current_remaining_bytes -= 2;
874 as->current_remaining_bytes = 0;
876 as->current_remaining_bytes--;
882 * No need for locking in this Interrupt handler: done_status is the
883 * only information modified.
886 atmel_spi_pio_interrupt(int irq, void *dev_id)
888 struct spi_master *master = dev_id;
889 struct atmel_spi *as = spi_master_get_devdata(master);
890 u32 status, pending, imr;
891 struct spi_transfer *xfer;
894 imr = spi_readl(as, IMR);
895 status = spi_readl(as, SR);
896 pending = status & imr;
898 if (pending & SPI_BIT(OVRES)) {
900 spi_writel(as, IDR, SPI_BIT(OVRES));
901 dev_warn(master->dev.parent, "overrun\n");
904 * When we get an overrun, we disregard the current
905 * transfer. Data will not be copied back from any
906 * bounce buffer and msg->actual_len will not be
907 * updated with the last xfer.
909 * We will also not process any remaning transfers in
912 as->done_status = -EIO;
915 /* Clear any overrun happening while cleaning up */
918 complete(&as->xfer_completion);
920 } else if (pending & SPI_BIT(RDRF)) {
923 if (as->current_remaining_bytes) {
925 xfer = as->current_transfer;
926 atmel_spi_pump_pio_data(as, xfer);
927 if (!as->current_remaining_bytes)
928 spi_writel(as, IDR, pending);
930 complete(&as->xfer_completion);
933 atmel_spi_unlock(as);
935 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
937 spi_writel(as, IDR, pending);
944 atmel_spi_pdc_interrupt(int irq, void *dev_id)
946 struct spi_master *master = dev_id;
947 struct atmel_spi *as = spi_master_get_devdata(master);
948 u32 status, pending, imr;
951 imr = spi_readl(as, IMR);
952 status = spi_readl(as, SR);
953 pending = status & imr;
955 if (pending & SPI_BIT(OVRES)) {
959 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
962 /* Clear any overrun happening while cleaning up */
965 as->done_status = -EIO;
967 complete(&as->xfer_completion);
969 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
972 spi_writel(as, IDR, pending);
974 complete(&as->xfer_completion);
980 static int atmel_spi_setup(struct spi_device *spi)
982 struct atmel_spi *as;
983 struct atmel_spi_device *asd;
985 unsigned int bits = spi->bits_per_word;
986 unsigned int npcs_pin;
989 as = spi_master_get_devdata(spi->master);
991 /* see notes above re chipselect */
992 if (!atmel_spi_is_v2(as)
993 && spi->chip_select == 0
994 && (spi->mode & SPI_CS_HIGH)) {
995 dev_dbg(&spi->dev, "setup: can't be active-high\n");
999 csr = SPI_BF(BITS, bits - 8);
1000 if (spi->mode & SPI_CPOL)
1001 csr |= SPI_BIT(CPOL);
1002 if (!(spi->mode & SPI_CPHA))
1003 csr |= SPI_BIT(NCPHA);
1005 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1007 * DLYBCT would add delays between words, slowing down transfers.
1008 * It could potentially be useful to cope with DMA bottlenecks, but
1009 * in those cases it's probably best to just use a lower bitrate.
1011 csr |= SPI_BF(DLYBS, 0);
1012 csr |= SPI_BF(DLYBCT, 0);
1014 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1015 npcs_pin = (unsigned long)spi->controller_data;
1017 if (gpio_is_valid(spi->cs_gpio))
1018 npcs_pin = spi->cs_gpio;
1020 asd = spi->controller_state;
1022 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1026 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1032 asd->npcs_pin = npcs_pin;
1033 spi->controller_state = asd;
1034 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1040 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1041 bits, spi->mode, spi->chip_select, csr);
1043 if (!atmel_spi_is_v2(as))
1044 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1049 static int atmel_spi_one_transfer(struct spi_master *master,
1050 struct spi_message *msg,
1051 struct spi_transfer *xfer)
1053 struct atmel_spi *as;
1054 struct spi_device *spi = msg->spi;
1057 struct atmel_spi_device *asd;
1061 as = spi_master_get_devdata(master);
1063 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1064 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1068 if (xfer->bits_per_word) {
1069 asd = spi->controller_state;
1070 bits = (asd->csr >> 4) & 0xf;
1071 if (bits != xfer->bits_per_word - 8) {
1073 "you can't yet change bits_per_word in transfers\n");
1074 return -ENOPROTOOPT;
1079 * DMA map early, for performance (empties dcache ASAP) and
1080 * better fault reporting.
1082 if ((!msg->is_dma_mapped)
1083 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1084 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1088 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1090 as->done_status = 0;
1091 as->current_transfer = xfer;
1092 as->current_remaining_bytes = xfer->len;
1093 while (as->current_remaining_bytes) {
1094 reinit_completion(&as->xfer_completion);
1097 atmel_spi_pdc_next_xfer(master, msg, xfer);
1098 } else if (atmel_spi_use_dma(as, xfer)) {
1099 len = as->current_remaining_bytes;
1100 ret = atmel_spi_next_xfer_dma_submit(master,
1104 "unable to use DMA, fallback to PIO\n");
1105 atmel_spi_next_xfer_pio(master, xfer);
1107 as->current_remaining_bytes -= len;
1108 if (as->current_remaining_bytes < 0)
1109 as->current_remaining_bytes = 0;
1112 atmel_spi_next_xfer_pio(master, xfer);
1115 /* interrupts are disabled, so free the lock for schedule */
1116 atmel_spi_unlock(as);
1117 ret = wait_for_completion_timeout(&as->xfer_completion,
1120 if (WARN_ON(ret == 0)) {
1122 "spi trasfer timeout, err %d\n", ret);
1123 as->done_status = -EIO;
1128 if (as->done_status)
1132 if (as->done_status) {
1134 dev_warn(master->dev.parent,
1135 "overrun (%u/%u remaining)\n",
1136 spi_readl(as, TCR), spi_readl(as, RCR));
1139 * Clean up DMA registers and make sure the data
1140 * registers are empty.
1142 spi_writel(as, RNCR, 0);
1143 spi_writel(as, TNCR, 0);
1144 spi_writel(as, RCR, 0);
1145 spi_writel(as, TCR, 0);
1146 for (timeout = 1000; timeout; timeout--)
1147 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1150 dev_warn(master->dev.parent,
1151 "timeout waiting for TXEMPTY");
1152 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1155 /* Clear any overrun happening while cleaning up */
1158 } else if (atmel_spi_use_dma(as, xfer)) {
1159 atmel_spi_stop_dma(as);
1162 if (!msg->is_dma_mapped
1163 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1164 atmel_spi_dma_unmap_xfer(master, xfer);
1169 /* only update length if no error */
1170 msg->actual_length += xfer->len;
1173 if (!msg->is_dma_mapped
1174 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1175 atmel_spi_dma_unmap_xfer(master, xfer);
1177 if (xfer->delay_usecs)
1178 udelay(xfer->delay_usecs);
1180 if (xfer->cs_change) {
1181 if (list_is_last(&xfer->transfer_list,
1185 as->cs_active = !as->cs_active;
1187 cs_activate(as, msg->spi);
1189 cs_deactivate(as, msg->spi);
1196 static int atmel_spi_transfer_one_message(struct spi_master *master,
1197 struct spi_message *msg)
1199 struct atmel_spi *as;
1200 struct spi_transfer *xfer;
1201 struct spi_device *spi = msg->spi;
1204 as = spi_master_get_devdata(master);
1206 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1207 msg, dev_name(&spi->dev));
1210 cs_activate(as, spi);
1212 as->cs_active = true;
1213 as->keep_cs = false;
1216 msg->actual_length = 0;
1218 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1219 ret = atmel_spi_one_transfer(master, msg, xfer);
1225 atmel_spi_disable_pdc_transfer(as);
1227 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1229 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1231 xfer->tx_buf, &xfer->tx_dma,
1232 xfer->rx_buf, &xfer->rx_dma);
1237 cs_deactivate(as, msg->spi);
1239 atmel_spi_unlock(as);
1241 msg->status = as->done_status;
1242 spi_finalize_current_message(spi->master);
1247 static void atmel_spi_cleanup(struct spi_device *spi)
1249 struct atmel_spi_device *asd = spi->controller_state;
1250 unsigned gpio = (unsigned long) spi->controller_data;
1255 spi->controller_state = NULL;
1260 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1262 return spi_readl(as, VERSION) & 0x00000fff;
1265 static void atmel_get_caps(struct atmel_spi *as)
1267 unsigned int version;
1269 version = atmel_get_version(as);
1270 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1272 as->caps.is_spi2 = version > 0x121;
1273 as->caps.has_wdrbt = version >= 0x210;
1274 as->caps.has_dma_support = version >= 0x212;
1277 /*-------------------------------------------------------------------------*/
1279 static int atmel_spi_probe(struct platform_device *pdev)
1281 struct resource *regs;
1285 struct spi_master *master;
1286 struct atmel_spi *as;
1288 /* Select default pin state */
1289 pinctrl_pm_select_default_state(&pdev->dev);
1291 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1295 irq = platform_get_irq(pdev, 0);
1299 clk = devm_clk_get(&pdev->dev, "spi_clk");
1301 return PTR_ERR(clk);
1303 /* setup spi core then atmel-specific driver state */
1305 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1309 /* the spi->mode bits understood by this driver: */
1310 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1311 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1312 master->dev.of_node = pdev->dev.of_node;
1313 master->bus_num = pdev->id;
1314 master->num_chipselect = master->dev.of_node ? 0 : 4;
1315 master->setup = atmel_spi_setup;
1316 master->transfer_one_message = atmel_spi_transfer_one_message;
1317 master->cleanup = atmel_spi_cleanup;
1318 platform_set_drvdata(pdev, master);
1320 as = spi_master_get_devdata(master);
1323 * Scratch buffer is used for throwaway rx and tx data.
1324 * It's coherent to minimize dcache pollution.
1326 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1327 &as->buffer_dma, GFP_KERNEL);
1331 spin_lock_init(&as->lock);
1334 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1335 if (IS_ERR(as->regs)) {
1336 ret = PTR_ERR(as->regs);
1337 goto out_free_buffer;
1339 as->phybase = regs->start;
1343 init_completion(&as->xfer_completion);
1347 as->use_dma = false;
1348 as->use_pdc = false;
1349 if (as->caps.has_dma_support) {
1350 if (atmel_spi_configure_dma(as) == 0)
1356 if (as->caps.has_dma_support && !as->use_dma)
1357 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1360 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1361 0, dev_name(&pdev->dev), master);
1363 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1364 0, dev_name(&pdev->dev), master);
1367 goto out_unmap_regs;
1369 /* Initialize the hardware */
1370 ret = clk_prepare_enable(clk);
1373 spi_writel(as, CR, SPI_BIT(SWRST));
1374 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1375 if (as->caps.has_wdrbt) {
1376 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1379 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1383 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1384 spi_writel(as, CR, SPI_BIT(SPIEN));
1387 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1388 (unsigned long)regs->start, irq);
1390 ret = devm_spi_register_master(&pdev->dev, master);
1398 atmel_spi_release_dma(as);
1400 spi_writel(as, CR, SPI_BIT(SWRST));
1401 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1402 clk_disable_unprepare(clk);
1406 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1409 spi_master_put(master);
1413 static int atmel_spi_remove(struct platform_device *pdev)
1415 struct spi_master *master = platform_get_drvdata(pdev);
1416 struct atmel_spi *as = spi_master_get_devdata(master);
1418 /* reset the hardware and block queue progress */
1419 spin_lock_irq(&as->lock);
1421 atmel_spi_stop_dma(as);
1422 atmel_spi_release_dma(as);
1425 spi_writel(as, CR, SPI_BIT(SWRST));
1426 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1428 spin_unlock_irq(&as->lock);
1430 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1433 clk_disable_unprepare(as->clk);
1438 #ifdef CONFIG_PM_SLEEP
1439 static int atmel_spi_suspend(struct device *dev)
1441 struct spi_master *master = dev_get_drvdata(dev);
1442 struct atmel_spi *as = spi_master_get_devdata(master);
1445 /* Stop the queue running */
1446 ret = spi_master_suspend(master);
1448 dev_warn(dev, "cannot suspend master\n");
1452 clk_disable_unprepare(as->clk);
1454 pinctrl_pm_select_sleep_state(dev);
1459 static int atmel_spi_resume(struct device *dev)
1461 struct spi_master *master = dev_get_drvdata(dev);
1462 struct atmel_spi *as = spi_master_get_devdata(master);
1465 pinctrl_pm_select_default_state(dev);
1467 clk_prepare_enable(as->clk);
1469 /* Start the queue running */
1470 ret = spi_master_resume(master);
1472 dev_err(dev, "problem starting queue (%d)\n", ret);
1477 static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume);
1479 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1481 #define ATMEL_SPI_PM_OPS NULL
1484 #if defined(CONFIG_OF)
1485 static const struct of_device_id atmel_spi_dt_ids[] = {
1486 { .compatible = "atmel,at91rm9200-spi" },
1490 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1493 static struct platform_driver atmel_spi_driver = {
1495 .name = "atmel_spi",
1496 .owner = THIS_MODULE,
1497 .pm = ATMEL_SPI_PM_OPS,
1498 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1500 .probe = atmel_spi_probe,
1501 .remove = atmel_spi_remove,
1503 module_platform_driver(atmel_spi_driver);
1505 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1506 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1507 MODULE_LICENSE("GPL");
1508 MODULE_ALIAS("platform:atmel_spi");