2 * Driver for Broadcom BCM2835 SPI Controllers
4 * Copyright (C) 2012 Chris Boot
5 * Copyright (C) 2013 Stephen Warren
6 * Copyright (C) 2015 Martin Sperl
8 * This driver is inspired by:
9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/clk.h>
24 #include <linux/completion.h>
25 #include <linux/delay.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/spi/spi.h>
37 /* SPI register offsets */
38 #define BCM2835_SPI_CS 0x00
39 #define BCM2835_SPI_FIFO 0x04
40 #define BCM2835_SPI_CLK 0x08
41 #define BCM2835_SPI_DLEN 0x0c
42 #define BCM2835_SPI_LTOH 0x10
43 #define BCM2835_SPI_DC 0x14
46 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
47 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
48 #define BCM2835_SPI_CS_CSPOL2 0x00800000
49 #define BCM2835_SPI_CS_CSPOL1 0x00400000
50 #define BCM2835_SPI_CS_CSPOL0 0x00200000
51 #define BCM2835_SPI_CS_RXF 0x00100000
52 #define BCM2835_SPI_CS_RXR 0x00080000
53 #define BCM2835_SPI_CS_TXD 0x00040000
54 #define BCM2835_SPI_CS_RXD 0x00020000
55 #define BCM2835_SPI_CS_DONE 0x00010000
56 #define BCM2835_SPI_CS_LEN 0x00002000
57 #define BCM2835_SPI_CS_REN 0x00001000
58 #define BCM2835_SPI_CS_ADCS 0x00000800
59 #define BCM2835_SPI_CS_INTR 0x00000400
60 #define BCM2835_SPI_CS_INTD 0x00000200
61 #define BCM2835_SPI_CS_DMAEN 0x00000100
62 #define BCM2835_SPI_CS_TA 0x00000080
63 #define BCM2835_SPI_CS_CSPOL 0x00000040
64 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
65 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
66 #define BCM2835_SPI_CS_CPOL 0x00000008
67 #define BCM2835_SPI_CS_CPHA 0x00000004
68 #define BCM2835_SPI_CS_CS_10 0x00000002
69 #define BCM2835_SPI_CS_CS_01 0x00000001
71 #define BCM2835_SPI_POLLING_LIMIT_US 30
72 #define BCM2835_SPI_TIMEOUT_MS 30000
73 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
74 | SPI_NO_CS | SPI_3WIRE)
76 #define DRV_NAME "spi-bcm2835"
88 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
90 return readl(bs->regs + reg);
93 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
95 writel(val, bs->regs + reg);
98 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
102 while ((bs->rx_len) &&
103 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
104 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
106 *bs->rx_buf++ = byte;
111 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
115 while ((bs->tx_len) &&
116 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
117 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
118 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
123 static void bcm2835_spi_reset_hw(struct spi_master *master)
125 struct bcm2835_spi *bs = spi_master_get_devdata(master);
126 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
128 /* Disable SPI interrupts and transfer */
129 cs &= ~(BCM2835_SPI_CS_INTR |
130 BCM2835_SPI_CS_INTD |
132 /* and reset RX/TX FIFOS */
133 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
135 /* and reset the SPI_HW */
136 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
139 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
141 struct spi_master *master = dev_id;
142 struct bcm2835_spi *bs = spi_master_get_devdata(master);
144 /* Read as many bytes as possible from FIFO */
146 /* Write as many bytes as possible to FIFO */
149 /* based on flags decide if we can finish the transfer */
150 if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
151 /* Transfer complete - reset SPI HW */
152 bcm2835_spi_reset_hw(master);
153 /* wake up the framework */
154 complete(&master->xfer_completion);
160 static int bcm2835_spi_transfer_one_poll(struct spi_master *master,
161 struct spi_device *spi,
162 struct spi_transfer *tfr,
164 unsigned long xfer_time_us)
166 struct bcm2835_spi *bs = spi_master_get_devdata(master);
167 unsigned long timeout = jiffies +
168 max(4 * xfer_time_us * HZ / 1000000, 2uL);
170 /* enable HW block without interrupts */
171 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
173 /* set timeout to 4x the expected time, or 2 jiffies */
174 /* loop until finished the transfer */
176 /* read from fifo as much as possible */
178 /* fill in tx fifo as much as possible */
180 /* if we still expect some data after the read,
181 * check for a possible timeout
183 if (bs->rx_len && time_after(jiffies, timeout)) {
184 /* Transfer complete - reset SPI HW */
185 bcm2835_spi_reset_hw(master);
186 /* and return timeout */
191 /* Transfer complete - reset SPI HW */
192 bcm2835_spi_reset_hw(master);
193 /* and return without waiting for completion */
197 static int bcm2835_spi_transfer_one_irq(struct spi_master *master,
198 struct spi_device *spi,
199 struct spi_transfer *tfr,
202 struct bcm2835_spi *bs = spi_master_get_devdata(master);
204 /* fill in fifo if we have gpio-cs
205 * note that there have been rare events where the native-CS
206 * flapped for <1us which may change the behaviour
207 * with gpio-cs this does not happen, so it is implemented
210 if (gpio_is_valid(spi->cs_gpio)) {
211 /* enable HW block, but without interrupts enabled
212 * this would triggern an immediate interrupt
214 bcm2835_wr(bs, BCM2835_SPI_CS,
215 cs | BCM2835_SPI_CS_TA);
216 /* fill in tx fifo as much as possible */
221 * Enable the HW block. This will immediately trigger a DONE (TX
222 * empty) interrupt, upon which we will fill the TX FIFO with the
223 * first TX bytes. Pre-filling the TX FIFO here to avoid the
224 * interrupt doesn't work:-(
226 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
227 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
229 /* signal that we need to wait for completion */
233 static int bcm2835_spi_transfer_one(struct spi_master *master,
234 struct spi_device *spi,
235 struct spi_transfer *tfr)
237 struct bcm2835_spi *bs = spi_master_get_devdata(master);
238 unsigned long spi_hz, clk_hz, cdiv;
239 unsigned long spi_used_hz, xfer_time_us;
240 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
243 spi_hz = tfr->speed_hz;
244 clk_hz = clk_get_rate(bs->clk);
246 if (spi_hz >= clk_hz / 2) {
247 cdiv = 2; /* clk_hz/2 is the fastest we can go */
249 /* CDIV must be a multiple of two */
250 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
254 cdiv = 0; /* 0 is the slowest we can go */
256 cdiv = 0; /* 0 is the slowest we can go */
258 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
259 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
261 /* handle all the modes */
262 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
263 cs |= BCM2835_SPI_CS_REN;
264 if (spi->mode & SPI_CPOL)
265 cs |= BCM2835_SPI_CS_CPOL;
266 if (spi->mode & SPI_CPHA)
267 cs |= BCM2835_SPI_CS_CPHA;
269 /* for gpio_cs set dummy CS so that no HW-CS get changed
270 * we can not run this in bcm2835_spi_set_cs, as it does
271 * not get called for cs_gpio cases, so we need to do it here
273 if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
274 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
276 /* set transmit buffers and length */
277 bs->tx_buf = tfr->tx_buf;
278 bs->rx_buf = tfr->rx_buf;
279 bs->tx_len = tfr->len;
280 bs->rx_len = tfr->len;
282 /* calculate the estimated time in us the transfer runs */
283 xfer_time_us = tfr->len
284 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */
285 * 1000000 / spi_used_hz;
287 /* for short requests run polling*/
288 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US)
289 return bcm2835_spi_transfer_one_poll(master, spi, tfr,
292 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs);
295 static void bcm2835_spi_handle_err(struct spi_master *master,
296 struct spi_message *msg)
298 bcm2835_spi_reset_hw(master);
301 static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
304 * we can assume that we are "native" as per spi_set_cs
305 * calling us ONLY when cs_gpio is not set
306 * we can also assume that we are CS < 3 as per bcm2835_spi_setup
307 * we would not get called because of error handling there.
308 * the level passed is the electrical level not enabled/disabled
309 * so it has to get translated back to enable/disable
310 * see spi_set_cs in spi.c for the implementation
313 struct spi_master *master = spi->master;
314 struct bcm2835_spi *bs = spi_master_get_devdata(master);
315 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
318 /* calculate the enable flag from the passed gpio_level */
319 enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
321 /* set flags for "reverse" polarity in the registers */
322 if (spi->mode & SPI_CS_HIGH) {
323 /* set the correct CS-bits */
324 cs |= BCM2835_SPI_CS_CSPOL;
325 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
327 /* clean the CS-bits */
328 cs &= ~BCM2835_SPI_CS_CSPOL;
329 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
332 /* select the correct chip_select depending on disabled/enabled */
334 /* set cs correctly */
335 if (spi->mode & SPI_NO_CS) {
336 /* use the "undefined" chip-select */
337 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
339 /* set the chip select */
340 cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
341 cs |= spi->chip_select;
344 /* disable CSPOL which puts HW-CS into deselected state */
345 cs &= ~BCM2835_SPI_CS_CSPOL;
346 /* use the "undefined" chip-select as precaution */
347 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
350 /* finally set the calculated flags in SPI_CS */
351 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
354 static int chip_match_name(struct gpio_chip *chip, void *data)
356 return !strcmp(chip->label, data);
359 static int bcm2835_spi_setup(struct spi_device *spi)
362 struct gpio_chip *chip;
364 * sanity checking the native-chipselects
366 if (spi->mode & SPI_NO_CS)
368 if (gpio_is_valid(spi->cs_gpio))
370 if (spi->chip_select > 1) {
371 /* error in the case of native CS requested with CS > 1
372 * officially there is a CS2, but it is not documented
373 * which GPIO is connected with that...
376 "setup: only two native chip-selects are supported\n");
379 /* now translate native cs to GPIO */
381 /* get the gpio chip for the base */
382 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
386 /* and calculate the real CS */
387 spi->cs_gpio = chip->base + 8 - spi->chip_select;
389 /* and set up the "mode" and level */
390 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
391 spi->chip_select, spi->cs_gpio);
393 /* set up GPIO as output and pull to the correct level */
394 err = gpio_direction_output(spi->cs_gpio,
395 (spi->mode & SPI_CS_HIGH) ? 0 : 1);
398 "could not set CS%i gpio %i as output: %i",
399 spi->chip_select, spi->cs_gpio, err);
402 /* the implementation of pinctrl-bcm2835 currently does not
403 * set the GPIO value when using gpio_direction_output
404 * so we are setting it here explicitly
406 gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
411 static int bcm2835_spi_probe(struct platform_device *pdev)
413 struct spi_master *master;
414 struct bcm2835_spi *bs;
415 struct resource *res;
418 master = spi_alloc_master(&pdev->dev, sizeof(*bs));
420 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
424 platform_set_drvdata(pdev, master);
426 master->mode_bits = BCM2835_SPI_MODE_BITS;
427 master->bits_per_word_mask = SPI_BPW_MASK(8);
428 master->num_chipselect = 3;
429 master->setup = bcm2835_spi_setup;
430 master->set_cs = bcm2835_spi_set_cs;
431 master->transfer_one = bcm2835_spi_transfer_one;
432 master->handle_err = bcm2835_spi_handle_err;
433 master->dev.of_node = pdev->dev.of_node;
435 bs = spi_master_get_devdata(master);
437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
438 bs->regs = devm_ioremap_resource(&pdev->dev, res);
439 if (IS_ERR(bs->regs)) {
440 err = PTR_ERR(bs->regs);
444 bs->clk = devm_clk_get(&pdev->dev, NULL);
445 if (IS_ERR(bs->clk)) {
446 err = PTR_ERR(bs->clk);
447 dev_err(&pdev->dev, "could not get clk: %d\n", err);
451 bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
453 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
454 err = bs->irq ? bs->irq : -ENODEV;
458 clk_prepare_enable(bs->clk);
460 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
461 dev_name(&pdev->dev), master);
463 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
464 goto out_clk_disable;
467 /* initialise the hardware with the default polarities */
468 bcm2835_wr(bs, BCM2835_SPI_CS,
469 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
471 err = devm_spi_register_master(&pdev->dev, master);
473 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
474 goto out_clk_disable;
480 clk_disable_unprepare(bs->clk);
482 spi_master_put(master);
486 static int bcm2835_spi_remove(struct platform_device *pdev)
488 struct spi_master *master = platform_get_drvdata(pdev);
489 struct bcm2835_spi *bs = spi_master_get_devdata(master);
491 /* Clear FIFOs, and disable the HW block */
492 bcm2835_wr(bs, BCM2835_SPI_CS,
493 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
495 clk_disable_unprepare(bs->clk);
500 static const struct of_device_id bcm2835_spi_match[] = {
501 { .compatible = "brcm,bcm2835-spi", },
504 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
506 static struct platform_driver bcm2835_spi_driver = {
509 .of_match_table = bcm2835_spi_match,
511 .probe = bcm2835_spi_probe,
512 .remove = bcm2835_spi_remove,
514 module_platform_driver(bcm2835_spi_driver);
516 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
517 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
518 MODULE_LICENSE("GPL v2");