2 * Broadcom BCM63xx SPI controller support
4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the
19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/clk.h>
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/spi/spi.h>
31 #include <linux/completion.h>
32 #include <linux/err.h>
33 #include <linux/workqueue.h>
34 #include <linux/pm_runtime.h>
36 #include <bcm63xx_dev_spi.h>
38 #define PFX KBUILD_MODNAME
40 #define BCM63XX_SPI_MAX_PREPEND 15
43 struct completion done;
50 unsigned int msg_type_shift;
51 unsigned int msg_ctl_width;
55 const u8 __iomem *rx_io;
58 struct platform_device *pdev;
61 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
64 return bcm_readb(bs->regs + bcm63xx_spireg(offset));
67 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
70 return bcm_readw(bs->regs + bcm63xx_spireg(offset));
73 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
74 u8 value, unsigned int offset)
76 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
79 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
80 u16 value, unsigned int offset)
82 bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
85 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
86 { 20000000, SPI_CLK_20MHZ },
87 { 12500000, SPI_CLK_12_50MHZ },
88 { 6250000, SPI_CLK_6_250MHZ },
89 { 3125000, SPI_CLK_3_125MHZ },
90 { 1563000, SPI_CLK_1_563MHZ },
91 { 781000, SPI_CLK_0_781MHZ },
92 { 391000, SPI_CLK_0_391MHZ }
95 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
96 struct spi_transfer *t)
98 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
102 /* Find the closest clock configuration */
103 for (i = 0; i < SPI_CLK_MASK; i++) {
104 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
105 clk_cfg = bcm63xx_spi_freq_table[i][1];
110 /* No matching configuration found, default to lowest */
111 if (i == SPI_CLK_MASK)
112 clk_cfg = SPI_CLK_0_391MHZ;
114 /* clear existing clock configuration bits of the register */
115 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
116 reg &= ~SPI_CLK_MASK;
119 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
120 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
121 clk_cfg, t->speed_hz);
124 /* the spi->mode bits understood by this driver: */
125 #define MODEBITS (SPI_CPOL | SPI_CPHA)
127 static int bcm63xx_spi_setup(struct spi_device *spi)
129 if (spi->bits_per_word != 8) {
130 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
131 __func__, spi->bits_per_word);
138 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
139 unsigned int num_transfers)
141 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
145 unsigned int i, timeout = 0, prepend_len = 0, len = 0;
146 struct spi_transfer *t = first;
150 /* Disable the CMD_DONE interrupt */
151 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
153 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
154 t->tx_buf, t->rx_buf, t->len);
156 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
157 prepend_len = t->len;
159 /* prepare the buffer */
160 for (i = 0; i < num_transfers; i++) {
163 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
165 /* don't prepend more than one tx */
172 /* prepend is half-duplex write only */
179 t = list_entry(t->transfer_list.next, struct spi_transfer,
185 init_completion(&bs->done);
187 /* Fill in the Message control register */
188 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
190 if (do_rx && do_tx && prepend_len == 0)
191 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
193 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
195 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
197 switch (bs->msg_ctl_width) {
199 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
202 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
206 /* Issue the transfer */
207 cmd = SPI_CMD_START_IMMEDIATE;
208 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
209 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
210 bcm_spi_writew(bs, cmd, SPI_CMD);
212 /* Enable the CMD_DONE interrupt */
213 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
215 timeout = wait_for_completion_timeout(&bs->done, HZ);
219 /* read out all data */
220 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
222 if (do_rx && rx_tail != len)
230 /* Read out all the data */
231 for (i = 0; i < num_transfers; i++) {
233 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
235 if (t != first || prepend_len == 0)
238 t = list_entry(t->transfer_list.next, struct spi_transfer,
245 static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
247 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
249 pm_runtime_get_sync(&bs->pdev->dev);
254 static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
256 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
258 pm_runtime_put(&bs->pdev->dev);
263 static int bcm63xx_spi_transfer_one(struct spi_master *master,
264 struct spi_message *m)
266 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
267 struct spi_transfer *t, *first = NULL;
268 struct spi_device *spi = m->spi;
270 unsigned int n_transfers = 0, total_len = 0;
271 bool can_use_prepend = false;
274 * This SPI controller does not support keeping CS active after a
276 * Work around this by merging as many transfers we can into one big
277 * full-duplex transfers.
279 list_for_each_entry(t, &m->transfers, transfer_list) {
280 if (t->bits_per_word != 8) {
281 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
282 __func__, t->bits_per_word);
293 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
294 first->len <= BCM63XX_SPI_MAX_PREPEND)
295 can_use_prepend = true;
296 else if (can_use_prepend && t->tx_buf)
297 can_use_prepend = false;
299 /* we can only transfer one fifo worth of data */
300 if ((can_use_prepend &&
301 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
302 (!can_use_prepend && total_len > bs->fifo_size)) {
303 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
304 total_len, bs->fifo_size);
309 /* all combined transfers have to have the same speed */
310 if (t->speed_hz != first->speed_hz) {
311 dev_err(&spi->dev, "unable to change speed between transfers\n");
316 /* CS will be deasserted directly after transfer */
317 if (t->delay_usecs) {
318 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
324 list_is_last(&t->transfer_list, &m->transfers)) {
325 /* configure adapter for a new transfer */
326 bcm63xx_spi_setup_transfer(spi, first);
329 status = bcm63xx_txrx_bufs(spi, first, n_transfers);
333 m->actual_length += total_len;
338 can_use_prepend = false;
343 spi_finalize_current_message(master);
348 /* This driver supports single master mode only. Hence
349 * CMD_DONE is the only interrupt we care about
351 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
353 struct spi_master *master = (struct spi_master *)dev_id;
354 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
357 /* Read interupts and clear them immediately */
358 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
359 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
360 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
362 /* A transfer completed */
363 if (intr & SPI_INTR_CMD_DONE)
370 static int bcm63xx_spi_probe(struct platform_device *pdev)
373 struct device *dev = &pdev->dev;
374 struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
376 struct spi_master *master;
378 struct bcm63xx_spi *bs;
381 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383 dev_err(dev, "no iomem\n");
388 irq = platform_get_irq(pdev, 0);
390 dev_err(dev, "no irq\n");
395 clk = clk_get(dev, "spi");
397 dev_err(dev, "no clock for device\n");
402 master = spi_alloc_master(dev, sizeof(*bs));
404 dev_err(dev, "out of memory\n");
409 bs = spi_master_get_devdata(master);
411 platform_set_drvdata(pdev, master);
414 bs->regs = devm_ioremap_resource(&pdev->dev, r);
415 if (IS_ERR(bs->regs)) {
416 ret = PTR_ERR(bs->regs);
422 bs->fifo_size = pdata->fifo_size;
424 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
427 dev_err(dev, "unable to request irq\n");
431 master->bus_num = pdata->bus_num;
432 master->num_chipselect = pdata->num_chipselect;
433 master->setup = bcm63xx_spi_setup;
434 master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
435 master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
436 master->transfer_one_message = bcm63xx_spi_transfer_one;
437 master->mode_bits = MODEBITS;
438 bs->msg_type_shift = pdata->msg_type_shift;
439 bs->msg_ctl_width = pdata->msg_ctl_width;
440 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
441 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
443 switch (bs->msg_ctl_width) {
448 dev_err(dev, "unsupported MSG_CTL width: %d\n",
453 /* Initialize hardware */
454 clk_prepare_enable(bs->clk);
455 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
457 /* register and we are done */
458 ret = spi_register_master(master);
460 dev_err(dev, "spi register failed\n");
461 goto out_clk_disable;
464 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
465 r->start, irq, bs->fifo_size);
470 clk_disable_unprepare(clk);
472 platform_set_drvdata(pdev, NULL);
473 spi_master_put(master);
480 static int bcm63xx_spi_remove(struct platform_device *pdev)
482 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
483 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
485 spi_unregister_master(master);
487 /* reset spi block */
488 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
491 clk_disable_unprepare(bs->clk);
494 platform_set_drvdata(pdev, 0);
496 spi_master_put(master);
502 static int bcm63xx_spi_suspend(struct device *dev)
504 struct spi_master *master =
505 platform_get_drvdata(to_platform_device(dev));
506 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
508 spi_master_suspend(master);
510 clk_disable_unprepare(bs->clk);
515 static int bcm63xx_spi_resume(struct device *dev)
517 struct spi_master *master =
518 platform_get_drvdata(to_platform_device(dev));
519 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
521 clk_prepare_enable(bs->clk);
523 spi_master_resume(master);
528 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
529 .suspend = bcm63xx_spi_suspend,
530 .resume = bcm63xx_spi_resume,
533 #define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
535 #define BCM63XX_SPI_PM_OPS NULL
538 static struct platform_driver bcm63xx_spi_driver = {
540 .name = "bcm63xx-spi",
541 .owner = THIS_MODULE,
542 .pm = BCM63XX_SPI_PM_OPS,
544 .probe = bcm63xx_spi_probe,
545 .remove = bcm63xx_spi_remove,
548 module_platform_driver(bcm63xx_spi_driver);
550 MODULE_ALIAS("platform:bcm63xx_spi");
551 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
552 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
553 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
554 MODULE_LICENSE("GPL");