2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/interrupt.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/edma.h>
28 #include <linux/of_device.h>
29 #include <linux/of_gpio.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/slab.h>
34 #include <linux/platform_data/spi-davinci.h>
36 #define SPI_NO_RESOURCE ((resource_size_t)-1)
38 #define CS_DEFAULT 0xFF
40 #define SPIFMT_PHASE_MASK BIT(16)
41 #define SPIFMT_POLARITY_MASK BIT(17)
42 #define SPIFMT_DISTIMER_MASK BIT(18)
43 #define SPIFMT_SHIFTDIR_MASK BIT(20)
44 #define SPIFMT_WAITENA_MASK BIT(21)
45 #define SPIFMT_PARITYENA_MASK BIT(22)
46 #define SPIFMT_ODD_PARITY_MASK BIT(23)
47 #define SPIFMT_WDELAY_MASK 0x3f000000u
48 #define SPIFMT_WDELAY_SHIFT 24
49 #define SPIFMT_PRESCALE_SHIFT 8
52 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
53 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
54 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
55 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
57 #define SPIINT_MASKALL 0x0101035F
58 #define SPIINT_MASKINT 0x0000015F
59 #define SPI_INTLVL_1 0x000001FF
60 #define SPI_INTLVL_0 0x00000000
62 /* SPIDAT1 (upper 16 bit defines) */
63 #define SPIDAT1_CSHOLD_MASK BIT(12)
64 #define SPIDAT1_WDEL BIT(10)
67 #define SPIGCR1_CLKMOD_MASK BIT(1)
68 #define SPIGCR1_MASTER_MASK BIT(0)
69 #define SPIGCR1_POWERDOWN_MASK BIT(8)
70 #define SPIGCR1_LOOPBACK_MASK BIT(16)
71 #define SPIGCR1_SPIENA_MASK BIT(24)
74 #define SPIBUF_TXFULL_MASK BIT(29)
75 #define SPIBUF_RXEMPTY_MASK BIT(31)
78 #define SPIDELAY_C2TDELAY_SHIFT 24
79 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
80 #define SPIDELAY_T2CDELAY_SHIFT 16
81 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
82 #define SPIDELAY_T2EDELAY_SHIFT 8
83 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
84 #define SPIDELAY_C2EDELAY_SHIFT 0
85 #define SPIDELAY_C2EDELAY_MASK 0xFF
88 #define SPIFLG_DLEN_ERR_MASK BIT(0)
89 #define SPIFLG_TIMEOUT_MASK BIT(1)
90 #define SPIFLG_PARERR_MASK BIT(2)
91 #define SPIFLG_DESYNC_MASK BIT(3)
92 #define SPIFLG_BITERR_MASK BIT(4)
93 #define SPIFLG_OVRRUN_MASK BIT(6)
94 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
95 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
96 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
97 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
100 #define SPIINT_DMA_REQ_EN BIT(16)
102 /* SPI Controller registers */
111 #define SPIDELAY 0x48
115 /* SPI Controller driver's private data. */
117 struct spi_bitbang bitbang;
121 resource_size_t pbase;
124 struct completion done;
131 struct dma_chan *dma_rx;
132 struct dma_chan *dma_tx;
136 struct davinci_spi_platform_data pdata;
138 void (*get_rx)(u32 rx_data, struct davinci_spi *);
139 u32 (*get_tx)(struct davinci_spi *);
144 static struct davinci_spi_config davinci_spi_default_cfg;
146 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
155 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
164 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
169 const u8 *tx = dspi->tx;
177 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
182 const u16 *tx = dspi->tx;
190 static inline void set_io_bits(void __iomem *addr, u32 bits)
192 u32 v = ioread32(addr);
198 static inline void clear_io_bits(void __iomem *addr, u32 bits)
200 u32 v = ioread32(addr);
207 * Interface to control the chip select signal
209 static void davinci_spi_chipselect(struct spi_device *spi, int value)
211 struct davinci_spi *dspi;
212 struct davinci_spi_platform_data *pdata;
213 struct davinci_spi_config *spicfg = spi->controller_data;
214 u8 chip_sel = spi->chip_select;
215 u16 spidat1 = CS_DEFAULT;
216 bool gpio_chipsel = false;
219 dspi = spi_master_get_devdata(spi->master);
220 pdata = &dspi->pdata;
222 if (spi->cs_gpio >= 0) {
223 /* SPI core parse and update master->cs_gpio */
228 /* program delay transfers if tx_delay is non zero */
230 spidat1 |= SPIDAT1_WDEL;
233 * Board specific chip select logic decides the polarity and cs
234 * line for the controller
237 if (value == BITBANG_CS_ACTIVE)
238 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH);
240 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH));
242 if (value == BITBANG_CS_ACTIVE) {
243 spidat1 |= SPIDAT1_CSHOLD_MASK;
244 spidat1 &= ~(0x1 << chip_sel);
248 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
252 * davinci_spi_get_prescale - Calculates the correct prescale value
253 * @maxspeed_hz: the maximum rate the SPI clock can run at
255 * This function calculates the prescale value that generates a clock rate
256 * less than or equal to the specified maximum.
258 * Returns: calculated prescale value for easy programming into SPI registers
259 * or negative error number if valid prescalar cannot be updated.
261 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
266 /* Subtract 1 to match what will be programmed into SPI register. */
267 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
269 if (ret < 0 || ret > 255)
276 * davinci_spi_setup_transfer - This functions will determine transfer method
277 * @spi: spi device on which data transfer to be done
278 * @t: spi transfer in which transfer info is filled
280 * This function determines data transfer method (8/16/32 bit transfer).
281 * It will also set the SPI Clock Control register according to
282 * SPI slave device freq.
284 static int davinci_spi_setup_transfer(struct spi_device *spi,
285 struct spi_transfer *t)
288 struct davinci_spi *dspi;
289 struct davinci_spi_config *spicfg;
290 u8 bits_per_word = 0;
291 u32 hz = 0, spifmt = 0;
294 dspi = spi_master_get_devdata(spi->master);
295 spicfg = spi->controller_data;
297 spicfg = &davinci_spi_default_cfg;
300 bits_per_word = t->bits_per_word;
304 /* if bits_per_word is not set then set it default */
306 bits_per_word = spi->bits_per_word;
309 * Assign function pointer to appropriate transfer method
310 * 8bit, 16bit or 32bit transfer
312 if (bits_per_word <= 8) {
313 dspi->get_rx = davinci_spi_rx_buf_u8;
314 dspi->get_tx = davinci_spi_tx_buf_u8;
315 dspi->bytes_per_word[spi->chip_select] = 1;
317 dspi->get_rx = davinci_spi_rx_buf_u16;
318 dspi->get_tx = davinci_spi_tx_buf_u16;
319 dspi->bytes_per_word[spi->chip_select] = 2;
323 hz = spi->max_speed_hz;
325 /* Set up SPIFMTn register, unique to this chipselect. */
327 prescale = davinci_spi_get_prescale(dspi, hz);
331 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
333 if (spi->mode & SPI_LSB_FIRST)
334 spifmt |= SPIFMT_SHIFTDIR_MASK;
336 if (spi->mode & SPI_CPOL)
337 spifmt |= SPIFMT_POLARITY_MASK;
339 if (!(spi->mode & SPI_CPHA))
340 spifmt |= SPIFMT_PHASE_MASK;
343 * Assume wdelay is used only on SPI peripherals that has this field
344 * in SPIFMTn register and when it's configured from board file or DT.
347 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
348 & SPIFMT_WDELAY_MASK);
351 * Version 1 hardware supports two basic SPI modes:
352 * - Standard SPI mode uses 4 pins, with chipselect
353 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
354 * (distinct from SPI_3WIRE, with just one data wire;
355 * or similar variants without MOSI or without MISO)
357 * Version 2 hardware supports an optional handshaking signal,
358 * so it can support two more modes:
359 * - 5 pin SPI variant is standard SPI plus SPI_READY
360 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
363 if (dspi->version == SPI_VERSION_2) {
367 if (spicfg->odd_parity)
368 spifmt |= SPIFMT_ODD_PARITY_MASK;
370 if (spicfg->parity_enable)
371 spifmt |= SPIFMT_PARITYENA_MASK;
373 if (spicfg->timer_disable) {
374 spifmt |= SPIFMT_DISTIMER_MASK;
376 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
377 & SPIDELAY_C2TDELAY_MASK;
378 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
379 & SPIDELAY_T2CDELAY_MASK;
382 if (spi->mode & SPI_READY) {
383 spifmt |= SPIFMT_WAITENA_MASK;
384 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
385 & SPIDELAY_T2EDELAY_MASK;
386 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
387 & SPIDELAY_C2EDELAY_MASK;
390 iowrite32(delay, dspi->base + SPIDELAY);
393 iowrite32(spifmt, dspi->base + SPIFMT0);
398 static int davinci_spi_of_setup(struct spi_device *spi)
400 struct davinci_spi_config *spicfg = spi->controller_data;
401 struct device_node *np = spi->dev.of_node;
404 if (spicfg == NULL && np) {
405 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);
408 *spicfg = davinci_spi_default_cfg;
409 /* override with dt configured values */
410 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))
411 spicfg->wdelay = (u8)prop;
412 spi->controller_data = spicfg;
419 * davinci_spi_setup - This functions will set default transfer method
420 * @spi: spi device on which data transfer to be done
422 * This functions sets the default transfer method.
424 static int davinci_spi_setup(struct spi_device *spi)
427 struct davinci_spi *dspi;
428 struct davinci_spi_platform_data *pdata;
429 struct spi_master *master = spi->master;
430 struct device_node *np = spi->dev.of_node;
431 bool internal_cs = true;
433 dspi = spi_master_get_devdata(spi->master);
434 pdata = &dspi->pdata;
436 if (!(spi->mode & SPI_NO_CS)) {
437 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) {
438 retval = gpio_direction_output(
439 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
441 } else if (pdata->chip_sel &&
442 spi->chip_select < pdata->num_chipselect &&
443 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) {
444 spi->cs_gpio = pdata->chip_sel[spi->chip_select];
445 retval = gpio_direction_output(
446 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
451 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n",
452 spi->cs_gpio, retval);
457 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
460 if (spi->mode & SPI_READY)
461 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
463 if (spi->mode & SPI_LOOP)
464 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
466 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
468 return davinci_spi_of_setup(spi);
471 static void davinci_spi_cleanup(struct spi_device *spi)
473 struct davinci_spi_config *spicfg = spi->controller_data;
475 spi->controller_data = NULL;
476 if (spi->dev.of_node)
480 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
482 struct device *sdev = dspi->bitbang.master->dev.parent;
484 if (int_status & SPIFLG_TIMEOUT_MASK) {
485 dev_dbg(sdev, "SPI Time-out Error\n");
488 if (int_status & SPIFLG_DESYNC_MASK) {
489 dev_dbg(sdev, "SPI Desynchronization Error\n");
492 if (int_status & SPIFLG_BITERR_MASK) {
493 dev_dbg(sdev, "SPI Bit error\n");
497 if (dspi->version == SPI_VERSION_2) {
498 if (int_status & SPIFLG_DLEN_ERR_MASK) {
499 dev_dbg(sdev, "SPI Data Length Error\n");
502 if (int_status & SPIFLG_PARERR_MASK) {
503 dev_dbg(sdev, "SPI Parity Error\n");
506 if (int_status & SPIFLG_OVRRUN_MASK) {
507 dev_dbg(sdev, "SPI Data Overrun error\n");
510 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
511 dev_dbg(sdev, "SPI Buffer Init Active\n");
520 * davinci_spi_process_events - check for and handle any SPI controller events
521 * @dspi: the controller data
523 * This function will check the SPIFLG register and handle any events that are
526 static int davinci_spi_process_events(struct davinci_spi *dspi)
528 u32 buf, status, errors = 0, spidat1;
530 buf = ioread32(dspi->base + SPIBUF);
532 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
533 dspi->get_rx(buf & 0xFFFF, dspi);
537 status = ioread32(dspi->base + SPIFLG);
539 if (unlikely(status & SPIFLG_ERROR_MASK)) {
540 errors = status & SPIFLG_ERROR_MASK;
544 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
545 spidat1 = ioread32(dspi->base + SPIDAT1);
548 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
549 iowrite32(spidat1, dspi->base + SPIDAT1);
556 static void davinci_spi_dma_rx_callback(void *data)
558 struct davinci_spi *dspi = (struct davinci_spi *)data;
562 if (!dspi->wcount && !dspi->rcount)
563 complete(&dspi->done);
566 static void davinci_spi_dma_tx_callback(void *data)
568 struct davinci_spi *dspi = (struct davinci_spi *)data;
572 if (!dspi->wcount && !dspi->rcount)
573 complete(&dspi->done);
577 * davinci_spi_bufs - functions which will handle transfer data
578 * @spi: spi device on which data transfer to be done
579 * @t: spi transfer in which transfer info is filled
581 * This function will put data to be transferred into data register
582 * of SPI controller and then wait until the completion will be marked
583 * by the IRQ Handler.
585 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
587 struct davinci_spi *dspi;
588 int data_type, ret = -ENOMEM;
589 u32 tx_data, spidat1;
591 struct davinci_spi_config *spicfg;
592 struct davinci_spi_platform_data *pdata;
593 unsigned uninitialized_var(rx_buf_count);
594 void *dummy_buf = NULL;
595 struct scatterlist sg_rx, sg_tx;
597 dspi = spi_master_get_devdata(spi->master);
598 pdata = &dspi->pdata;
599 spicfg = (struct davinci_spi_config *)spi->controller_data;
601 spicfg = &davinci_spi_default_cfg;
603 /* convert len to words based on bits_per_word */
604 data_type = dspi->bytes_per_word[spi->chip_select];
606 dspi->tx = t->tx_buf;
607 dspi->rx = t->rx_buf;
608 dspi->wcount = t->len / data_type;
609 dspi->rcount = dspi->wcount;
611 spidat1 = ioread32(dspi->base + SPIDAT1);
613 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
614 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
616 reinit_completion(&dspi->done);
618 if (spicfg->io_type == SPI_IO_TYPE_INTR)
619 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
621 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
622 /* start the transfer */
624 tx_data = dspi->get_tx(dspi);
625 spidat1 &= 0xFFFF0000;
626 spidat1 |= tx_data & 0xFFFF;
627 iowrite32(spidat1, dspi->base + SPIDAT1);
629 struct dma_slave_config dma_rx_conf = {
630 .direction = DMA_DEV_TO_MEM,
631 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
632 .src_addr_width = data_type,
635 struct dma_slave_config dma_tx_conf = {
636 .direction = DMA_MEM_TO_DEV,
637 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
638 .dst_addr_width = data_type,
641 struct dma_async_tx_descriptor *rxdesc;
642 struct dma_async_tx_descriptor *txdesc;
645 dummy_buf = kzalloc(t->len, GFP_KERNEL);
647 goto err_alloc_dummy_buf;
649 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
650 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
652 sg_init_table(&sg_rx, 1);
657 t->rx_dma = dma_map_single(&spi->dev, buf,
658 t->len, DMA_FROM_DEVICE);
663 sg_dma_address(&sg_rx) = t->rx_dma;
664 sg_dma_len(&sg_rx) = t->len;
666 sg_init_table(&sg_tx, 1);
670 buf = (void *)t->tx_buf;
671 t->tx_dma = dma_map_single(&spi->dev, buf,
672 t->len, DMA_TO_DEVICE);
677 sg_dma_address(&sg_tx) = t->tx_dma;
678 sg_dma_len(&sg_tx) = t->len;
680 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
681 &sg_rx, 1, DMA_DEV_TO_MEM,
682 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
686 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
687 &sg_tx, 1, DMA_MEM_TO_DEV,
688 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
692 rxdesc->callback = davinci_spi_dma_rx_callback;
693 rxdesc->callback_param = (void *)dspi;
694 txdesc->callback = davinci_spi_dma_tx_callback;
695 txdesc->callback_param = (void *)dspi;
697 if (pdata->cshold_bug)
698 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
700 dmaengine_submit(rxdesc);
701 dmaengine_submit(txdesc);
703 dma_async_issue_pending(dspi->dma_rx);
704 dma_async_issue_pending(dspi->dma_tx);
706 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
709 /* Wait for the transfer to complete */
710 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
711 wait_for_completion_interruptible(&(dspi->done));
713 while (dspi->rcount > 0 || dspi->wcount > 0) {
714 errors = davinci_spi_process_events(dspi);
721 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
722 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
723 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
725 dma_unmap_single(&spi->dev, t->rx_dma,
726 t->len, DMA_FROM_DEVICE);
727 dma_unmap_single(&spi->dev, t->tx_dma,
728 t->len, DMA_TO_DEVICE);
732 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
733 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
736 * Check for bit error, desync error,parity error,timeout error and
737 * receive overflow errors
740 ret = davinci_spi_check_error(dspi, errors);
741 WARN(!ret, "%s: error reported but no error found!\n",
742 dev_name(&spi->dev));
746 if (dspi->rcount != 0 || dspi->wcount != 0) {
747 dev_err(&spi->dev, "SPI data transfer error\n");
754 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
756 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
764 * dummy_thread_fn - dummy thread function
765 * @irq: IRQ number for this SPI Master
766 * @context_data: structure for SPI Master controller davinci_spi
768 * This is to satisfy the request_threaded_irq() API so that the irq
769 * handler is called in interrupt context.
771 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
777 * davinci_spi_irq - Interrupt handler for SPI Master Controller
778 * @irq: IRQ number for this SPI Master
779 * @context_data: structure for SPI Master controller davinci_spi
781 * ISR will determine that interrupt arrives either for READ or WRITE command.
782 * According to command it will do the appropriate action. It will check
783 * transfer length and if it is not zero then dispatch transfer command again.
784 * If transfer length is zero then it will indicate the COMPLETION so that
785 * davinci_spi_bufs function can go ahead.
787 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
789 struct davinci_spi *dspi = data;
792 status = davinci_spi_process_events(dspi);
793 if (unlikely(status != 0))
794 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
796 if ((!dspi->rcount && !dspi->wcount) || status)
797 complete(&dspi->done);
802 static int davinci_spi_request_dma(struct davinci_spi *dspi)
805 struct device *sdev = dspi->bitbang.master->dev.parent;
809 dma_cap_set(DMA_SLAVE, mask);
811 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
812 &dspi->dma_rx_chnum);
814 dev_err(sdev, "request RX DMA channel failed\n");
819 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
820 &dspi->dma_tx_chnum);
822 dev_err(sdev, "request TX DMA channel failed\n");
830 dma_release_channel(dspi->dma_rx);
835 #if defined(CONFIG_OF)
836 static const struct of_device_id davinci_spi_of_match[] = {
838 .compatible = "ti,dm6441-spi",
841 .compatible = "ti,da830-spi",
842 .data = (void *)SPI_VERSION_2,
846 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
849 * spi_davinci_get_pdata - Get platform data from DTS binding
850 * @pdev: ptr to platform data
851 * @dspi: ptr to driver data
853 * Parses and populates pdata in dspi from device tree bindings.
855 * NOTE: Not all platform data params are supported currently.
857 static int spi_davinci_get_pdata(struct platform_device *pdev,
858 struct davinci_spi *dspi)
860 struct device_node *node = pdev->dev.of_node;
861 struct davinci_spi_platform_data *pdata;
862 unsigned int num_cs, intr_line = 0;
863 const struct of_device_id *match;
865 pdata = &dspi->pdata;
867 pdata->version = SPI_VERSION_1;
868 match = of_match_device(davinci_spi_of_match, &pdev->dev);
872 /* match data has the SPI version number for SPI_VERSION_2 */
873 if (match->data == (void *)SPI_VERSION_2)
874 pdata->version = SPI_VERSION_2;
877 * default num_cs is 1 and all chipsel are internal to the chip
878 * indicated by chip_sel being NULL or cs_gpios being NULL or
879 * set to -ENOENT. num-cs includes internal as well as gpios.
880 * indicated by chip_sel being NULL. GPIO based CS is not
881 * supported yet in DT bindings.
884 of_property_read_u32(node, "num-cs", &num_cs);
885 pdata->num_chipselect = num_cs;
886 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
887 pdata->intr_line = intr_line;
891 static struct davinci_spi_platform_data
892 *spi_davinci_get_pdata(struct platform_device *pdev,
893 struct davinci_spi *dspi)
900 * davinci_spi_probe - probe function for SPI Master Controller
901 * @pdev: platform_device structure which contains plateform specific data
903 * According to Linux Device Model this function will be invoked by Linux
904 * with platform_device struct which contains the device specific info.
905 * This function will map the SPI controller's memory, register IRQ,
906 * Reset SPI controller and setting its registers to default value.
907 * It will invoke spi_bitbang_start to create work queue so that client driver
908 * can register transfer method to work queue.
910 static int davinci_spi_probe(struct platform_device *pdev)
912 struct spi_master *master;
913 struct davinci_spi *dspi;
914 struct davinci_spi_platform_data *pdata;
916 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
917 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
921 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
922 if (master == NULL) {
927 platform_set_drvdata(pdev, master);
929 dspi = spi_master_get_devdata(master);
931 if (dev_get_platdata(&pdev->dev)) {
932 pdata = dev_get_platdata(&pdev->dev);
933 dspi->pdata = *pdata;
935 /* update dspi pdata with that from the DT */
936 ret = spi_davinci_get_pdata(pdev, dspi);
941 /* pdata in dspi is now updated and point pdata to that */
942 pdata = &dspi->pdata;
944 dspi->bytes_per_word = devm_kzalloc(&pdev->dev,
945 sizeof(*dspi->bytes_per_word) *
946 pdata->num_chipselect, GFP_KERNEL);
947 if (dspi->bytes_per_word == NULL) {
952 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
958 dspi->pbase = r->start;
960 dspi->base = devm_ioremap_resource(&pdev->dev, r);
961 if (IS_ERR(dspi->base)) {
962 ret = PTR_ERR(dspi->base);
966 dspi->irq = platform_get_irq(pdev, 0);
967 if (dspi->irq <= 0) {
972 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
973 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
977 dspi->bitbang.master = master;
979 dspi->clk = devm_clk_get(&pdev->dev, NULL);
980 if (IS_ERR(dspi->clk)) {
984 clk_prepare_enable(dspi->clk);
986 master->dev.of_node = pdev->dev.of_node;
987 master->bus_num = pdev->id;
988 master->num_chipselect = pdata->num_chipselect;
989 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
990 master->setup = davinci_spi_setup;
991 master->cleanup = davinci_spi_cleanup;
993 dspi->bitbang.chipselect = davinci_spi_chipselect;
994 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
996 dspi->version = pdata->version;
998 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
999 if (dspi->version == SPI_VERSION_2)
1000 dspi->bitbang.flags |= SPI_READY;
1002 if (pdev->dev.of_node) {
1005 for (i = 0; i < pdata->num_chipselect; i++) {
1006 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1009 if (cs_gpio == -EPROBE_DEFER) {
1014 if (gpio_is_valid(cs_gpio)) {
1015 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1016 dev_name(&pdev->dev));
1023 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1025 dma_rx_chan = r->start;
1026 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1028 dma_tx_chan = r->start;
1030 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
1031 if (dma_rx_chan != SPI_NO_RESOURCE &&
1032 dma_tx_chan != SPI_NO_RESOURCE) {
1033 dspi->dma_rx_chnum = dma_rx_chan;
1034 dspi->dma_tx_chnum = dma_tx_chan;
1036 ret = davinci_spi_request_dma(dspi);
1040 dev_info(&pdev->dev, "DMA: supported\n");
1041 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, event queue: %d\n",
1042 &dma_rx_chan, &dma_tx_chan,
1043 pdata->dma_event_q);
1046 dspi->get_rx = davinci_spi_rx_buf_u8;
1047 dspi->get_tx = davinci_spi_tx_buf_u8;
1049 init_completion(&dspi->done);
1051 /* Reset In/OUT SPI module */
1052 iowrite32(0, dspi->base + SPIGCR0);
1054 iowrite32(1, dspi->base + SPIGCR0);
1056 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
1057 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
1058 iowrite32(spipc0, dspi->base + SPIPC0);
1060 if (pdata->intr_line)
1061 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
1063 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
1065 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
1067 /* master mode default */
1068 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1069 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1070 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
1072 ret = spi_bitbang_start(&dspi->bitbang);
1076 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1081 dma_release_channel(dspi->dma_rx);
1082 dma_release_channel(dspi->dma_tx);
1084 clk_disable_unprepare(dspi->clk);
1086 spi_master_put(master);
1092 * davinci_spi_remove - remove function for SPI Master Controller
1093 * @pdev: platform_device structure which contains plateform specific data
1095 * This function will do the reverse action of davinci_spi_probe function
1096 * It will free the IRQ and SPI controller's memory region.
1097 * It will also call spi_bitbang_stop to destroy the work queue which was
1098 * created by spi_bitbang_start.
1100 static int davinci_spi_remove(struct platform_device *pdev)
1102 struct davinci_spi *dspi;
1103 struct spi_master *master;
1105 master = platform_get_drvdata(pdev);
1106 dspi = spi_master_get_devdata(master);
1108 spi_bitbang_stop(&dspi->bitbang);
1110 clk_disable_unprepare(dspi->clk);
1111 spi_master_put(master);
1116 static struct platform_driver davinci_spi_driver = {
1118 .name = "spi_davinci",
1119 .of_match_table = of_match_ptr(davinci_spi_of_match),
1121 .probe = davinci_spi_probe,
1122 .remove = davinci_spi_remove,
1124 module_platform_driver(davinci_spi_driver);
1126 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1127 MODULE_LICENSE("GPL");