1 #ifndef DW_SPI_HEADER_H
2 #define DW_SPI_HEADER_H
5 #include <linux/scatterlist.h>
6 #include <linux/gpio.h>
9 #define DW_SPI_CTRL0 0x00
10 #define DW_SPI_CTRL1 0x04
11 #define DW_SPI_SSIENR 0x08
12 #define DW_SPI_MWCR 0x0c
13 #define DW_SPI_SER 0x10
14 #define DW_SPI_BAUDR 0x14
15 #define DW_SPI_TXFLTR 0x18
16 #define DW_SPI_RXFLTR 0x1c
17 #define DW_SPI_TXFLR 0x20
18 #define DW_SPI_RXFLR 0x24
19 #define DW_SPI_SR 0x28
20 #define DW_SPI_IMR 0x2c
21 #define DW_SPI_ISR 0x30
22 #define DW_SPI_RISR 0x34
23 #define DW_SPI_TXOICR 0x38
24 #define DW_SPI_RXOICR 0x3c
25 #define DW_SPI_RXUICR 0x40
26 #define DW_SPI_MSTICR 0x44
27 #define DW_SPI_ICR 0x48
28 #define DW_SPI_DMACR 0x4c
29 #define DW_SPI_DMATDLR 0x50
30 #define DW_SPI_DMARDLR 0x54
31 #define DW_SPI_IDR 0x58
32 #define DW_SPI_VERSION 0x5c
33 #define DW_SPI_DR 0x60
35 /* Bit fields in CTRLR0 */
36 #define SPI_DFS_OFFSET 0
38 #define SPI_FRF_OFFSET 4
39 #define SPI_FRF_SPI 0x0
40 #define SPI_FRF_SSP 0x1
41 #define SPI_FRF_MICROWIRE 0x2
42 #define SPI_FRF_RESV 0x3
44 #define SPI_MODE_OFFSET 6
45 #define SPI_SCPH_OFFSET 6
46 #define SPI_SCOL_OFFSET 7
48 #define SPI_TMOD_OFFSET 8
49 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
50 #define SPI_TMOD_TR 0x0 /* xmit & recv */
51 #define SPI_TMOD_TO 0x1 /* xmit only */
52 #define SPI_TMOD_RO 0x2 /* recv only */
53 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
55 #define SPI_SLVOE_OFFSET 10
56 #define SPI_SRL_OFFSET 11
57 #define SPI_CFS_OFFSET 12
59 /* Bit fields in SR, 7 bits */
60 #define SR_MASK 0x7f /* cover 7 bits */
61 #define SR_BUSY (1 << 0)
62 #define SR_TF_NOT_FULL (1 << 1)
63 #define SR_TF_EMPT (1 << 2)
64 #define SR_RF_NOT_EMPT (1 << 3)
65 #define SR_RF_FULL (1 << 4)
66 #define SR_TX_ERR (1 << 5)
67 #define SR_DCOL (1 << 6)
69 /* Bit fields in ISR, IMR, RISR, 7 bits */
70 #define SPI_INT_TXEI (1 << 0)
71 #define SPI_INT_TXOI (1 << 1)
72 #define SPI_INT_RXUI (1 << 2)
73 #define SPI_INT_RXOI (1 << 3)
74 #define SPI_INT_RXFI (1 << 4)
75 #define SPI_INT_MSTI (1 << 5)
77 /* Bit fields in DMACR */
78 #define SPI_DMA_RDMAE (1 << 0)
79 #define SPI_DMA_TDMAE (1 << 1)
81 /* TX RX interrupt level threshold, max can be 256 */
82 #define SPI_INT_THRESHOLD 32
91 struct dw_spi_dma_ops {
92 int (*dma_init)(struct dw_spi *dws);
93 void (*dma_exit)(struct dw_spi *dws);
94 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
95 bool (*can_dma)(struct spi_master *master, struct spi_device *spi,
96 struct spi_transfer *xfer);
97 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
98 void (*dma_stop)(struct dw_spi *dws);
102 struct spi_master *master;
103 enum dw_ssi_type type;
109 u32 fifo_len; /* depth of the FIFO buffer */
110 u32 max_freq; /* max bus freq supported */
113 u16 num_cs; /* supported slave numbers */
115 /* Current message transfer state info */
122 u8 n_bytes; /* current is a 1/2 bytes op */
124 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
128 struct dma_chan *txchan;
129 struct dma_chan *rxchan;
130 unsigned long dma_chan_busy;
131 dma_addr_t dma_addr; /* phy address of the Data register */
132 struct dw_spi_dma_ops *dma_ops;
136 /* Bus interface info */
138 #ifdef CONFIG_DEBUG_FS
139 struct dentry *debugfs;
143 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
145 return __raw_readl(dws->regs + offset);
148 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
150 __raw_writel(val, dws->regs + offset);
153 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
155 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
158 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
160 dw_writel(dws, DW_SPI_BAUDR, div);
163 /* Disable IRQ bits */
164 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
168 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
169 dw_writel(dws, DW_SPI_IMR, new_mask);
172 /* Enable IRQ bits */
173 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
177 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
178 dw_writel(dws, DW_SPI_IMR, new_mask);
182 * This does disable the SPI controller, interrupts, and re-enable the
183 * controller back. Transmit and receive FIFO buffers are cleared when the
184 * device is disabled.
186 static inline void spi_reset_chip(struct dw_spi *dws)
188 spi_enable_chip(dws, 0);
189 spi_mask_intr(dws, 0xff);
190 spi_enable_chip(dws, 1);
194 * Each SPI slave device to work with dw_api controller should
195 * has such a structure claiming its working mode (poll or PIO/DMA),
196 * which can be save in the "controller_data" member of the
200 u8 poll_mode; /* 1 for controller polling mode */
201 u8 type; /* SPI/SSP/MicroWire */
202 void (*cs_control)(u32 command);
205 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
206 extern void dw_spi_remove_host(struct dw_spi *dws);
207 extern int dw_spi_suspend_host(struct dw_spi *dws);
208 extern int dw_spi_resume_host(struct dw_spi *dws);
210 /* platform related setup */
211 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
212 #endif /* DW_SPI_HEADER_H */