2 * drivers/spi/spi-fsl-dspi.c
4 * Copyright 2013 Freescale Semiconductor, Inc.
6 * Freescale DSPI driver
7 * This file contains a driver for the Freescale DSPI
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/errno.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/sched.h>
23 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/spi_bitbang.h>
29 #include <linux/pm_runtime.h>
31 #include <linux/of_device.h>
33 #define DRIVER_NAME "fsl-dspi"
35 #define TRAN_STATE_RX_VOID 0x01
36 #define TRAN_STATE_TX_VOID 0x02
37 #define TRAN_STATE_WORD_ODD_NUM 0x04
39 #define DSPI_FIFO_SIZE 4
42 #define SPI_MCR_MASTER (1 << 31)
43 #define SPI_MCR_PCSIS (0x3F << 16)
44 #define SPI_MCR_CLR_TXF (1 << 11)
45 #define SPI_MCR_CLR_RXF (1 << 10)
49 #define SPI_CTAR(x) (0x0c + (x * 4))
50 #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
51 #define SPI_CTAR_CPOL(x) ((x) << 26)
52 #define SPI_CTAR_CPHA(x) ((x) << 25)
53 #define SPI_CTAR_LSBFE(x) ((x) << 24)
54 #define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
55 #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
56 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
57 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
58 #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
59 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
60 #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
61 #define SPI_CTAR_BR(x) ((x) & 0x0000000f)
63 #define SPI_CTAR0_SLAVE 0x0c
66 #define SPI_SR_EOQF 0x10000000
69 #define SPI_RSER_EOQFE 0x10000000
71 #define SPI_PUSHR 0x34
72 #define SPI_PUSHR_CONT (1 << 31)
73 #define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28)
74 #define SPI_PUSHR_EOQ (1 << 27)
75 #define SPI_PUSHR_CTCNT (1 << 26)
76 #define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
77 #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
79 #define SPI_PUSHR_SLAVE 0x34
82 #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
84 #define SPI_TXFR0 0x3c
85 #define SPI_TXFR1 0x40
86 #define SPI_TXFR2 0x44
87 #define SPI_TXFR3 0x48
88 #define SPI_RXFR0 0x7c
89 #define SPI_RXFR1 0x80
90 #define SPI_RXFR2 0x84
91 #define SPI_RXFR3 0x88
93 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
94 #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
95 #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
96 #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
98 #define SPI_CS_INIT 0x01
99 #define SPI_CS_ASSERT 0x02
100 #define SPI_CS_DROP 0x04
109 struct spi_bitbang bitbang;
110 struct platform_device *pdev;
112 struct regmap *regmap;
116 struct spi_transfer *cur_transfer;
117 struct chip_data *cur_chip;
127 wait_queue_head_t waitq;
131 static inline int is_double_byte_mode(struct fsl_dspi *dspi)
135 regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
137 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
140 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
141 unsigned long clkrate)
143 /* Valid baud rate pre-scaler values */
144 int pbr_tbl[4] = {2, 3, 5, 7};
145 int brs[16] = { 2, 4, 6, 8,
147 256, 512, 1024, 2048,
148 4096, 8192, 16384, 32768 };
149 int temp, i = 0, j = 0;
151 temp = clkrate / 2 / speed_hz;
153 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
154 for (j = 0; j < ARRAY_SIZE(brs); j++) {
155 if (pbr_tbl[i] * brs[j] >= temp) {
162 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
163 ,we use the max prescaler value.\n", speed_hz, clkrate);
164 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
165 *br = ARRAY_SIZE(brs) - 1;
168 static int dspi_transfer_write(struct fsl_dspi *dspi)
177 tx_word = is_double_byte_mode(dspi);
179 /* If we are in word mode, but only have a single byte to transfer
180 * then switch to byte mode temporarily. Will switch back at the
181 * end of the transfer.
183 if (tx_word && (dspi->len == 1)) {
184 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
185 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
186 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
190 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
195 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
196 d16 = *(u16 *)dspi->tx;
199 d16 = dspi->void_write_data;
202 dspi_pushr = SPI_PUSHR_TXDATA(d16) |
203 SPI_PUSHR_PCS(dspi->cs) |
204 SPI_PUSHR_CTAS(dspi->cs) |
209 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
211 d8 = *(u8 *)dspi->tx;
214 d8 = (u8)dspi->void_write_data;
217 dspi_pushr = SPI_PUSHR_TXDATA(d8) |
218 SPI_PUSHR_PCS(dspi->cs) |
219 SPI_PUSHR_CTAS(dspi->cs) |
225 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
226 /* last transfer in the transfer */
227 dspi_pushr |= SPI_PUSHR_EOQ;
228 } else if (tx_word && (dspi->len == 1))
229 dspi_pushr |= SPI_PUSHR_EOQ;
233 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
236 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
241 return tx_count * (tx_word + 1);
244 static int dspi_transfer_read(struct fsl_dspi *dspi)
247 int rx_word = is_double_byte_mode(dspi);
249 while ((dspi->rx < dspi->rx_end)
250 && (rx_count < DSPI_FIFO_SIZE)) {
254 if ((dspi->rx_end - dspi->rx) == 1)
257 regmap_read(dspi->regmap, SPI_POPR, &val);
258 d = SPI_POPR_RXDATA(val);
260 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
261 *(u16 *)dspi->rx = d;
267 regmap_read(dspi->regmap, SPI_POPR, &val);
268 d = SPI_POPR_RXDATA(val);
269 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
279 static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
281 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
282 dspi->cur_transfer = t;
283 dspi->cur_chip = spi_get_ctldata(spi);
284 dspi->cs = spi->chip_select;
285 dspi->void_write_data = dspi->cur_chip->void_write_data;
288 dspi->tx = (void *)t->tx_buf;
289 dspi->tx_end = dspi->tx + t->len;
290 dspi->rx = t->rx_buf;
291 dspi->rx_end = dspi->rx + t->len;
295 dspi->dataflags |= TRAN_STATE_RX_VOID;
298 dspi->dataflags |= TRAN_STATE_TX_VOID;
300 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
301 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
302 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
305 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
306 dspi->cur_chip->ctar_val);
308 dspi_transfer_write(dspi);
310 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
311 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
314 return t->len - dspi->len;
317 static void dspi_chipselect(struct spi_device *spi, int value)
319 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
322 regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
325 case BITBANG_CS_ACTIVE:
326 pushr |= SPI_PUSHR_CONT;
328 case BITBANG_CS_INACTIVE:
329 pushr &= ~SPI_PUSHR_CONT;
333 regmap_write(dspi->regmap, SPI_PUSHR, pushr);
336 static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
338 struct chip_data *chip;
339 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
340 unsigned char br = 0, pbr = 0, fmsz = 0;
342 /* Only alloc on first setup */
343 chip = spi_get_ctldata(spi);
345 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
351 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
352 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
353 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
354 fmsz = spi->bits_per_word - 1;
356 pr_err("Invalid wordsize\n");
360 chip->void_write_data = 0;
362 hz_to_spi_baud(&pbr, &br,
363 spi->max_speed_hz, clk_get_rate(dspi->clk));
365 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
366 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
367 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
368 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
372 spi_set_ctldata(spi, chip);
377 static int dspi_setup(struct spi_device *spi)
379 if (!spi->max_speed_hz)
382 return dspi_setup_transfer(spi, NULL);
385 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
387 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
389 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
391 dspi_transfer_read(dspi);
394 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
395 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
396 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
399 wake_up_interruptible(&dspi->waitq);
401 dspi_transfer_write(dspi);
409 static struct of_device_id fsl_dspi_dt_ids[] = {
410 { .compatible = "fsl,vf610-dspi", .data = NULL, },
413 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
415 #ifdef CONFIG_PM_SLEEP
416 static int dspi_suspend(struct device *dev)
418 struct spi_master *master = dev_get_drvdata(dev);
419 struct fsl_dspi *dspi = spi_master_get_devdata(master);
421 spi_master_suspend(master);
422 clk_disable_unprepare(dspi->clk);
427 static int dspi_resume(struct device *dev)
429 struct spi_master *master = dev_get_drvdata(dev);
430 struct fsl_dspi *dspi = spi_master_get_devdata(master);
432 clk_prepare_enable(dspi->clk);
433 spi_master_resume(master);
437 #endif /* CONFIG_PM_SLEEP */
439 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
441 static struct regmap_config dspi_regmap_config = {
445 .max_register = 0x88,
448 static int dspi_probe(struct platform_device *pdev)
450 struct device_node *np = pdev->dev.of_node;
451 struct spi_master *master;
452 struct fsl_dspi *dspi;
453 struct resource *res;
455 int ret = 0, cs_num, bus_num;
457 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
461 dspi = spi_master_get_devdata(master);
463 dspi->bitbang.master = master;
464 dspi->bitbang.chipselect = dspi_chipselect;
465 dspi->bitbang.setup_transfer = dspi_setup_transfer;
466 dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
467 dspi->bitbang.master->setup = dspi_setup;
468 dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
470 master->mode_bits = SPI_CPOL | SPI_CPHA;
471 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
474 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
476 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
479 master->num_chipselect = cs_num;
481 ret = of_property_read_u32(np, "bus-num", &bus_num);
483 dev_err(&pdev->dev, "can't get bus-num\n");
486 master->bus_num = bus_num;
488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 base = devm_ioremap_resource(&pdev->dev, res);
495 dspi_regmap_config.lock_arg = dspi;
496 dspi_regmap_config.val_format_endian =
497 of_property_read_bool(np, "big-endian")
498 ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
499 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
500 &dspi_regmap_config);
501 if (IS_ERR(dspi->regmap)) {
502 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
503 PTR_ERR(dspi->regmap));
504 return PTR_ERR(dspi->regmap);
507 dspi->irq = platform_get_irq(pdev, 0);
509 dev_err(&pdev->dev, "can't get platform irq\n");
514 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
517 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
521 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
522 if (IS_ERR(dspi->clk)) {
523 ret = PTR_ERR(dspi->clk);
524 dev_err(&pdev->dev, "unable to get clock\n");
527 clk_prepare_enable(dspi->clk);
529 init_waitqueue_head(&dspi->waitq);
530 platform_set_drvdata(pdev, master);
532 ret = spi_bitbang_start(&dspi->bitbang);
534 dev_err(&pdev->dev, "Problem registering DSPI master\n");
538 pr_info(KERN_INFO "Freescale DSPI master initialized\n");
542 clk_disable_unprepare(dspi->clk);
544 spi_master_put(master);
549 static int dspi_remove(struct platform_device *pdev)
551 struct spi_master *master = platform_get_drvdata(pdev);
552 struct fsl_dspi *dspi = spi_master_get_devdata(master);
554 /* Disconnect from the SPI framework */
555 spi_bitbang_stop(&dspi->bitbang);
556 clk_disable_unprepare(dspi->clk);
557 spi_master_put(dspi->bitbang.master);
562 static struct platform_driver fsl_dspi_driver = {
563 .driver.name = DRIVER_NAME,
564 .driver.of_match_table = fsl_dspi_dt_ids,
565 .driver.owner = THIS_MODULE,
566 .driver.pm = &dspi_pm,
568 .remove = dspi_remove,
570 module_platform_driver(fsl_dspi_driver);
572 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
573 MODULE_LICENSE("GPL");
574 MODULE_ALIAS("platform:" DRIVER_NAME);