2 * Freescale eSPI controller driver.
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/irq.h>
14 #include <linux/spi/spi.h>
15 #include <linux/platform_device.h>
16 #include <linux/fsl_devices.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/interrupt.h>
23 #include <linux/err.h>
24 #include <sysdev/fsl_soc.h>
26 #include "spi-fsl-lib.h"
28 /* eSPI Controller registers */
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
40 struct fsl_espi_transfer {
46 unsigned actual_length;
50 /* eSPI Controller mode register definitions */
51 #define SPMODE_ENABLE (1 << 31)
52 #define SPMODE_LOOP (1 << 30)
53 #define SPMODE_TXTHR(x) ((x) << 8)
54 #define SPMODE_RXTHR(x) ((x) << 0)
56 /* eSPI Controller CS mode register definitions */
57 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
58 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59 #define CSMODE_REV (1 << 29)
60 #define CSMODE_DIV16 (1 << 28)
61 #define CSMODE_PM(x) ((x) << 24)
62 #define CSMODE_POL_1 (1 << 20)
63 #define CSMODE_LEN(x) ((x) << 16)
64 #define CSMODE_BEF(x) ((x) << 12)
65 #define CSMODE_AFT(x) ((x) << 8)
66 #define CSMODE_CG(x) ((x) << 3)
68 /* Default mode/csmode for eSPI controller */
69 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
73 /* SPIE register values */
74 #define SPIE_NE 0x00000200 /* Not empty */
75 #define SPIE_NF 0x00000100 /* Not full */
77 /* SPIM register values */
78 #define SPIM_NE 0x00000200 /* Not empty */
79 #define SPIM_NF 0x00000100 /* Not full */
80 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
83 /* SPCOM register values */
84 #define SPCOM_CS(x) ((x) << 30)
85 #define SPCOM_TRANLEN(x) ((x) << 0)
86 #define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
88 static void fsl_espi_change_mode(struct spi_device *spi)
90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
91 struct spi_mpc8xxx_cs *cs = spi->controller_state;
92 struct fsl_espi_reg *reg_base = mspi->reg_base;
93 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
94 __be32 __iomem *espi_mode = ®_base->mode;
98 /* Turn off IRQs locally to minimize time that SPI is disabled. */
99 local_irq_save(flags);
101 /* Turn off SPI unit prior changing mode */
102 tmp = mpc8xxx_spi_read_reg(espi_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp);
107 local_irq_restore(flags);
110 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
115 const u32 *tx = mpc8xxx_spi->tx;
120 data = *tx++ << mpc8xxx_spi->tx_shift;
121 data_l = data & 0xffff;
122 data_h = (data >> 16) & 0xffff;
125 data = data_h | data_l;
127 mpc8xxx_spi->tx = tx;
131 static int fsl_espi_setup_transfer(struct spi_device *spi,
132 struct spi_transfer *t)
134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
135 int bits_per_word = 0;
138 struct spi_mpc8xxx_cs *cs = spi->controller_state;
141 bits_per_word = t->bits_per_word;
145 /* spi_transfer level calls that work per-word */
147 bits_per_word = spi->bits_per_word;
150 hz = spi->max_speed_hz;
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
156 if (bits_per_word <= 8) {
157 cs->rx_shift = 8 - bits_per_word;
159 cs->rx_shift = 16 - bits_per_word;
160 if (spi->mode & SPI_LSB_FIRST)
161 cs->get_tx = fsl_espi_tx_buf_lsb;
164 mpc8xxx_spi->rx_shift = cs->rx_shift;
165 mpc8xxx_spi->tx_shift = cs->tx_shift;
166 mpc8xxx_spi->get_rx = cs->get_rx;
167 mpc8xxx_spi->get_tx = cs->get_tx;
169 bits_per_word = bits_per_word - 1;
171 /* mask out bits we are going to set */
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
174 cs->hw_mode |= CSMODE_LEN(bits_per_word);
176 if ((mpc8xxx_spi->spibrg / hz) > 64) {
177 cs->hw_mode |= CSMODE_DIV16;
178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
181 "Will use %d Hz instead.\n", dev_name(&spi->dev),
182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
193 cs->hw_mode |= CSMODE_PM(pm);
195 fsl_espi_change_mode(spi);
199 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
203 struct fsl_espi_reg *reg_base = mspi->reg_base;
208 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
211 word = mspi->get_tx(mspi);
212 mpc8xxx_spi_write_reg(®_base->transmit, word);
217 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len;
224 mpc8xxx_spi->len = t->len;
225 len = roundup(len, 4) / 4;
227 mpc8xxx_spi->tx = t->tx_buf;
228 mpc8xxx_spi->rx = t->rx_buf;
230 reinit_completion(&mpc8xxx_spi->done);
232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
235 " beyond the SPCOM[TRANLEN] field\n", t->len);
238 mpc8xxx_spi_write_reg(®_base->command,
239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
245 wait_for_completion(&mpc8xxx_spi->done);
247 /* disable rx ints */
248 mpc8xxx_spi_write_reg(®_base->mask, 0);
250 return mpc8xxx_spi->count;
253 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
256 cmd[1] = (u8)(addr >> 16);
257 cmd[2] = (u8)(addr >> 8);
258 cmd[3] = (u8)(addr >> 0);
262 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
270 static void fsl_espi_do_trans(struct spi_message *m,
271 struct fsl_espi_transfer *tr)
273 struct spi_device *spi = m->spi;
274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
275 struct fsl_espi_transfer *espi_trans = tr;
276 struct spi_message message;
277 struct spi_transfer *t, *first, trans;
280 spi_message_init(&message);
281 memset(&trans, 0, sizeof(trans));
283 first = list_first_entry(&m->transfers, struct spi_transfer,
285 list_for_each_entry(t, &m->transfers, transfer_list) {
286 if ((first->bits_per_word != t->bits_per_word) ||
287 (first->speed_hz != t->speed_hz)) {
288 espi_trans->status = -EINVAL;
290 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
294 trans.speed_hz = t->speed_hz;
295 trans.bits_per_word = t->bits_per_word;
296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
299 trans.len = espi_trans->len;
300 trans.tx_buf = espi_trans->tx_buf;
301 trans.rx_buf = espi_trans->rx_buf;
302 spi_message_add_tail(&trans, &message);
304 list_for_each_entry(t, &message.transfers, transfer_list) {
305 if (t->bits_per_word || t->speed_hz) {
308 status = fsl_espi_setup_transfer(spi, t);
314 status = fsl_espi_bufs(spi, t);
322 udelay(t->delay_usecs);
325 espi_trans->status = status;
326 fsl_espi_setup_transfer(spi, NULL);
329 static void fsl_espi_cmd_trans(struct spi_message *m,
330 struct fsl_espi_transfer *trans, u8 *rx_buff)
332 struct spi_transfer *t;
335 struct fsl_espi_transfer *espi_trans = trans;
337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
339 espi_trans->status = -ENOMEM;
343 list_for_each_entry(t, &m->transfers, transfer_list) {
345 memcpy(local_buf + i, t->tx_buf, t->len);
350 espi_trans->tx_buf = local_buf;
351 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
352 fsl_espi_do_trans(m, espi_trans);
354 espi_trans->actual_length = espi_trans->len;
358 static void fsl_espi_rw_trans(struct spi_message *m,
359 struct fsl_espi_transfer *trans, u8 *rx_buff)
361 struct fsl_espi_transfer *espi_trans = trans;
362 unsigned int n_tx = espi_trans->n_tx;
363 unsigned int n_rx = espi_trans->n_rx;
364 struct spi_transfer *t;
366 u8 *rx_buf = rx_buff;
367 unsigned int trans_len;
371 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
373 espi_trans->status = -ENOMEM;
377 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
378 trans_len = n_rx - pos;
379 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
380 trans_len = SPCOM_TRANLEN_MAX - n_tx;
383 list_for_each_entry(t, &m->transfers, transfer_list) {
385 memcpy(local_buf + i, t->tx_buf, t->len);
391 addr = fsl_espi_cmd2addr(local_buf);
393 fsl_espi_addr2cmd(addr, local_buf);
396 espi_trans->n_tx = n_tx;
397 espi_trans->n_rx = trans_len;
398 espi_trans->len = trans_len + n_tx;
399 espi_trans->tx_buf = local_buf;
400 espi_trans->rx_buf = local_buf + n_tx;
401 fsl_espi_do_trans(m, espi_trans);
403 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
406 espi_trans->actual_length += espi_trans->len - n_tx;
408 espi_trans->actual_length += espi_trans->len;
414 static void fsl_espi_do_one_msg(struct spi_message *m)
416 struct spi_transfer *t;
418 unsigned int n_tx = 0;
419 unsigned int n_rx = 0;
420 struct fsl_espi_transfer espi_trans;
422 list_for_each_entry(t, &m->transfers, transfer_list) {
431 espi_trans.n_tx = n_tx;
432 espi_trans.n_rx = n_rx;
433 espi_trans.len = n_tx + n_rx;
434 espi_trans.actual_length = 0;
435 espi_trans.status = 0;
438 fsl_espi_cmd_trans(m, &espi_trans, NULL);
440 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
442 m->actual_length = espi_trans.actual_length;
443 m->status = espi_trans.status;
445 m->complete(m->context);
448 static int fsl_espi_setup(struct spi_device *spi)
450 struct mpc8xxx_spi *mpc8xxx_spi;
451 struct fsl_espi_reg *reg_base;
455 struct spi_mpc8xxx_cs *cs = spi->controller_state;
457 if (!spi->max_speed_hz)
461 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
464 spi->controller_state = cs;
467 mpc8xxx_spi = spi_master_get_devdata(spi->master);
468 reg_base = mpc8xxx_spi->reg_base;
470 hw_mode = cs->hw_mode; /* Save original settings */
471 cs->hw_mode = mpc8xxx_spi_read_reg(
472 ®_base->csmode[spi->chip_select]);
473 /* mask out bits we are going to set */
474 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
477 if (spi->mode & SPI_CPHA)
478 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
479 if (spi->mode & SPI_CPOL)
480 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
481 if (!(spi->mode & SPI_LSB_FIRST))
482 cs->hw_mode |= CSMODE_REV;
484 /* Handle the loop mode */
485 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
486 loop_mode &= ~SPMODE_LOOP;
487 if (spi->mode & SPI_LOOP)
488 loop_mode |= SPMODE_LOOP;
489 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
491 retval = fsl_espi_setup_transfer(spi, NULL);
493 cs->hw_mode = hw_mode; /* Restore settings */
499 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
501 struct fsl_espi_reg *reg_base = mspi->reg_base;
503 /* We need handle RX first */
504 if (events & SPIE_NE) {
508 /* Spin until RX is done */
509 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
511 events = mpc8xxx_spi_read_reg(®_base->event);
514 if (mspi->len >= 4) {
515 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
520 rx_data_8 = in_8((u8 *)®_base->receive);
521 rx_data |= (rx_data_8 << (tmp * 8));
524 rx_data <<= (4 - mspi->len) * 8;
530 mspi->get_rx(rx_data, mspi);
533 if (!(events & SPIE_NF)) {
536 /* spin until TX is done */
537 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
538 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
540 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
545 /* Clear the events */
546 mpc8xxx_spi_write_reg(®_base->event, events);
550 u32 word = mspi->get_tx(mspi);
552 mpc8xxx_spi_write_reg(®_base->transmit, word);
554 complete(&mspi->done);
558 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
560 struct mpc8xxx_spi *mspi = context_data;
561 struct fsl_espi_reg *reg_base = mspi->reg_base;
562 irqreturn_t ret = IRQ_NONE;
565 /* Get interrupt events(tx/rx) */
566 events = mpc8xxx_spi_read_reg(®_base->event);
570 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
572 fsl_espi_cpu_irq(mspi, events);
577 static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
579 iounmap(mspi->reg_base);
582 static struct spi_master * fsl_espi_probe(struct device *dev,
583 struct resource *mem, unsigned int irq)
585 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
586 struct spi_master *master;
587 struct mpc8xxx_spi *mpc8xxx_spi;
588 struct fsl_espi_reg *reg_base;
592 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
598 dev_set_drvdata(dev, master);
600 ret = mpc8xxx_spi_probe(dev, mem, irq);
604 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
605 master->setup = fsl_espi_setup;
607 mpc8xxx_spi = spi_master_get_devdata(master);
608 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
609 mpc8xxx_spi->spi_remove = fsl_espi_remove;
611 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
612 if (!mpc8xxx_spi->reg_base) {
617 reg_base = mpc8xxx_spi->reg_base;
619 /* Register for SPI Interrupt */
620 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
621 0, "fsl_espi", mpc8xxx_spi);
625 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
626 mpc8xxx_spi->rx_shift = 16;
627 mpc8xxx_spi->tx_shift = 24;
630 /* SPI controller initializations */
631 mpc8xxx_spi_write_reg(®_base->mode, 0);
632 mpc8xxx_spi_write_reg(®_base->mask, 0);
633 mpc8xxx_spi_write_reg(®_base->command, 0);
634 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
636 /* Init eSPI CS mode register */
637 for (i = 0; i < pdata->max_chipselect; i++)
638 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
640 /* Enable SPI interface */
641 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
643 mpc8xxx_spi_write_reg(®_base->mode, regval);
645 ret = spi_register_master(master);
649 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
654 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
656 iounmap(mpc8xxx_spi->reg_base);
658 spi_master_put(master);
663 static int of_fsl_espi_get_chipselects(struct device *dev)
665 struct device_node *np = dev->of_node;
666 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
670 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
671 if (!prop || len < sizeof(*prop)) {
672 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
676 pdata->max_chipselect = *prop;
677 pdata->cs_control = NULL;
682 static int of_fsl_espi_probe(struct platform_device *ofdev)
684 struct device *dev = &ofdev->dev;
685 struct device_node *np = ofdev->dev.of_node;
686 struct spi_master *master;
691 ret = of_mpc8xxx_spi_probe(ofdev);
695 ret = of_fsl_espi_get_chipselects(dev);
699 ret = of_address_to_resource(np, 0, &mem);
703 irq = irq_of_parse_and_map(np, 0);
709 master = fsl_espi_probe(dev, &mem, irq);
710 if (IS_ERR(master)) {
711 ret = PTR_ERR(master);
721 static int of_fsl_espi_remove(struct platform_device *dev)
723 return mpc8xxx_spi_remove(&dev->dev);
726 #ifdef CONFIG_PM_SLEEP
727 static int of_fsl_espi_suspend(struct device *dev)
729 struct spi_master *master = dev_get_drvdata(dev);
730 struct mpc8xxx_spi *mpc8xxx_spi;
731 struct fsl_espi_reg *reg_base;
735 mpc8xxx_spi = spi_master_get_devdata(master);
736 reg_base = mpc8xxx_spi->reg_base;
738 ret = spi_master_suspend(master);
740 dev_warn(dev, "cannot suspend master\n");
744 regval = mpc8xxx_spi_read_reg(®_base->mode);
745 regval &= ~SPMODE_ENABLE;
746 mpc8xxx_spi_write_reg(®_base->mode, regval);
751 static int of_fsl_espi_resume(struct device *dev)
753 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
754 struct spi_master *master = dev_get_drvdata(dev);
755 struct mpc8xxx_spi *mpc8xxx_spi;
756 struct fsl_espi_reg *reg_base;
760 mpc8xxx_spi = spi_master_get_devdata(master);
761 reg_base = mpc8xxx_spi->reg_base;
763 /* SPI controller initializations */
764 mpc8xxx_spi_write_reg(®_base->mode, 0);
765 mpc8xxx_spi_write_reg(®_base->mask, 0);
766 mpc8xxx_spi_write_reg(®_base->command, 0);
767 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
769 /* Init eSPI CS mode register */
770 for (i = 0; i < pdata->max_chipselect; i++)
771 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
773 /* Enable SPI interface */
774 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
776 mpc8xxx_spi_write_reg(®_base->mode, regval);
778 return spi_master_resume(master);
780 #endif /* CONFIG_PM_SLEEP */
782 static const struct dev_pm_ops espi_pm = {
783 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
786 static const struct of_device_id of_fsl_espi_match[] = {
787 { .compatible = "fsl,mpc8536-espi" },
790 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
792 static struct platform_driver fsl_espi_driver = {
795 .owner = THIS_MODULE,
796 .of_match_table = of_fsl_espi_match,
799 .probe = of_fsl_espi_probe,
800 .remove = of_fsl_espi_remove,
802 module_platform_driver(fsl_espi_driver);
804 MODULE_AUTHOR("Mingkai Hu");
805 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
806 MODULE_LICENSE("GPL");