2 * Freescale eSPI controller driver.
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/irq.h>
14 #include <linux/spi/spi.h>
15 #include <linux/platform_device.h>
16 #include <linux/fsl_devices.h>
19 #include <linux/of_platform.h>
20 #include <linux/interrupt.h>
21 #include <linux/err.h>
22 #include <sysdev/fsl_soc.h>
24 #include "spi-fsl-lib.h"
26 /* eSPI Controller registers */
28 __be32 mode; /* 0x000 - eSPI mode register */
29 __be32 event; /* 0x004 - eSPI event register */
30 __be32 mask; /* 0x008 - eSPI mask register */
31 __be32 command; /* 0x00c - eSPI command register */
32 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
33 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
34 u8 res[8]; /* 0x018 - 0x01c reserved */
35 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
38 struct fsl_espi_transfer {
44 unsigned actual_length;
48 /* eSPI Controller mode register definitions */
49 #define SPMODE_ENABLE (1 << 31)
50 #define SPMODE_LOOP (1 << 30)
51 #define SPMODE_TXTHR(x) ((x) << 8)
52 #define SPMODE_RXTHR(x) ((x) << 0)
54 /* eSPI Controller CS mode register definitions */
55 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
56 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
57 #define CSMODE_REV (1 << 29)
58 #define CSMODE_DIV16 (1 << 28)
59 #define CSMODE_PM(x) ((x) << 24)
60 #define CSMODE_POL_1 (1 << 20)
61 #define CSMODE_LEN(x) ((x) << 16)
62 #define CSMODE_BEF(x) ((x) << 12)
63 #define CSMODE_AFT(x) ((x) << 8)
64 #define CSMODE_CG(x) ((x) << 3)
66 /* Default mode/csmode for eSPI controller */
67 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
68 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
69 | CSMODE_AFT(0) | CSMODE_CG(1))
71 /* SPIE register values */
72 #define SPIE_NE 0x00000200 /* Not empty */
73 #define SPIE_NF 0x00000100 /* Not full */
75 /* SPIM register values */
76 #define SPIM_NE 0x00000200 /* Not empty */
77 #define SPIM_NF 0x00000100 /* Not full */
78 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
79 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
81 /* SPCOM register values */
82 #define SPCOM_CS(x) ((x) << 30)
83 #define SPCOM_TRANLEN(x) ((x) << 0)
84 #define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
86 static void fsl_espi_change_mode(struct spi_device *spi)
88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
89 struct spi_mpc8xxx_cs *cs = spi->controller_state;
90 struct fsl_espi_reg *reg_base = mspi->reg_base;
91 __be32 __iomem *mode = ®_base->csmode[spi->chip_select];
92 __be32 __iomem *espi_mode = ®_base->mode;
96 /* Turn off IRQs locally to minimize time that SPI is disabled. */
97 local_irq_save(flags);
99 /* Turn off SPI unit prior changing mode */
100 tmp = mpc8xxx_spi_read_reg(espi_mode);
101 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
102 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp);
105 local_irq_restore(flags);
108 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
113 const u32 *tx = mpc8xxx_spi->tx;
118 data = *tx++ << mpc8xxx_spi->tx_shift;
119 data_l = data & 0xffff;
120 data_h = (data >> 16) & 0xffff;
123 data = data_h | data_l;
125 mpc8xxx_spi->tx = tx;
129 static int fsl_espi_setup_transfer(struct spi_device *spi,
130 struct spi_transfer *t)
132 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
133 int bits_per_word = 0;
136 struct spi_mpc8xxx_cs *cs = spi->controller_state;
139 bits_per_word = t->bits_per_word;
143 /* spi_transfer level calls that work per-word */
145 bits_per_word = spi->bits_per_word;
148 hz = spi->max_speed_hz;
152 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
153 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
154 if (bits_per_word <= 8) {
155 cs->rx_shift = 8 - bits_per_word;
157 cs->rx_shift = 16 - bits_per_word;
158 if (spi->mode & SPI_LSB_FIRST)
159 cs->get_tx = fsl_espi_tx_buf_lsb;
162 mpc8xxx_spi->rx_shift = cs->rx_shift;
163 mpc8xxx_spi->tx_shift = cs->tx_shift;
164 mpc8xxx_spi->get_rx = cs->get_rx;
165 mpc8xxx_spi->get_tx = cs->get_tx;
167 bits_per_word = bits_per_word - 1;
169 /* mask out bits we are going to set */
170 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
172 cs->hw_mode |= CSMODE_LEN(bits_per_word);
174 if ((mpc8xxx_spi->spibrg / hz) > 64) {
175 cs->hw_mode |= CSMODE_DIV16;
176 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
178 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
179 "Will use %d Hz instead.\n", dev_name(&spi->dev),
180 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
184 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
191 cs->hw_mode |= CSMODE_PM(pm);
193 fsl_espi_change_mode(spi);
197 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
201 struct fsl_espi_reg *reg_base = mspi->reg_base;
206 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
209 word = mspi->get_tx(mspi);
210 mpc8xxx_spi_write_reg(®_base->transmit, word);
215 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
217 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
218 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
219 unsigned int len = t->len;
223 bits_per_word = spi->bits_per_word;
224 if (t->bits_per_word)
225 bits_per_word = t->bits_per_word;
227 mpc8xxx_spi->len = t->len;
228 len = roundup(len, 4) / 4;
230 mpc8xxx_spi->tx = t->tx_buf;
231 mpc8xxx_spi->rx = t->rx_buf;
233 INIT_COMPLETION(mpc8xxx_spi->done);
235 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
236 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
237 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
238 " beyond the SPCOM[TRANLEN] field\n", t->len);
241 mpc8xxx_spi_write_reg(®_base->command,
242 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
244 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
248 wait_for_completion(&mpc8xxx_spi->done);
250 /* disable rx ints */
251 mpc8xxx_spi_write_reg(®_base->mask, 0);
253 return mpc8xxx_spi->count;
256 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
259 cmd[1] = (u8)(addr >> 16);
260 cmd[2] = (u8)(addr >> 8);
261 cmd[3] = (u8)(addr >> 0);
265 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
268 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
273 static void fsl_espi_do_trans(struct spi_message *m,
274 struct fsl_espi_transfer *tr)
276 struct spi_device *spi = m->spi;
277 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
278 struct fsl_espi_transfer *espi_trans = tr;
279 struct spi_message message;
280 struct spi_transfer *t, *first, trans;
283 spi_message_init(&message);
284 memset(&trans, 0, sizeof(trans));
286 first = list_first_entry(&m->transfers, struct spi_transfer,
288 list_for_each_entry(t, &m->transfers, transfer_list) {
289 if ((first->bits_per_word != t->bits_per_word) ||
290 (first->speed_hz != t->speed_hz)) {
291 espi_trans->status = -EINVAL;
293 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
297 trans.speed_hz = t->speed_hz;
298 trans.bits_per_word = t->bits_per_word;
299 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
302 trans.len = espi_trans->len;
303 trans.tx_buf = espi_trans->tx_buf;
304 trans.rx_buf = espi_trans->rx_buf;
305 spi_message_add_tail(&trans, &message);
307 list_for_each_entry(t, &message.transfers, transfer_list) {
308 if (t->bits_per_word || t->speed_hz) {
311 status = fsl_espi_setup_transfer(spi, t);
317 status = fsl_espi_bufs(spi, t);
325 udelay(t->delay_usecs);
328 espi_trans->status = status;
329 fsl_espi_setup_transfer(spi, NULL);
332 static void fsl_espi_cmd_trans(struct spi_message *m,
333 struct fsl_espi_transfer *trans, u8 *rx_buff)
335 struct spi_transfer *t;
338 struct fsl_espi_transfer *espi_trans = trans;
340 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
342 espi_trans->status = -ENOMEM;
346 list_for_each_entry(t, &m->transfers, transfer_list) {
348 memcpy(local_buf + i, t->tx_buf, t->len);
353 espi_trans->tx_buf = local_buf;
354 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
355 fsl_espi_do_trans(m, espi_trans);
357 espi_trans->actual_length = espi_trans->len;
361 static void fsl_espi_rw_trans(struct spi_message *m,
362 struct fsl_espi_transfer *trans, u8 *rx_buff)
364 struct fsl_espi_transfer *espi_trans = trans;
365 unsigned int n_tx = espi_trans->n_tx;
366 unsigned int n_rx = espi_trans->n_rx;
367 struct spi_transfer *t;
369 u8 *rx_buf = rx_buff;
370 unsigned int trans_len;
374 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
376 espi_trans->status = -ENOMEM;
380 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
381 trans_len = n_rx - pos;
382 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
383 trans_len = SPCOM_TRANLEN_MAX - n_tx;
386 list_for_each_entry(t, &m->transfers, transfer_list) {
388 memcpy(local_buf + i, t->tx_buf, t->len);
394 addr = fsl_espi_cmd2addr(local_buf);
396 fsl_espi_addr2cmd(addr, local_buf);
399 espi_trans->n_tx = n_tx;
400 espi_trans->n_rx = trans_len;
401 espi_trans->len = trans_len + n_tx;
402 espi_trans->tx_buf = local_buf;
403 espi_trans->rx_buf = local_buf + n_tx;
404 fsl_espi_do_trans(m, espi_trans);
406 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
409 espi_trans->actual_length += espi_trans->len - n_tx;
411 espi_trans->actual_length += espi_trans->len;
417 static void fsl_espi_do_one_msg(struct spi_message *m)
419 struct spi_transfer *t;
421 unsigned int n_tx = 0;
422 unsigned int n_rx = 0;
423 struct fsl_espi_transfer espi_trans;
425 list_for_each_entry(t, &m->transfers, transfer_list) {
434 espi_trans.n_tx = n_tx;
435 espi_trans.n_rx = n_rx;
436 espi_trans.len = n_tx + n_rx;
437 espi_trans.actual_length = 0;
438 espi_trans.status = 0;
441 fsl_espi_cmd_trans(m, &espi_trans, NULL);
443 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
445 m->actual_length = espi_trans.actual_length;
446 m->status = espi_trans.status;
447 m->complete(m->context);
450 static int fsl_espi_setup(struct spi_device *spi)
452 struct mpc8xxx_spi *mpc8xxx_spi;
453 struct fsl_espi_reg *reg_base;
457 struct spi_mpc8xxx_cs *cs = spi->controller_state;
459 if (!spi->max_speed_hz)
463 cs = kzalloc(sizeof *cs, GFP_KERNEL);
466 spi->controller_state = cs;
469 mpc8xxx_spi = spi_master_get_devdata(spi->master);
470 reg_base = mpc8xxx_spi->reg_base;
472 hw_mode = cs->hw_mode; /* Save original settings */
473 cs->hw_mode = mpc8xxx_spi_read_reg(
474 ®_base->csmode[spi->chip_select]);
475 /* mask out bits we are going to set */
476 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
479 if (spi->mode & SPI_CPHA)
480 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
481 if (spi->mode & SPI_CPOL)
482 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
483 if (!(spi->mode & SPI_LSB_FIRST))
484 cs->hw_mode |= CSMODE_REV;
486 /* Handle the loop mode */
487 loop_mode = mpc8xxx_spi_read_reg(®_base->mode);
488 loop_mode &= ~SPMODE_LOOP;
489 if (spi->mode & SPI_LOOP)
490 loop_mode |= SPMODE_LOOP;
491 mpc8xxx_spi_write_reg(®_base->mode, loop_mode);
493 retval = fsl_espi_setup_transfer(spi, NULL);
495 cs->hw_mode = hw_mode; /* Restore settings */
501 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
503 struct fsl_espi_reg *reg_base = mspi->reg_base;
505 /* We need handle RX first */
506 if (events & SPIE_NE) {
510 /* Spin until RX is done */
511 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
513 events = mpc8xxx_spi_read_reg(®_base->event);
516 if (mspi->len >= 4) {
517 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
522 rx_data_8 = in_8((u8 *)®_base->receive);
523 rx_data |= (rx_data_8 << (tmp * 8));
526 rx_data <<= (4 - mspi->len) * 8;
532 mspi->get_rx(rx_data, mspi);
535 if (!(events & SPIE_NF)) {
538 /* spin until TX is done */
539 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
540 ®_base->event)) & SPIE_NF) == 0, 1000, 0);
542 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
547 /* Clear the events */
548 mpc8xxx_spi_write_reg(®_base->event, events);
552 u32 word = mspi->get_tx(mspi);
554 mpc8xxx_spi_write_reg(®_base->transmit, word);
556 complete(&mspi->done);
560 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
562 struct mpc8xxx_spi *mspi = context_data;
563 struct fsl_espi_reg *reg_base = mspi->reg_base;
564 irqreturn_t ret = IRQ_NONE;
567 /* Get interrupt events(tx/rx) */
568 events = mpc8xxx_spi_read_reg(®_base->event);
572 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
574 fsl_espi_cpu_irq(mspi, events);
579 static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
581 iounmap(mspi->reg_base);
584 static struct spi_master * fsl_espi_probe(struct device *dev,
585 struct resource *mem, unsigned int irq)
587 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
588 struct spi_master *master;
589 struct mpc8xxx_spi *mpc8xxx_spi;
590 struct fsl_espi_reg *reg_base;
594 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
600 dev_set_drvdata(dev, master);
602 ret = mpc8xxx_spi_probe(dev, mem, irq);
606 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
607 master->setup = fsl_espi_setup;
609 mpc8xxx_spi = spi_master_get_devdata(master);
610 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
611 mpc8xxx_spi->spi_remove = fsl_espi_remove;
613 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
614 if (!mpc8xxx_spi->reg_base) {
619 reg_base = mpc8xxx_spi->reg_base;
621 /* Register for SPI Interrupt */
622 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
623 0, "fsl_espi", mpc8xxx_spi);
627 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
628 mpc8xxx_spi->rx_shift = 16;
629 mpc8xxx_spi->tx_shift = 24;
632 /* SPI controller initializations */
633 mpc8xxx_spi_write_reg(®_base->mode, 0);
634 mpc8xxx_spi_write_reg(®_base->mask, 0);
635 mpc8xxx_spi_write_reg(®_base->command, 0);
636 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
638 /* Init eSPI CS mode register */
639 for (i = 0; i < pdata->max_chipselect; i++)
640 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
642 /* Enable SPI interface */
643 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
645 mpc8xxx_spi_write_reg(®_base->mode, regval);
647 ret = spi_register_master(master);
651 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
656 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
658 iounmap(mpc8xxx_spi->reg_base);
660 spi_master_put(master);
665 static int of_fsl_espi_get_chipselects(struct device *dev)
667 struct device_node *np = dev->of_node;
668 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
672 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
673 if (!prop || len < sizeof(*prop)) {
674 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
678 pdata->max_chipselect = *prop;
679 pdata->cs_control = NULL;
684 static int of_fsl_espi_probe(struct platform_device *ofdev)
686 struct device *dev = &ofdev->dev;
687 struct device_node *np = ofdev->dev.of_node;
688 struct spi_master *master;
693 ret = of_mpc8xxx_spi_probe(ofdev);
697 ret = of_fsl_espi_get_chipselects(dev);
701 ret = of_address_to_resource(np, 0, &mem);
705 ret = of_irq_to_resource(np, 0, &irq);
711 master = fsl_espi_probe(dev, &mem, irq.start);
712 if (IS_ERR(master)) {
713 ret = PTR_ERR(master);
723 static int of_fsl_espi_remove(struct platform_device *dev)
725 return mpc8xxx_spi_remove(&dev->dev);
728 static const struct of_device_id of_fsl_espi_match[] = {
729 { .compatible = "fsl,mpc8536-espi" },
732 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
734 static struct platform_driver fsl_espi_driver = {
737 .owner = THIS_MODULE,
738 .of_match_table = of_fsl_espi_match,
740 .probe = of_fsl_espi_probe,
741 .remove = of_fsl_espi_remove,
743 module_platform_driver(fsl_espi_driver);
745 MODULE_AUTHOR("Mingkai Hu");
746 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
747 MODULE_LICENSE("GPL");