drivers/spi/spi-fsl-spi.c

   1 /*
   2  * Freescale SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * GRLIB support:
  14  * Copyright (c) 2012 Aeroflex Gaisler AB.
  15  * Author: Andreas Larsson <andreas@gaisler.com>
  16  *
  17  * This program is free software; you can redistribute  it and/or modify it
  18  * under  the terms of  the GNU General  Public License as published by the
  19  * Free Software Foundation;  either version 2 of the  License, or (at your
  20  * option) any later version.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/spi_bitbang.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/fsl_devices.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/mm.h>
  34 #include <linux/mutex.h>
  35 #include <linux/of.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/of_address.h>
  38 #include <linux/of_irq.h>
  39 #include <linux/gpio.h>
  40 #include <linux/of_gpio.h>
  41
  42 #include "spi-fsl-lib.h"
  43 #include "spi-fsl-cpm.h"
  44 #include "spi-fsl-spi.h"
  45
  46 #define TYPE_FSL        0
  47 #define TYPE_GRLIB      1
  48
  49 struct fsl_spi_match_data {
  50         int type;
  51 };
  52
  53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
  54         .type = TYPE_FSL,
  55 };
  56
  57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
  58         .type = TYPE_GRLIB,
  59 };
  60
  61 static struct of_device_id of_fsl_spi_match[] = {
  62         {
  63                 .compatible = "fsl,spi",
  64                 .data = &of_fsl_spi_fsl_config,
  65         },
  66         {
  67                 .compatible = "aeroflexgaisler,spictrl",
  68                 .data = &of_fsl_spi_grlib_config,
  69         },
  70         {}
  71 };
  72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
  73
  74 static int fsl_spi_get_type(struct device *dev)
  75 {
  76         const struct of_device_id *match;
  77
  78         if (dev->of_node) {
  79                 match = of_match_node(of_fsl_spi_match, dev->of_node);
  80                 if (match && match->data)
  81                         return ((struct fsl_spi_match_data *)match->data)->type;
  82         }
  83         return TYPE_FSL;
  84 }
  85
  86 static void fsl_spi_change_mode(struct spi_device *spi)
  87 {
  88         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  89         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  90         struct fsl_spi_reg *reg_base = mspi->reg_base;
  91         __be32 __iomem *mode = &reg_base->mode;
  92         unsigned long flags;
  93
  94         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  95                 return;
  96
  97         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  98         local_irq_save(flags);
  99
 100         /* Turn off SPI unit prior changing mode */
 101         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 102
 103         /* When in CPM mode, we need to reinit tx and rx. */
 104         if (mspi->flags & SPI_CPM_MODE) {
 105                 fsl_spi_cpm_reinit_txrx(mspi);
 106         }
 107         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 108         local_irq_restore(flags);
 109 }
 110
 111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
 112 {
 113         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 114         struct fsl_spi_platform_data *pdata;
 115         bool pol = spi->mode & SPI_CS_HIGH;
 116         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 117
 118         pdata = spi->dev.parent->parent->platform_data;
 119
 120         if (value == BITBANG_CS_INACTIVE) {
 121                 if (pdata->cs_control)
 122                         pdata->cs_control(spi, !pol);
 123         }
 124
 125         if (value == BITBANG_CS_ACTIVE) {
 126                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 127                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 128                 mpc8xxx_spi->get_rx = cs->get_rx;
 129                 mpc8xxx_spi->get_tx = cs->get_tx;
 130
 131                 fsl_spi_change_mode(spi);
 132
 133                 if (pdata->cs_control)
 134                         pdata->cs_control(spi, pol);
 135         }
 136 }
 137
 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
 139                                       int bits_per_word, int msb_first)
 140 {
 141         *rx_shift = 0;
 142         *tx_shift = 0;
 143         if (msb_first) {
 144                 if (bits_per_word <= 8) {
 145                         *rx_shift = 16;
 146                         *tx_shift = 24;
 147                 } else if (bits_per_word <= 16) {
 148                         *rx_shift = 16;
 149                         *tx_shift = 16;
 150                 }
 151         } else {
 152                 if (bits_per_word <= 8)
 153                         *rx_shift = 8;
 154         }
 155 }
 156
 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
 158                                      int bits_per_word, int msb_first)
 159 {
 160         *rx_shift = 0;
 161         *tx_shift = 0;
 162         if (bits_per_word <= 16) {
 163                 if (msb_first) {
 164                         *rx_shift = 16; /* LSB in bit 16 */
 165                         *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
 166                 } else {
 167                         *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
 168                 }
 169         }
 170 }
 171
 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 173                                 struct spi_device *spi,
 174                                 struct mpc8xxx_spi *mpc8xxx_spi,
 175                                 int bits_per_word)
 176 {
 177         cs->rx_shift = 0;
 178         cs->tx_shift = 0;
 179         if (bits_per_word <= 8) {
 180                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 181                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 182         } else if (bits_per_word <= 16) {
 183                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 184                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 185         } else if (bits_per_word <= 32) {
 186                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 187                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 188         } else
 189                 return -EINVAL;
 190
 191         if (mpc8xxx_spi->set_shifts)
 192                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 193                                         bits_per_word,
 194                                         !(spi->mode & SPI_LSB_FIRST));
 195
 196         mpc8xxx_spi->rx_shift = cs->rx_shift;
 197         mpc8xxx_spi->tx_shift = cs->tx_shift;
 198         mpc8xxx_spi->get_rx = cs->get_rx;
 199         mpc8xxx_spi->get_tx = cs->get_tx;
 200
 201         return bits_per_word;
 202 }
 203
 204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 205                                 struct spi_device *spi,
 206                                 int bits_per_word)
 207 {
 208         /* QE uses Little Endian for words > 8
 209          * so transform all words > 8 into 8 bits
 210          * Unfortnatly that doesn't work for LSB so
 211          * reject these for now */
 212         /* Note: 32 bits word, LSB works iff
 213          * tfcr/rfcr is set to CPMFCR_GBL */
 214         if (spi->mode & SPI_LSB_FIRST &&
 215             bits_per_word > 8)
 216                 return -EINVAL;
 217         if (bits_per_word > 8)
 218                 return 8; /* pretend its 8 bits */
 219         return bits_per_word;
 220 }
 221
 222 static int fsl_spi_setup_transfer(struct spi_device *spi,
 223                                         struct spi_transfer *t)
 224 {
 225         struct mpc8xxx_spi *mpc8xxx_spi;
 226         int bits_per_word = 0;
 227         u8 pm;
 228         u32 hz = 0;
 229         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 230
 231         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 232
 233         if (t) {
 234                 bits_per_word = t->bits_per_word;
 235                 hz = t->speed_hz;
 236         }
 237
 238         /* spi_transfer level calls that work per-word */
 239         if (!bits_per_word)
 240                 bits_per_word = spi->bits_per_word;
 241
 242         /* Make sure its a bit width we support [4..16, 32] */
 243         if ((bits_per_word < 4)
 244             || ((bits_per_word > 16) && (bits_per_word != 32))
 245             || (bits_per_word > mpc8xxx_spi->max_bits_per_word))
 246                 return -EINVAL;
 247
 248         if (!hz)
 249                 hz = spi->max_speed_hz;
 250
 251         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 252                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 253                                                            mpc8xxx_spi,
 254                                                            bits_per_word);
 255         else if (mpc8xxx_spi->flags & SPI_QE)
 256                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 257                                                           bits_per_word);
 258
 259         if (bits_per_word < 0)
 260                 return bits_per_word;
 261
 262         if (bits_per_word == 32)
 263                 bits_per_word = 0;
 264         else
 265                 bits_per_word = bits_per_word - 1;
 266
 267         /* mask out bits we are going to set */
 268         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 269                                   | SPMODE_PM(0xF));
 270
 271         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 272
 273         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 274                 cs->hw_mode |= SPMODE_DIV16;
 275                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 276
 277                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 278                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 279                           hz, mpc8xxx_spi->spibrg / 1024);
 280                 if (pm > 16)
 281                         pm = 16;
 282         } else {
 283                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 284         }
 285         if (pm)
 286                 pm--;
 287
 288         cs->hw_mode |= SPMODE_PM(pm);
 289
 290         fsl_spi_change_mode(spi);
 291         return 0;
 292 }
 293
 294 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 295                                 struct spi_transfer *t, unsigned int len)
 296 {
 297         u32 word;
 298         struct fsl_spi_reg *reg_base = mspi->reg_base;
 299
 300         mspi->count = len;
 301
 302         /* enable rx ints */
 303         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 304
 305         /* transmit word */
 306         word = mspi->get_tx(mspi);
 307         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 308
 309         return 0;
 310 }
 311
 312 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 313                             bool is_dma_mapped)
 314 {
 315         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 316         struct fsl_spi_reg *reg_base;
 317         unsigned int len = t->len;
 318         u8 bits_per_word;
 319         int ret;
 320
 321         reg_base = mpc8xxx_spi->reg_base;
 322         bits_per_word = spi->bits_per_word;
 323         if (t->bits_per_word)
 324                 bits_per_word = t->bits_per_word;
 325
 326         if (bits_per_word > 8) {
 327                 /* invalid length? */
 328                 if (len & 1)
 329                         return -EINVAL;
 330                 len /= 2;
 331         }
 332         if (bits_per_word > 16) {
 333                 /* invalid length? */
 334                 if (len & 1)
 335                         return -EINVAL;
 336                 len /= 2;
 337         }
 338
 339         mpc8xxx_spi->tx = t->tx_buf;
 340         mpc8xxx_spi->rx = t->rx_buf;
 341
 342         reinit_completion(&mpc8xxx_spi->done);
 343
 344         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 345                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 346         else
 347                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 348         if (ret)
 349                 return ret;
 350
 351         wait_for_completion(&mpc8xxx_spi->done);
 352
 353         /* disable rx ints */
 354         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 355
 356         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 357                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 358
 359         return mpc8xxx_spi->count;
 360 }
 361
 362 static void fsl_spi_do_one_msg(struct spi_message *m)
 363 {
 364         struct spi_device *spi = m->spi;
 365         struct spi_transfer *t;
 366         unsigned int cs_change;
 367         const int nsecs = 50;
 368         int status;
 369
 370         cs_change = 1;
 371         status = 0;
 372         list_for_each_entry(t, &m->transfers, transfer_list) {
 373                 if (t->bits_per_word || t->speed_hz) {
 374                         /* Don't allow changes if CS is active */
 375                         status = -EINVAL;
 376
 377                         if (cs_change)
 378                                 status = fsl_spi_setup_transfer(spi, t);
 379                         if (status < 0)
 380                                 break;
 381                 }
 382
 383                 if (cs_change) {
 384                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 385                         ndelay(nsecs);
 386                 }
 387                 cs_change = t->cs_change;
 388                 if (t->len)
 389                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 390                 if (status) {
 391                         status = -EMSGSIZE;
 392                         break;
 393                 }
 394                 m->actual_length += t->len;
 395
 396                 if (t->delay_usecs)
 397                         udelay(t->delay_usecs);
 398
 399                 if (cs_change) {
 400                         ndelay(nsecs);
 401                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 402                         ndelay(nsecs);
 403                 }
 404         }
 405
 406         m->status = status;
 407         if (m->complete)
 408                 m->complete(m->context);
 409
 410         if (status || !cs_change) {
 411                 ndelay(nsecs);
 412                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 413         }
 414
 415         fsl_spi_setup_transfer(spi, NULL);
 416 }
 417
 418 static int fsl_spi_setup(struct spi_device *spi)
 419 {
 420         struct mpc8xxx_spi *mpc8xxx_spi;
 421         struct fsl_spi_reg *reg_base;
 422         int retval;
 423         u32 hw_mode;
 424         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 425
 426         if (!spi->max_speed_hz)
 427                 return -EINVAL;
 428
 429         if (!cs) {
 430                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 431                 if (!cs)
 432                         return -ENOMEM;
 433                 spi->controller_state = cs;
 434         }
 435         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 436
 437         reg_base = mpc8xxx_spi->reg_base;
 438
 439         hw_mode = cs->hw_mode; /* Save original settings */
 440         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 441         /* mask out bits we are going to set */
 442         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 443                          | SPMODE_REV | SPMODE_LOOP);
 444
 445         if (spi->mode & SPI_CPHA)
 446                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 447         if (spi->mode & SPI_CPOL)
 448                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 449         if (!(spi->mode & SPI_LSB_FIRST))
 450                 cs->hw_mode |= SPMODE_REV;
 451         if (spi->mode & SPI_LOOP)
 452                 cs->hw_mode |= SPMODE_LOOP;
 453
 454         retval = fsl_spi_setup_transfer(spi, NULL);
 455         if (retval < 0) {
 456                 cs->hw_mode = hw_mode; /* Restore settings */
 457                 return retval;
 458         }
 459
 460         if (mpc8xxx_spi->type == TYPE_GRLIB) {
 461                 if (gpio_is_valid(spi->cs_gpio)) {
 462                         int desel;
 463
 464                         retval = gpio_request(spi->cs_gpio,
 465                                               dev_name(&spi->dev));
 466                         if (retval)
 467                                 return retval;
 468
 469                         desel = !(spi->mode & SPI_CS_HIGH);
 470                         retval = gpio_direction_output(spi->cs_gpio, desel);
 471                         if (retval) {
 472                                 gpio_free(spi->cs_gpio);
 473                                 return retval;
 474                         }
 475                 } else if (spi->cs_gpio != -ENOENT) {
 476                         if (spi->cs_gpio < 0)
 477                                 return spi->cs_gpio;
 478                         return -EINVAL;
 479                 }
 480                 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
 481                  * indicates to use native chipselect if present, or allow for
 482                  * an always selected chip
 483                  */
 484         }
 485
 486         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 487         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 488
 489         return 0;
 490 }
 491
 492 static void fsl_spi_cleanup(struct spi_device *spi)
 493 {
 494         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 495
 496         if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
 497                 gpio_free(spi->cs_gpio);
 498 }
 499
 500 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 501 {
 502         struct fsl_spi_reg *reg_base = mspi->reg_base;
 503
 504         /* We need handle RX first */
 505         if (events & SPIE_NE) {
 506                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 507
 508                 if (mspi->rx)
 509                         mspi->get_rx(rx_data, mspi);
 510         }
 511
 512         if ((events & SPIE_NF) == 0)
 513                 /* spin until TX is done */
 514                 while (((events =
 515                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 516                                                 SPIE_NF) == 0)
 517                         cpu_relax();
 518
 519         /* Clear the events */
 520         mpc8xxx_spi_write_reg(&reg_base->event, events);
 521
 522         mspi->count -= 1;
 523         if (mspi->count) {
 524                 u32 word = mspi->get_tx(mspi);
 525
 526                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 527         } else {
 528                 complete(&mspi->done);
 529         }
 530 }
 531
 532 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 533 {
 534         struct mpc8xxx_spi *mspi = context_data;
 535         irqreturn_t ret = IRQ_NONE;
 536         u32 events;
 537         struct fsl_spi_reg *reg_base = mspi->reg_base;
 538
 539         /* Get interrupt events(tx/rx) */
 540         events = mpc8xxx_spi_read_reg(&reg_base->event);
 541         if (events)
 542                 ret = IRQ_HANDLED;
 543
 544         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 545
 546         if (mspi->flags & SPI_CPM_MODE)
 547                 fsl_spi_cpm_irq(mspi, events);
 548         else
 549                 fsl_spi_cpu_irq(mspi, events);
 550
 551         return ret;
 552 }
 553
 554 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
 555 {
 556         iounmap(mspi->reg_base);
 557         fsl_spi_cpm_free(mspi);
 558 }
 559
 560 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
 561 {
 562         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 563         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 564         u32 slvsel;
 565         u16 cs = spi->chip_select;
 566
 567         if (gpio_is_valid(spi->cs_gpio)) {
 568                 gpio_set_value(spi->cs_gpio, on);
 569         } else if (cs < mpc8xxx_spi->native_chipselects) {
 570                 slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
 571                 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
 572                 mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
 573         }
 574 }
 575
 576 static void fsl_spi_grlib_probe(struct device *dev)
 577 {
 578         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 579         struct spi_master *master = dev_get_drvdata(dev);
 580         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 581         struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
 582         int mbits;
 583         u32 capabilities;
 584
 585         capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
 586
 587         mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
 588         mbits = SPCAP_MAXWLEN(capabilities);
 589         if (mbits)
 590                 mpc8xxx_spi->max_bits_per_word = mbits + 1;
 591
 592         mpc8xxx_spi->native_chipselects = 0;
 593         if (SPCAP_SSEN(capabilities)) {
 594                 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
 595                 mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
 596         }
 597         master->num_chipselect = mpc8xxx_spi->native_chipselects;
 598         pdata->cs_control = fsl_spi_grlib_cs_control;
 599 }
 600
 601 static struct spi_master * fsl_spi_probe(struct device *dev,
 602                 struct resource *mem, unsigned int irq)
 603 {
 604         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 605         struct spi_master *master;
 606         struct mpc8xxx_spi *mpc8xxx_spi;
 607         struct fsl_spi_reg *reg_base;
 608         u32 regval;
 609         int ret = 0;
 610
 611         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 612         if (master == NULL) {
 613                 ret = -ENOMEM;
 614                 goto err;
 615         }
 616
 617         dev_set_drvdata(dev, master);
 618
 619         ret = mpc8xxx_spi_probe(dev, mem, irq);
 620         if (ret)
 621                 goto err_probe;
 622
 623         master->setup = fsl_spi_setup;
 624         master->cleanup = fsl_spi_cleanup;
 625
 626         mpc8xxx_spi = spi_master_get_devdata(master);
 627         mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
 628         mpc8xxx_spi->spi_remove = fsl_spi_remove;
 629         mpc8xxx_spi->max_bits_per_word = 32;
 630         mpc8xxx_spi->type = fsl_spi_get_type(dev);
 631
 632         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 633         if (ret)
 634                 goto err_cpm_init;
 635
 636         mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
 637         if (mpc8xxx_spi->reg_base == NULL) {
 638                 ret = -ENOMEM;
 639                 goto err_ioremap;
 640         }
 641
 642         if (mpc8xxx_spi->type == TYPE_GRLIB)
 643                 fsl_spi_grlib_probe(dev);
 644
 645         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 646                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 647
 648         if (mpc8xxx_spi->set_shifts)
 649                 /* 8 bits per word and MSB first */
 650                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 651                                         &mpc8xxx_spi->tx_shift, 8, 1);
 652
 653         /* Register for SPI Interrupt */
 654         ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
 655                           0, "fsl_spi", mpc8xxx_spi);
 656
 657         if (ret != 0)
 658                 goto free_irq;
 659
 660         reg_base = mpc8xxx_spi->reg_base;
 661
 662         /* SPI controller initializations */
 663         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 664         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 665         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 666         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 667
 668         /* Enable SPI interface */
 669         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 670         if (mpc8xxx_spi->max_bits_per_word < 8) {
 671                 regval &= ~SPMODE_LEN(0xF);
 672                 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
 673         }
 674         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 675                 regval |= SPMODE_OP;
 676
 677         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 678
 679         ret = spi_register_master(master);
 680         if (ret < 0)
 681                 goto unreg_master;
 682
 683         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 684                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 685
 686         return master;
 687
 688 unreg_master:
 689         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
 690 free_irq:
 691         iounmap(mpc8xxx_spi->reg_base);
 692 err_ioremap:
 693         fsl_spi_cpm_free(mpc8xxx_spi);
 694 err_cpm_init:
 695 err_probe:
 696         spi_master_put(master);
 697 err:
 698         return ERR_PTR(ret);
 699 }
 700
 701 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 702 {
 703         struct device *dev = spi->dev.parent->parent;
 704         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 705         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 706         u16 cs = spi->chip_select;
 707         int gpio = pinfo->gpios[cs];
 708         bool alow = pinfo->alow_flags[cs];
 709
 710         gpio_set_value(gpio, on ^ alow);
 711 }
 712
 713 static int of_fsl_spi_get_chipselects(struct device *dev)
 714 {
 715         struct device_node *np = dev->of_node;
 716         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 717         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 718         int ngpios;
 719         int i = 0;
 720         int ret;
 721
 722         ngpios = of_gpio_count(np);
 723         if (ngpios <= 0) {
 724                 /*
 725                  * SPI w/o chip-select line. One SPI device is still permitted
 726                  * though.
 727                  */
 728                 pdata->max_chipselect = 1;
 729                 return 0;
 730         }
 731
 732         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
 733         if (!pinfo->gpios)
 734                 return -ENOMEM;
 735         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 736
 737         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
 738                                     GFP_KERNEL);
 739         if (!pinfo->alow_flags) {
 740                 ret = -ENOMEM;
 741                 goto err_alloc_flags;
 742         }
 743
 744         for (; i < ngpios; i++) {
 745                 int gpio;
 746                 enum of_gpio_flags flags;
 747
 748                 gpio = of_get_gpio_flags(np, i, &flags);
 749                 if (!gpio_is_valid(gpio)) {
 750                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 751                         ret = gpio;
 752                         goto err_loop;
 753                 }
 754
 755                 ret = gpio_request(gpio, dev_name(dev));
 756                 if (ret) {
 757                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 758                         goto err_loop;
 759                 }
 760
 761                 pinfo->gpios[i] = gpio;
 762                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 763
 764                 ret = gpio_direction_output(pinfo->gpios[i],
 765                                             pinfo->alow_flags[i]);
 766                 if (ret) {
 767                         dev_err(dev, "can't set output direction for gpio "
 768                                 "#%d: %d\n", i, ret);
 769                         goto err_loop;
 770                 }
 771         }
 772
 773         pdata->max_chipselect = ngpios;
 774         pdata->cs_control = fsl_spi_cs_control;
 775
 776         return 0;
 777
 778 err_loop:
 779         while (i >= 0) {
 780                 if (gpio_is_valid(pinfo->gpios[i]))
 781                         gpio_free(pinfo->gpios[i]);
 782                 i--;
 783         }
 784
 785         kfree(pinfo->alow_flags);
 786         pinfo->alow_flags = NULL;
 787 err_alloc_flags:
 788         kfree(pinfo->gpios);
 789         pinfo->gpios = NULL;
 790         return ret;
 791 }
 792
 793 static int of_fsl_spi_free_chipselects(struct device *dev)
 794 {
 795         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 796         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 797         int i;
 798
 799         if (!pinfo->gpios)
 800                 return 0;
 801
 802         for (i = 0; i < pdata->max_chipselect; i++) {
 803                 if (gpio_is_valid(pinfo->gpios[i]))
 804                         gpio_free(pinfo->gpios[i]);
 805         }
 806
 807         kfree(pinfo->gpios);
 808         kfree(pinfo->alow_flags);
 809         return 0;
 810 }
 811
 812 static int of_fsl_spi_probe(struct platform_device *ofdev)
 813 {
 814         struct device *dev = &ofdev->dev;
 815         struct device_node *np = ofdev->dev.of_node;
 816         struct spi_master *master;
 817         struct resource mem;
 818         int irq, type;
 819         int ret = -ENOMEM;
 820
 821         ret = of_mpc8xxx_spi_probe(ofdev);
 822         if (ret)
 823                 return ret;
 824
 825         type = fsl_spi_get_type(&ofdev->dev);
 826         if (type == TYPE_FSL) {
 827                 ret = of_fsl_spi_get_chipselects(dev);
 828                 if (ret)
 829                         goto err;
 830         }
 831
 832         ret = of_address_to_resource(np, 0, &mem);
 833         if (ret)
 834                 goto err;
 835
 836         irq = irq_of_parse_and_map(np, 0);
 837         if (!irq) {
 838                 ret = -EINVAL;
 839                 goto err;
 840         }
 841
 842         master = fsl_spi_probe(dev, &mem, irq);
 843         if (IS_ERR(master)) {
 844                 ret = PTR_ERR(master);
 845                 goto err;
 846         }
 847
 848         return 0;
 849
 850 err:
 851         if (type == TYPE_FSL)
 852                 of_fsl_spi_free_chipselects(dev);
 853         return ret;
 854 }
 855
 856 static int of_fsl_spi_remove(struct platform_device *ofdev)
 857 {
 858         struct spi_master *master = platform_get_drvdata(ofdev);
 859         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
 860         int ret;
 861
 862         ret = mpc8xxx_spi_remove(&ofdev->dev);
 863         if (ret)
 864                 return ret;
 865         if (mpc8xxx_spi->type == TYPE_FSL)
 866                 of_fsl_spi_free_chipselects(&ofdev->dev);
 867         return 0;
 868 }
 869
 870 static struct platform_driver of_fsl_spi_driver = {
 871         .driver = {
 872                 .name = "fsl_spi",
 873                 .owner = THIS_MODULE,
 874                 .of_match_table = of_fsl_spi_match,
 875         },
 876         .probe          = of_fsl_spi_probe,
 877         .remove         = of_fsl_spi_remove,
 878 };
 879
 880 #ifdef CONFIG_MPC832x_RDB
 881 /*
 882  * XXX XXX XXX
 883  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 884  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 885  * tree can work with OpenFirmware driver. But for now we support old trees
 886  * as well.
 887  */
 888 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 889 {
 890         struct resource *mem;
 891         int irq;
 892         struct spi_master *master;
 893
 894         if (!dev_get_platdata(&pdev->dev))
 895                 return -EINVAL;
 896
 897         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 898         if (!mem)
 899                 return -EINVAL;
 900
 901         irq = platform_get_irq(pdev, 0);
 902         if (irq <= 0)
 903                 return -EINVAL;
 904
 905         master = fsl_spi_probe(&pdev->dev, mem, irq);
 906         return PTR_ERR_OR_ZERO(master);
 907 }
 908
 909 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 910 {
 911         return mpc8xxx_spi_remove(&pdev->dev);
 912 }
 913
 914 MODULE_ALIAS("platform:mpc8xxx_spi");
 915 static struct platform_driver mpc8xxx_spi_driver = {
 916         .probe = plat_mpc8xxx_spi_probe,
 917         .remove = plat_mpc8xxx_spi_remove,
 918         .driver = {
 919                 .name = "mpc8xxx_spi",
 920                 .owner = THIS_MODULE,
 921         },
 922 };
 923
 924 static bool legacy_driver_failed;
 925
 926 static void __init legacy_driver_register(void)
 927 {
 928         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 929 }
 930
 931 static void __exit legacy_driver_unregister(void)
 932 {
 933         if (legacy_driver_failed)
 934                 return;
 935         platform_driver_unregister(&mpc8xxx_spi_driver);
 936 }
 937 #else
 938 static void __init legacy_driver_register(void) {}
 939 static void __exit legacy_driver_unregister(void) {}
 940 #endif /* CONFIG_MPC832x_RDB */
 941
 942 static int __init fsl_spi_init(void)
 943 {
 944         legacy_driver_register();
 945         return platform_driver_register(&of_fsl_spi_driver);
 946 }
 947 module_init(fsl_spi_init);
 948
 949 static void __exit fsl_spi_exit(void)
 950 {
 951         platform_driver_unregister(&of_fsl_spi_driver);
 952         legacy_driver_unregister();
 953 }
 954 module_exit(fsl_spi_exit);
 955
 956 MODULE_AUTHOR("Kumar Gala");
 957 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 958 MODULE_LICENSE("GPL");