2 * Freescale SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
14 * Copyright (c) 2012 Aeroflex Gaisler AB.
15 * Author: Andreas Larsson <andreas@gaisler.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/platform_device.h>
31 #include <linux/fsl_devices.h>
32 #include <linux/dma-mapping.h>
34 #include <linux/mutex.h>
36 #include <linux/of_platform.h>
37 #include <linux/of_address.h>
38 #include <linux/of_irq.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
42 #include "spi-fsl-lib.h"
43 #include "spi-fsl-cpm.h"
44 #include "spi-fsl-spi.h"
49 struct fsl_spi_match_data {
53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
61 static struct of_device_id of_fsl_spi_match[] = {
63 .compatible = "fsl,spi",
64 .data = &of_fsl_spi_fsl_config,
67 .compatible = "aeroflexgaisler,spictrl",
68 .data = &of_fsl_spi_grlib_config,
72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
74 static int fsl_spi_get_type(struct device *dev)
76 const struct of_device_id *match;
79 match = of_match_node(of_fsl_spi_match, dev->of_node);
80 if (match && match->data)
81 return ((struct fsl_spi_match_data *)match->data)->type;
86 static void fsl_spi_change_mode(struct spi_device *spi)
88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
89 struct spi_mpc8xxx_cs *cs = spi->controller_state;
90 struct fsl_spi_reg *reg_base = mspi->reg_base;
91 __be32 __iomem *mode = ®_base->mode;
94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
97 /* Turn off IRQs locally to minimize time that SPI is disabled. */
98 local_irq_save(flags);
100 /* Turn off SPI unit prior changing mode */
101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
103 /* When in CPM mode, we need to reinit tx and rx. */
104 if (mspi->flags & SPI_CPM_MODE) {
105 fsl_spi_cpm_reinit_txrx(mspi);
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
108 local_irq_restore(flags);
111 static void fsl_spi_chipselect(struct spi_device *spi, int value)
113 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
114 struct fsl_spi_platform_data *pdata;
115 bool pol = spi->mode & SPI_CS_HIGH;
116 struct spi_mpc8xxx_cs *cs = spi->controller_state;
118 pdata = spi->dev.parent->parent->platform_data;
120 if (value == BITBANG_CS_INACTIVE) {
121 if (pdata->cs_control)
122 pdata->cs_control(spi, !pol);
125 if (value == BITBANG_CS_ACTIVE) {
126 mpc8xxx_spi->rx_shift = cs->rx_shift;
127 mpc8xxx_spi->tx_shift = cs->tx_shift;
128 mpc8xxx_spi->get_rx = cs->get_rx;
129 mpc8xxx_spi->get_tx = cs->get_tx;
131 fsl_spi_change_mode(spi);
133 if (pdata->cs_control)
134 pdata->cs_control(spi, pol);
138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
139 int bits_per_word, int msb_first)
144 if (bits_per_word <= 8) {
147 } else if (bits_per_word <= 16) {
152 if (bits_per_word <= 8)
157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
158 int bits_per_word, int msb_first)
162 if (bits_per_word <= 16) {
164 *rx_shift = 16; /* LSB in bit 16 */
165 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
167 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
173 struct spi_device *spi,
174 struct mpc8xxx_spi *mpc8xxx_spi,
179 if (bits_per_word <= 8) {
180 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
181 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
182 } else if (bits_per_word <= 16) {
183 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
184 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
185 } else if (bits_per_word <= 32) {
186 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
187 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
191 if (mpc8xxx_spi->set_shifts)
192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
194 !(spi->mode & SPI_LSB_FIRST));
196 mpc8xxx_spi->rx_shift = cs->rx_shift;
197 mpc8xxx_spi->tx_shift = cs->tx_shift;
198 mpc8xxx_spi->get_rx = cs->get_rx;
199 mpc8xxx_spi->get_tx = cs->get_tx;
201 return bits_per_word;
204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
205 struct spi_device *spi,
208 /* QE uses Little Endian for words > 8
209 * so transform all words > 8 into 8 bits
210 * Unfortnatly that doesn't work for LSB so
211 * reject these for now */
212 /* Note: 32 bits word, LSB works iff
213 * tfcr/rfcr is set to CPMFCR_GBL */
214 if (spi->mode & SPI_LSB_FIRST &&
217 if (bits_per_word > 8)
218 return 8; /* pretend its 8 bits */
219 return bits_per_word;
222 static int fsl_spi_setup_transfer(struct spi_device *spi,
223 struct spi_transfer *t)
225 struct mpc8xxx_spi *mpc8xxx_spi;
226 int bits_per_word = 0;
229 struct spi_mpc8xxx_cs *cs = spi->controller_state;
231 mpc8xxx_spi = spi_master_get_devdata(spi->master);
234 bits_per_word = t->bits_per_word;
238 /* spi_transfer level calls that work per-word */
240 bits_per_word = spi->bits_per_word;
242 /* Make sure its a bit width we support [4..16, 32] */
243 if ((bits_per_word < 4)
244 || ((bits_per_word > 16) && (bits_per_word != 32))
245 || (bits_per_word > mpc8xxx_spi->max_bits_per_word))
249 hz = spi->max_speed_hz;
251 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
252 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
255 else if (mpc8xxx_spi->flags & SPI_QE)
256 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
259 if (bits_per_word < 0)
260 return bits_per_word;
262 if (bits_per_word == 32)
265 bits_per_word = bits_per_word - 1;
267 /* mask out bits we are going to set */
268 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
271 cs->hw_mode |= SPMODE_LEN(bits_per_word);
273 if ((mpc8xxx_spi->spibrg / hz) > 64) {
274 cs->hw_mode |= SPMODE_DIV16;
275 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
277 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
278 "Will use %d Hz instead.\n", dev_name(&spi->dev),
279 hz, mpc8xxx_spi->spibrg / 1024);
283 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
288 cs->hw_mode |= SPMODE_PM(pm);
290 fsl_spi_change_mode(spi);
294 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
295 struct spi_transfer *t, unsigned int len)
298 struct fsl_spi_reg *reg_base = mspi->reg_base;
303 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE);
306 word = mspi->get_tx(mspi);
307 mpc8xxx_spi_write_reg(®_base->transmit, word);
312 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
315 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
316 struct fsl_spi_reg *reg_base;
317 unsigned int len = t->len;
321 reg_base = mpc8xxx_spi->reg_base;
322 bits_per_word = spi->bits_per_word;
323 if (t->bits_per_word)
324 bits_per_word = t->bits_per_word;
326 if (bits_per_word > 8) {
327 /* invalid length? */
332 if (bits_per_word > 16) {
333 /* invalid length? */
339 mpc8xxx_spi->tx = t->tx_buf;
340 mpc8xxx_spi->rx = t->rx_buf;
342 INIT_COMPLETION(mpc8xxx_spi->done);
344 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
345 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
347 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
351 wait_for_completion(&mpc8xxx_spi->done);
353 /* disable rx ints */
354 mpc8xxx_spi_write_reg(®_base->mask, 0);
356 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
357 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
359 return mpc8xxx_spi->count;
362 static void fsl_spi_do_one_msg(struct spi_message *m)
364 struct spi_device *spi = m->spi;
365 struct spi_transfer *t;
366 unsigned int cs_change;
367 const int nsecs = 50;
372 list_for_each_entry(t, &m->transfers, transfer_list) {
373 if (t->bits_per_word || t->speed_hz) {
374 /* Don't allow changes if CS is active */
378 status = fsl_spi_setup_transfer(spi, t);
384 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
387 cs_change = t->cs_change;
389 status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
394 m->actual_length += t->len;
397 udelay(t->delay_usecs);
401 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
407 m->complete(m->context);
409 if (status || !cs_change) {
411 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
414 fsl_spi_setup_transfer(spi, NULL);
417 static int fsl_spi_setup(struct spi_device *spi)
419 struct mpc8xxx_spi *mpc8xxx_spi;
420 struct fsl_spi_reg *reg_base;
423 struct spi_mpc8xxx_cs *cs = spi->controller_state;
425 if (!spi->max_speed_hz)
429 cs = kzalloc(sizeof *cs, GFP_KERNEL);
432 spi->controller_state = cs;
434 mpc8xxx_spi = spi_master_get_devdata(spi->master);
436 reg_base = mpc8xxx_spi->reg_base;
438 hw_mode = cs->hw_mode; /* Save original settings */
439 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode);
440 /* mask out bits we are going to set */
441 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
442 | SPMODE_REV | SPMODE_LOOP);
444 if (spi->mode & SPI_CPHA)
445 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
446 if (spi->mode & SPI_CPOL)
447 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
448 if (!(spi->mode & SPI_LSB_FIRST))
449 cs->hw_mode |= SPMODE_REV;
450 if (spi->mode & SPI_LOOP)
451 cs->hw_mode |= SPMODE_LOOP;
453 retval = fsl_spi_setup_transfer(spi, NULL);
455 cs->hw_mode = hw_mode; /* Restore settings */
459 if (mpc8xxx_spi->type == TYPE_GRLIB) {
460 if (gpio_is_valid(spi->cs_gpio)) {
463 retval = gpio_request(spi->cs_gpio,
464 dev_name(&spi->dev));
468 desel = !(spi->mode & SPI_CS_HIGH);
469 retval = gpio_direction_output(spi->cs_gpio, desel);
471 gpio_free(spi->cs_gpio);
474 } else if (spi->cs_gpio != -ENOENT) {
475 if (spi->cs_gpio < 0)
479 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
480 * indicates to use native chipselect if present, or allow for
481 * an always selected chip
485 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
486 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
491 static void fsl_spi_cleanup(struct spi_device *spi)
493 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
495 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
496 gpio_free(spi->cs_gpio);
499 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
501 struct fsl_spi_reg *reg_base = mspi->reg_base;
503 /* We need handle RX first */
504 if (events & SPIE_NE) {
505 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive);
508 mspi->get_rx(rx_data, mspi);
511 if ((events & SPIE_NF) == 0)
512 /* spin until TX is done */
514 mpc8xxx_spi_read_reg(®_base->event)) &
518 /* Clear the events */
519 mpc8xxx_spi_write_reg(®_base->event, events);
523 u32 word = mspi->get_tx(mspi);
525 mpc8xxx_spi_write_reg(®_base->transmit, word);
527 complete(&mspi->done);
531 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
533 struct mpc8xxx_spi *mspi = context_data;
534 irqreturn_t ret = IRQ_NONE;
536 struct fsl_spi_reg *reg_base = mspi->reg_base;
538 /* Get interrupt events(tx/rx) */
539 events = mpc8xxx_spi_read_reg(®_base->event);
543 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
545 if (mspi->flags & SPI_CPM_MODE)
546 fsl_spi_cpm_irq(mspi, events);
548 fsl_spi_cpu_irq(mspi, events);
553 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
555 iounmap(mspi->reg_base);
556 fsl_spi_cpm_free(mspi);
559 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
561 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
562 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
564 u16 cs = spi->chip_select;
566 if (gpio_is_valid(spi->cs_gpio)) {
567 gpio_set_value(spi->cs_gpio, on);
568 } else if (cs < mpc8xxx_spi->native_chipselects) {
569 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel);
570 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
571 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel);
575 static void fsl_spi_grlib_probe(struct device *dev)
577 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
578 struct spi_master *master = dev_get_drvdata(dev);
579 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
580 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
584 capabilities = mpc8xxx_spi_read_reg(®_base->cap);
586 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
587 mbits = SPCAP_MAXWLEN(capabilities);
589 mpc8xxx_spi->max_bits_per_word = mbits + 1;
591 mpc8xxx_spi->native_chipselects = 0;
592 if (SPCAP_SSEN(capabilities)) {
593 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
594 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff);
596 master->num_chipselect = mpc8xxx_spi->native_chipselects;
597 pdata->cs_control = fsl_spi_grlib_cs_control;
600 static struct spi_master * fsl_spi_probe(struct device *dev,
601 struct resource *mem, unsigned int irq)
603 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
604 struct spi_master *master;
605 struct mpc8xxx_spi *mpc8xxx_spi;
606 struct fsl_spi_reg *reg_base;
610 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
611 if (master == NULL) {
616 dev_set_drvdata(dev, master);
618 ret = mpc8xxx_spi_probe(dev, mem, irq);
622 master->setup = fsl_spi_setup;
623 master->cleanup = fsl_spi_cleanup;
625 mpc8xxx_spi = spi_master_get_devdata(master);
626 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
627 mpc8xxx_spi->spi_remove = fsl_spi_remove;
628 mpc8xxx_spi->max_bits_per_word = 32;
629 mpc8xxx_spi->type = fsl_spi_get_type(dev);
631 ret = fsl_spi_cpm_init(mpc8xxx_spi);
635 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
636 if (mpc8xxx_spi->reg_base == NULL) {
641 if (mpc8xxx_spi->type == TYPE_GRLIB)
642 fsl_spi_grlib_probe(dev);
644 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
645 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
647 if (mpc8xxx_spi->set_shifts)
648 /* 8 bits per word and MSB first */
649 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
650 &mpc8xxx_spi->tx_shift, 8, 1);
652 /* Register for SPI Interrupt */
653 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
654 0, "fsl_spi", mpc8xxx_spi);
659 reg_base = mpc8xxx_spi->reg_base;
661 /* SPI controller initializations */
662 mpc8xxx_spi_write_reg(®_base->mode, 0);
663 mpc8xxx_spi_write_reg(®_base->mask, 0);
664 mpc8xxx_spi_write_reg(®_base->command, 0);
665 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
667 /* Enable SPI interface */
668 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
669 if (mpc8xxx_spi->max_bits_per_word < 8) {
670 regval &= ~SPMODE_LEN(0xF);
671 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
673 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
676 mpc8xxx_spi_write_reg(®_base->mode, regval);
678 ret = spi_register_master(master);
682 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
683 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
688 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
690 iounmap(mpc8xxx_spi->reg_base);
692 fsl_spi_cpm_free(mpc8xxx_spi);
695 spi_master_put(master);
700 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
702 struct device *dev = spi->dev.parent->parent;
703 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
704 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
705 u16 cs = spi->chip_select;
706 int gpio = pinfo->gpios[cs];
707 bool alow = pinfo->alow_flags[cs];
709 gpio_set_value(gpio, on ^ alow);
712 static int of_fsl_spi_get_chipselects(struct device *dev)
714 struct device_node *np = dev->of_node;
715 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
716 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
721 ngpios = of_gpio_count(np);
724 * SPI w/o chip-select line. One SPI device is still permitted
727 pdata->max_chipselect = 1;
731 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
734 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
736 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
738 if (!pinfo->alow_flags) {
740 goto err_alloc_flags;
743 for (; i < ngpios; i++) {
745 enum of_gpio_flags flags;
747 gpio = of_get_gpio_flags(np, i, &flags);
748 if (!gpio_is_valid(gpio)) {
749 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
754 ret = gpio_request(gpio, dev_name(dev));
756 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
760 pinfo->gpios[i] = gpio;
761 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
763 ret = gpio_direction_output(pinfo->gpios[i],
764 pinfo->alow_flags[i]);
766 dev_err(dev, "can't set output direction for gpio "
767 "#%d: %d\n", i, ret);
772 pdata->max_chipselect = ngpios;
773 pdata->cs_control = fsl_spi_cs_control;
779 if (gpio_is_valid(pinfo->gpios[i]))
780 gpio_free(pinfo->gpios[i]);
784 kfree(pinfo->alow_flags);
785 pinfo->alow_flags = NULL;
792 static int of_fsl_spi_free_chipselects(struct device *dev)
794 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
795 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
801 for (i = 0; i < pdata->max_chipselect; i++) {
802 if (gpio_is_valid(pinfo->gpios[i]))
803 gpio_free(pinfo->gpios[i]);
807 kfree(pinfo->alow_flags);
811 static int of_fsl_spi_probe(struct platform_device *ofdev)
813 struct device *dev = &ofdev->dev;
814 struct device_node *np = ofdev->dev.of_node;
815 struct spi_master *master;
820 ret = of_mpc8xxx_spi_probe(ofdev);
824 type = fsl_spi_get_type(&ofdev->dev);
825 if (type == TYPE_FSL) {
826 ret = of_fsl_spi_get_chipselects(dev);
831 ret = of_address_to_resource(np, 0, &mem);
835 irq = irq_of_parse_and_map(np, 0);
841 master = fsl_spi_probe(dev, &mem, irq);
842 if (IS_ERR(master)) {
843 ret = PTR_ERR(master);
850 if (type == TYPE_FSL)
851 of_fsl_spi_free_chipselects(dev);
855 static int of_fsl_spi_remove(struct platform_device *ofdev)
857 struct spi_master *master = platform_get_drvdata(ofdev);
858 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
861 ret = mpc8xxx_spi_remove(&ofdev->dev);
864 if (mpc8xxx_spi->type == TYPE_FSL)
865 of_fsl_spi_free_chipselects(&ofdev->dev);
869 static struct platform_driver of_fsl_spi_driver = {
872 .owner = THIS_MODULE,
873 .of_match_table = of_fsl_spi_match,
875 .probe = of_fsl_spi_probe,
876 .remove = of_fsl_spi_remove,
879 #ifdef CONFIG_MPC832x_RDB
882 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
883 * only. The driver should go away soon, since newer MPC8323E-RDB's device
884 * tree can work with OpenFirmware driver. But for now we support old trees
887 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
889 struct resource *mem;
891 struct spi_master *master;
893 if (!dev_get_platdata(&pdev->dev))
896 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
900 irq = platform_get_irq(pdev, 0);
904 master = fsl_spi_probe(&pdev->dev, mem, irq);
905 return PTR_RET(master);
908 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
910 return mpc8xxx_spi_remove(&pdev->dev);
913 MODULE_ALIAS("platform:mpc8xxx_spi");
914 static struct platform_driver mpc8xxx_spi_driver = {
915 .probe = plat_mpc8xxx_spi_probe,
916 .remove = plat_mpc8xxx_spi_remove,
918 .name = "mpc8xxx_spi",
919 .owner = THIS_MODULE,
923 static bool legacy_driver_failed;
925 static void __init legacy_driver_register(void)
927 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
930 static void __exit legacy_driver_unregister(void)
932 if (legacy_driver_failed)
934 platform_driver_unregister(&mpc8xxx_spi_driver);
937 static void __init legacy_driver_register(void) {}
938 static void __exit legacy_driver_unregister(void) {}
939 #endif /* CONFIG_MPC832x_RDB */
941 static int __init fsl_spi_init(void)
943 legacy_driver_register();
944 return platform_driver_register(&of_fsl_spi_driver);
946 module_init(fsl_spi_init);
948 static void __exit fsl_spi_exit(void)
950 platform_driver_unregister(&of_fsl_spi_driver);
951 legacy_driver_unregister();
953 module_exit(fsl_spi_exit);
955 MODULE_AUTHOR("Kumar Gala");
956 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
957 MODULE_LICENSE("GPL");