2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Leilk Liu <leilk.liu@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/err.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/platform_data/spi-mt65xx.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
27 #define SPI_CFG0_REG 0x0000
28 #define SPI_CFG1_REG 0x0004
29 #define SPI_TX_SRC_REG 0x0008
30 #define SPI_RX_DST_REG 0x000c
31 #define SPI_TX_DATA_REG 0x0010
32 #define SPI_RX_DATA_REG 0x0014
33 #define SPI_CMD_REG 0x0018
34 #define SPI_STATUS0_REG 0x001c
35 #define SPI_PAD_SEL_REG 0x0024
37 #define SPI_CFG0_SCK_HIGH_OFFSET 0
38 #define SPI_CFG0_SCK_LOW_OFFSET 8
39 #define SPI_CFG0_CS_HOLD_OFFSET 16
40 #define SPI_CFG0_CS_SETUP_OFFSET 24
42 #define SPI_CFG1_CS_IDLE_OFFSET 0
43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
47 #define SPI_CFG1_CS_IDLE_MASK 0xff
48 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
49 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
51 #define SPI_CMD_ACT_OFFSET 0
52 #define SPI_CMD_RESUME_OFFSET 1
53 #define SPI_CMD_CPHA_OFFSET 8
54 #define SPI_CMD_CPOL_OFFSET 9
55 #define SPI_CMD_TXMSBF_OFFSET 12
56 #define SPI_CMD_RXMSBF_OFFSET 13
57 #define SPI_CMD_RX_ENDIAN_OFFSET 14
58 #define SPI_CMD_TX_ENDIAN_OFFSET 15
60 #define SPI_CMD_RST BIT(2)
61 #define SPI_CMD_PAUSE_EN BIT(4)
62 #define SPI_CMD_DEASSERT BIT(5)
63 #define SPI_CMD_CPHA BIT(8)
64 #define SPI_CMD_CPOL BIT(9)
65 #define SPI_CMD_RX_DMA BIT(10)
66 #define SPI_CMD_TX_DMA BIT(11)
67 #define SPI_CMD_TXMSBF BIT(12)
68 #define SPI_CMD_RXMSBF BIT(13)
69 #define SPI_CMD_RX_ENDIAN BIT(14)
70 #define SPI_CMD_TX_ENDIAN BIT(15)
71 #define SPI_CMD_FINISH_IE BIT(16)
72 #define SPI_CMD_PAUSE_IE BIT(17)
74 #define MTK_SPI_QUIRK_PAD_SELECT 1
75 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
76 #define MTK_SPI_QUIRK_MUST_TX 1
78 #define MT8173_SPI_MAX_PAD_SEL 3
80 #define MTK_SPI_IDLE 0
81 #define MTK_SPI_PAUSED 1
83 #define MTK_SPI_MAX_FIFO_SIZE 32
84 #define MTK_SPI_PACKET_SIZE 1024
86 struct mtk_spi_compatible {
95 struct clk *spi_clk, *parent_clk;
96 struct spi_transfer *cur_transfer;
98 struct scatterlist *tx_sgl, *rx_sgl;
99 u32 tx_sgl_len, rx_sgl_len;
100 const struct mtk_spi_compatible *dev_comp;
103 static const struct mtk_spi_compatible mt6589_compat = {
108 static const struct mtk_spi_compatible mt8135_compat = {
113 static const struct mtk_spi_compatible mt8173_compat = {
114 .need_pad_sel = MTK_SPI_QUIRK_PAD_SELECT,
115 .must_tx = MTK_SPI_QUIRK_MUST_TX,
119 * A piece of default chip info unless the platform
122 static const struct mtk_chip_config mtk_default_chip_info = {
129 static const struct of_device_id mtk_spi_of_match[] = {
130 { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat },
131 { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat },
132 { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat },
135 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
137 static void mtk_spi_reset(struct mtk_spi *mdata)
141 /* set the software reset bit in SPI_CMD_REG. */
142 reg_val = readl(mdata->base + SPI_CMD_REG);
143 reg_val |= SPI_CMD_RST;
144 writel(reg_val, mdata->base + SPI_CMD_REG);
146 reg_val = readl(mdata->base + SPI_CMD_REG);
147 reg_val &= ~SPI_CMD_RST;
148 writel(reg_val, mdata->base + SPI_CMD_REG);
151 static void mtk_spi_config(struct mtk_spi *mdata,
152 struct mtk_chip_config *chip_config)
156 reg_val = readl(mdata->base + SPI_CMD_REG);
158 /* set the mlsbx and mlsbtx */
159 reg_val &= ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF);
160 reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET);
161 reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET);
163 /* set the tx/rx endian */
164 reg_val &= ~(SPI_CMD_TX_ENDIAN | SPI_CMD_RX_ENDIAN);
165 reg_val |= (chip_config->tx_endian << SPI_CMD_TX_ENDIAN_OFFSET);
166 reg_val |= (chip_config->rx_endian << SPI_CMD_RX_ENDIAN_OFFSET);
168 /* set finish and pause interrupt always enable */
169 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN;
171 /* disable dma mode */
172 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
174 /* disable deassert mode */
175 reg_val &= ~SPI_CMD_DEASSERT;
177 writel(reg_val, mdata->base + SPI_CMD_REG);
180 if (mdata->dev_comp->need_pad_sel)
181 writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
184 static int mtk_spi_prepare_hardware(struct spi_master *master)
186 struct spi_transfer *trans;
187 struct mtk_spi *mdata = spi_master_get_devdata(master);
188 struct spi_message *msg = master->cur_msg;
191 ret = clk_prepare_enable(mdata->spi_clk);
193 dev_err(&master->dev, "failed to enable clock (%d)\n", ret);
197 trans = list_first_entry(&msg->transfers, struct spi_transfer,
199 if (trans->cs_change == 0) {
200 mdata->state = MTK_SPI_IDLE;
201 mtk_spi_reset(mdata);
207 static int mtk_spi_unprepare_hardware(struct spi_master *master)
209 struct mtk_spi *mdata = spi_master_get_devdata(master);
211 clk_disable_unprepare(mdata->spi_clk);
216 static int mtk_spi_prepare_message(struct spi_master *master,
217 struct spi_message *msg)
221 struct mtk_chip_config *chip_config;
222 struct spi_device *spi = msg->spi;
223 struct mtk_spi *mdata = spi_master_get_devdata(master);
225 cpha = spi->mode & SPI_CPHA ? 1 : 0;
226 cpol = spi->mode & SPI_CPOL ? 1 : 0;
228 reg_val = readl(mdata->base + SPI_CMD_REG);
229 reg_val &= ~(SPI_CMD_CPHA | SPI_CMD_CPOL);
230 reg_val |= (cpha << SPI_CMD_CPHA_OFFSET);
231 reg_val |= (cpol << SPI_CMD_CPOL_OFFSET);
232 writel(reg_val, mdata->base + SPI_CMD_REG);
234 chip_config = spi->controller_data;
236 chip_config = (void *)&mtk_default_chip_info;
237 spi->controller_data = chip_config;
239 mtk_spi_config(mdata, chip_config);
244 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
247 struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
249 reg_val = readl(mdata->base + SPI_CMD_REG);
251 reg_val |= SPI_CMD_PAUSE_EN;
253 reg_val &= ~SPI_CMD_PAUSE_EN;
254 writel(reg_val, mdata->base + SPI_CMD_REG);
257 static void mtk_spi_prepare_transfer(struct spi_master *master,
258 struct spi_transfer *xfer)
260 u32 spi_clk_hz, div, high_time, low_time, holdtime,
261 setuptime, cs_idletime, reg_val = 0;
262 struct mtk_spi *mdata = spi_master_get_devdata(master);
264 spi_clk_hz = clk_get_rate(mdata->spi_clk);
265 if (xfer->speed_hz < spi_clk_hz / 2)
266 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz);
270 high_time = (div + 1) / 2;
271 low_time = (div + 1) / 2;
272 holdtime = (div + 1) / 2 * 2;
273 setuptime = (div + 1) / 2 * 2;
274 cs_idletime = (div + 1) / 2 * 2;
276 reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
277 reg_val |= (((low_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
278 reg_val |= (((holdtime - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
279 reg_val |= (((setuptime - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET);
280 writel(reg_val, mdata->base + SPI_CFG0_REG);
282 reg_val = readl(mdata->base + SPI_CFG1_REG);
283 reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
284 reg_val |= (((cs_idletime - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
285 writel(reg_val, mdata->base + SPI_CFG1_REG);
288 static void mtk_spi_setup_packet(struct spi_master *master)
290 u32 packet_size, packet_loop, reg_val;
291 struct mtk_spi *mdata = spi_master_get_devdata(master);
293 packet_size = min_t(unsigned, mdata->xfer_len, MTK_SPI_PACKET_SIZE);
294 packet_loop = mdata->xfer_len / packet_size;
296 reg_val = readl(mdata->base + SPI_CFG1_REG);
297 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK + SPI_CFG1_PACKET_LOOP_MASK);
298 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
299 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
300 writel(reg_val, mdata->base + SPI_CFG1_REG);
303 static void mtk_spi_enable_transfer(struct spi_master *master)
306 struct mtk_spi *mdata = spi_master_get_devdata(master);
308 cmd = readl(mdata->base + SPI_CMD_REG);
309 if (mdata->state == MTK_SPI_IDLE)
310 cmd |= 1 << SPI_CMD_ACT_OFFSET;
312 cmd |= 1 << SPI_CMD_RESUME_OFFSET;
313 writel(cmd, mdata->base + SPI_CMD_REG);
316 static int mtk_spi_get_mult_delta(int xfer_len)
320 if (xfer_len > MTK_SPI_PACKET_SIZE)
321 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
328 static void mtk_spi_update_mdata_len(struct spi_master *master)
331 struct mtk_spi *mdata = spi_master_get_devdata(master);
333 if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
334 if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
335 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
336 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
337 mdata->rx_sgl_len = mult_delta;
338 mdata->tx_sgl_len -= mdata->xfer_len;
340 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
341 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
342 mdata->tx_sgl_len = mult_delta;
343 mdata->rx_sgl_len -= mdata->xfer_len;
345 } else if (mdata->tx_sgl_len) {
346 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len);
347 mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
348 mdata->tx_sgl_len = mult_delta;
349 } else if (mdata->rx_sgl_len) {
350 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len);
351 mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
352 mdata->rx_sgl_len = mult_delta;
356 static void mtk_spi_setup_dma_addr(struct spi_master *master,
357 struct spi_transfer *xfer)
359 struct mtk_spi *mdata = spi_master_get_devdata(master);
362 writel(cpu_to_le32(xfer->tx_dma), mdata->base + SPI_TX_SRC_REG);
364 writel(cpu_to_le32(xfer->rx_dma), mdata->base + SPI_RX_DST_REG);
367 static int mtk_spi_fifo_transfer(struct spi_master *master,
368 struct spi_device *spi,
369 struct spi_transfer *xfer)
372 struct mtk_spi *mdata = spi_master_get_devdata(master);
374 mdata->cur_transfer = xfer;
375 mdata->xfer_len = xfer->len;
376 mtk_spi_prepare_transfer(master, xfer);
377 mtk_spi_setup_packet(master);
380 cnt = xfer->len / 4 + 1;
384 for (i = 0; i < cnt; i++)
385 writel(*((u32 *)xfer->tx_buf + i),
386 mdata->base + SPI_TX_DATA_REG);
388 mtk_spi_enable_transfer(master);
393 static int mtk_spi_dma_transfer(struct spi_master *master,
394 struct spi_device *spi,
395 struct spi_transfer *xfer)
398 struct mtk_spi *mdata = spi_master_get_devdata(master);
400 mdata->tx_sgl = NULL;
401 mdata->rx_sgl = NULL;
402 mdata->tx_sgl_len = 0;
403 mdata->rx_sgl_len = 0;
404 mdata->cur_transfer = xfer;
406 mtk_spi_prepare_transfer(master, xfer);
408 cmd = readl(mdata->base + SPI_CMD_REG);
410 cmd |= SPI_CMD_TX_DMA;
412 cmd |= SPI_CMD_RX_DMA;
413 writel(cmd, mdata->base + SPI_CMD_REG);
416 mdata->tx_sgl = xfer->tx_sg.sgl;
418 mdata->rx_sgl = xfer->rx_sg.sgl;
421 xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
422 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
425 xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
426 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
429 mtk_spi_update_mdata_len(master);
430 mtk_spi_setup_packet(master);
431 mtk_spi_setup_dma_addr(master, xfer);
432 mtk_spi_enable_transfer(master);
437 static int mtk_spi_transfer_one(struct spi_master *master,
438 struct spi_device *spi,
439 struct spi_transfer *xfer)
441 if (master->can_dma(master, spi, xfer))
442 return mtk_spi_dma_transfer(master, spi, xfer);
444 return mtk_spi_fifo_transfer(master, spi, xfer);
447 static bool mtk_spi_can_dma(struct spi_master *master,
448 struct spi_device *spi,
449 struct spi_transfer *xfer)
451 return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
454 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
457 struct spi_master *master = dev_id;
458 struct mtk_spi *mdata = spi_master_get_devdata(master);
459 struct spi_transfer *trans = mdata->cur_transfer;
461 reg_val = readl(mdata->base + SPI_STATUS0_REG);
463 mdata->state = MTK_SPI_PAUSED;
465 mdata->state = MTK_SPI_IDLE;
467 if (!master->can_dma(master, master->cur_msg->spi, trans)) {
468 /* xfer len is not N*4 bytes every time in a transfer,
469 * but SPI_RX_DATA_REG must reads 4 bytes once,
470 * so rx buffer byte by byte.
473 for (i = 0; i < mdata->xfer_len; i++) {
476 readl(mdata->base + SPI_RX_DATA_REG);
477 *((u8 *)(trans->rx_buf + i)) =
478 (reg_val >> ((i % 4) * 8)) & 0xff;
481 spi_finalize_current_transfer(master);
486 trans->tx_dma += mdata->xfer_len;
488 trans->rx_dma += mdata->xfer_len;
490 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
491 mdata->tx_sgl = sg_next(mdata->tx_sgl);
493 trans->tx_dma = sg_dma_address(mdata->tx_sgl);
494 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
497 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
498 mdata->rx_sgl = sg_next(mdata->rx_sgl);
500 trans->rx_dma = sg_dma_address(mdata->rx_sgl);
501 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
505 if (!mdata->tx_sgl && !mdata->rx_sgl) {
506 /* spi disable dma */
507 cmd = readl(mdata->base + SPI_CMD_REG);
508 cmd &= ~SPI_CMD_TX_DMA;
509 cmd &= ~SPI_CMD_RX_DMA;
510 writel(cmd, mdata->base + SPI_CMD_REG);
512 spi_finalize_current_transfer(master);
516 mtk_spi_update_mdata_len(master);
517 mtk_spi_setup_packet(master);
518 mtk_spi_setup_dma_addr(master, trans);
519 mtk_spi_enable_transfer(master);
524 static int mtk_spi_probe(struct platform_device *pdev)
526 struct spi_master *master;
527 struct mtk_spi *mdata;
528 const struct of_device_id *of_id;
529 struct resource *res;
532 master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
534 dev_err(&pdev->dev, "failed to alloc spi master\n");
538 master->auto_runtime_pm = true;
539 master->dev.of_node = pdev->dev.of_node;
540 master->mode_bits = SPI_CPOL | SPI_CPHA;
542 master->set_cs = mtk_spi_set_cs;
543 master->prepare_transfer_hardware = mtk_spi_prepare_hardware;
544 master->unprepare_transfer_hardware = mtk_spi_unprepare_hardware;
545 master->prepare_message = mtk_spi_prepare_message;
546 master->transfer_one = mtk_spi_transfer_one;
547 master->can_dma = mtk_spi_can_dma;
549 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
551 dev_err(&pdev->dev, "failed to probe of_node\n");
556 mdata = spi_master_get_devdata(master);
557 mdata->dev_comp = of_id->data;
558 if (mdata->dev_comp->must_tx)
559 master->flags = SPI_MASTER_MUST_TX;
561 if (mdata->dev_comp->need_pad_sel) {
562 ret = of_property_read_u32(pdev->dev.of_node,
563 "mediatek,pad-select",
566 dev_err(&pdev->dev, "failed to read pad select: %d\n",
571 if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) {
572 dev_err(&pdev->dev, "wrong pad-select: %u\n",
579 platform_set_drvdata(pdev, master);
581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
584 dev_err(&pdev->dev, "failed to determine base address\n");
588 mdata->base = devm_ioremap_resource(&pdev->dev, res);
589 if (IS_ERR(mdata->base)) {
590 ret = PTR_ERR(mdata->base);
594 irq = platform_get_irq(pdev, 0);
596 dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
601 if (!pdev->dev.dma_mask)
602 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
604 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt,
605 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master);
607 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
611 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk");
612 if (IS_ERR(mdata->spi_clk)) {
613 ret = PTR_ERR(mdata->spi_clk);
614 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret);
618 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk");
619 if (IS_ERR(mdata->parent_clk)) {
620 ret = PTR_ERR(mdata->parent_clk);
621 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret);
625 ret = clk_prepare_enable(mdata->spi_clk);
627 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret);
631 ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk);
633 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret);
634 goto err_disable_clk;
637 clk_disable_unprepare(mdata->spi_clk);
639 pm_runtime_enable(&pdev->dev);
641 ret = devm_spi_register_master(&pdev->dev, master);
643 dev_err(&pdev->dev, "failed to register master (%d)\n", ret);
650 clk_disable_unprepare(mdata->spi_clk);
652 spi_master_put(master);
657 static int mtk_spi_remove(struct platform_device *pdev)
659 struct spi_master *master = platform_get_drvdata(pdev);
660 struct mtk_spi *mdata = spi_master_get_devdata(master);
662 pm_runtime_disable(&pdev->dev);
664 mtk_spi_reset(mdata);
665 clk_disable_unprepare(mdata->spi_clk);
666 spi_master_put(master);
671 #ifdef CONFIG_PM_SLEEP
672 static int mtk_spi_suspend(struct device *dev)
675 struct spi_master *master = dev_get_drvdata(dev);
676 struct mtk_spi *mdata = spi_master_get_devdata(master);
678 ret = spi_master_suspend(master);
682 if (!pm_runtime_suspended(dev))
683 clk_disable_unprepare(mdata->spi_clk);
688 static int mtk_spi_resume(struct device *dev)
691 struct spi_master *master = dev_get_drvdata(dev);
692 struct mtk_spi *mdata = spi_master_get_devdata(master);
694 if (!pm_runtime_suspended(dev)) {
695 ret = clk_prepare_enable(mdata->spi_clk);
700 ret = spi_master_resume(master);
702 clk_disable_unprepare(mdata->spi_clk);
706 #endif /* CONFIG_PM_SLEEP */
709 static int mtk_spi_runtime_suspend(struct device *dev)
711 struct spi_master *master = dev_get_drvdata(dev);
712 struct mtk_spi *mdata = spi_master_get_devdata(master);
714 clk_disable_unprepare(mdata->spi_clk);
719 static int mtk_spi_runtime_resume(struct device *dev)
721 struct spi_master *master = dev_get_drvdata(dev);
722 struct mtk_spi *mdata = spi_master_get_devdata(master);
724 return clk_prepare_enable(mdata->spi_clk);
726 #endif /* CONFIG_PM */
728 static const struct dev_pm_ops mtk_spi_pm = {
729 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
730 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
731 mtk_spi_runtime_resume, NULL)
734 static struct platform_driver mtk_spi_driver = {
738 .of_match_table = mtk_spi_of_match,
740 .probe = mtk_spi_probe,
741 .remove = mtk_spi_remove,
744 module_platform_driver(mtk_spi_driver);
746 MODULE_DESCRIPTION("MTK SPI Controller driver");
747 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
748 MODULE_LICENSE("GPL v2");
749 MODULE_ALIAS("platform:mtk-spi");