2 * Freescale MXS SPI master driver
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/init.h>
33 #include <linux/ioport.h>
35 #include <linux/of_device.h>
36 #include <linux/of_gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/dmaengine.h>
42 #include <linux/highmem.h>
43 #include <linux/clk.h>
44 #include <linux/err.h>
45 #include <linux/completion.h>
46 #include <linux/gpio.h>
47 #include <linux/regulator/consumer.h>
48 #include <linux/module.h>
49 #include <linux/stmp_device.h>
50 #include <linux/spi/spi.h>
51 #include <linux/spi/mxs-spi.h>
53 #define DRIVER_NAME "mxs-spi"
55 /* Use 10S timeout for very long transfers, it should suffice. */
56 #define SSP_TIMEOUT 10000
58 #define SG_MAXLEN 0xff00
65 static int mxs_spi_setup_transfer(struct spi_device *dev,
66 struct spi_transfer *t)
68 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
69 struct mxs_ssp *ssp = &spi->ssp;
72 hz = dev->max_speed_hz;
74 hz = min(hz, t->speed_hz);
76 dev_err(&dev->dev, "Cannot continue with zero clock\n");
80 mxs_ssp_set_clk_rate(ssp, hz);
82 writel(BM_SSP_CTRL0_LOCK_CS,
83 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
84 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
85 BF_SSP_CTRL1_WORD_LENGTH
86 (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
87 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
88 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
89 ssp->base + HW_SSP_CTRL1(ssp));
91 writel(0x0, ssp->base + HW_SSP_CMD0);
92 writel(0x0, ssp->base + HW_SSP_CMD1);
97 static int mxs_spi_setup(struct spi_device *dev)
101 if (!dev->bits_per_word)
102 dev->bits_per_word = 8;
104 if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
107 err = mxs_spi_setup_transfer(dev, NULL);
110 "Failed to setup transfer, error = %d\n", err);
116 static uint32_t mxs_spi_cs_to_reg(unsigned cs)
121 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
123 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
124 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
125 * the datasheet for further details. In SPI mode, they are used to
126 * toggle the chip-select lines (nCS pins).
129 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
131 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
136 static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
138 const uint32_t mask =
139 BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
141 struct mxs_ssp *ssp = &spi->ssp;
143 writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
144 select = mxs_spi_cs_to_reg(cs);
145 writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
148 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
150 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
151 struct mxs_ssp *ssp = &spi->ssp;
155 reg = readl_relaxed(ssp->base + offset);
164 } while (time_before(jiffies, timeout));
169 static void mxs_ssp_dma_irq_callback(void *param)
171 struct mxs_spi *spi = param;
175 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
177 struct mxs_ssp *ssp = dev_id;
178 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
180 readl(ssp->base + HW_SSP_CTRL1(ssp)),
181 readl(ssp->base + HW_SSP_STATUS(ssp)));
185 static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
186 unsigned char *buf, int len,
187 int *first, int *last, int write)
189 struct mxs_ssp *ssp = &spi->ssp;
190 struct dma_async_tx_descriptor *desc = NULL;
191 const bool vmalloced_buf = is_vmalloc_addr(buf);
192 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
193 const int sgs = DIV_ROUND_UP(len, desc_len);
197 struct page *vm_page;
201 struct scatterlist sg;
207 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
211 INIT_COMPLETION(spi->c);
213 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
214 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
215 ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);
218 ctrl0 |= BM_SSP_CTRL0_READ;
220 /* Queue the DMA data transfer. */
221 for (sg_count = 0; sg_count < sgs; sg_count++) {
222 min = min(len, desc_len);
224 /* Prepare the transfer descriptor. */
225 if ((sg_count + 1 == sgs) && *last)
226 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
228 if (ssp->devid == IMX23_SSP) {
229 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
233 dma_xfer[sg_count].pio[0] = ctrl0;
234 dma_xfer[sg_count].pio[3] = min;
237 vm_page = vmalloc_to_page(buf);
242 sg_buf = page_address(vm_page) +
243 ((size_t)buf & ~PAGE_MASK);
248 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
249 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
250 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
255 /* Queue the PIO register write transfer. */
256 desc = dmaengine_prep_slave_sg(ssp->dmach,
257 (struct scatterlist *)dma_xfer[sg_count].pio,
258 (ssp->devid == IMX23_SSP) ? 1 : 4,
260 sg_count ? DMA_PREP_INTERRUPT : 0);
263 "Failed to get PIO reg. write descriptor.\n");
268 desc = dmaengine_prep_slave_sg(ssp->dmach,
269 &dma_xfer[sg_count].sg, 1,
270 write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
271 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
275 "Failed to get DMA data write descriptor.\n");
282 * The last descriptor must have this callback,
283 * to finish the DMA transaction.
285 desc->callback = mxs_ssp_dma_irq_callback;
286 desc->callback_param = spi;
288 /* Start the transfer. */
289 dmaengine_submit(desc);
290 dma_async_issue_pending(ssp->dmach);
292 ret = wait_for_completion_timeout(&spi->c,
293 msecs_to_jiffies(SSP_TIMEOUT));
295 dev_err(ssp->dev, "DMA transfer timeout\n");
297 dmaengine_terminate_all(ssp->dmach);
304 while (--sg_count >= 0) {
306 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
307 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
315 static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
316 unsigned char *buf, int len,
317 int *first, int *last, int write)
319 struct mxs_ssp *ssp = &spi->ssp;
322 writel(BM_SSP_CTRL0_IGNORE_CRC,
323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
325 mxs_spi_set_cs(spi, cs);
328 if (*last && len == 0)
329 writel(BM_SSP_CTRL0_IGNORE_CRC,
330 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
332 if (ssp->devid == IMX23_SSP) {
333 writel(BM_SSP_CTRL0_XFER_COUNT,
334 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
336 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
338 writel(1, ssp->base + HW_SSP_XFER_SIZE);
342 writel(BM_SSP_CTRL0_READ,
343 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
345 writel(BM_SSP_CTRL0_READ,
346 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
348 writel(BM_SSP_CTRL0_RUN,
349 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
351 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
355 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
357 writel(BM_SSP_CTRL0_DATA_XFER,
358 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
361 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
362 BM_SSP_STATUS_FIFO_EMPTY, 0))
365 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
368 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
380 static int mxs_spi_transfer_one(struct spi_master *master,
381 struct spi_message *m)
383 struct mxs_spi *spi = spi_master_get_devdata(master);
384 struct mxs_ssp *ssp = &spi->ssp;
386 struct spi_transfer *t, *tmp_t;
392 cs = m->spi->chip_select;
394 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
396 status = mxs_spi_setup_transfer(m->spi, t);
400 if (&t->transfer_list == m->transfers.next)
402 if (&t->transfer_list == m->transfers.prev)
404 if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
406 "Cannot send and receive simultaneously\n");
412 * Small blocks can be transfered via PIO.
413 * Measured by empiric means:
415 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
417 * DMA only: 2.164808 seconds, 473.0KB/s
418 * Combined: 1.676276 seconds, 610.9KB/s
421 writel(BM_SSP_CTRL1_DMA_ENABLE,
422 ssp->base + HW_SSP_CTRL1(ssp) +
423 STMP_OFFSET_REG_CLR);
426 status = mxs_spi_txrx_pio(spi, cs,
428 t->len, &first, &last, 1);
430 status = mxs_spi_txrx_pio(spi, cs,
434 writel(BM_SSP_CTRL1_DMA_ENABLE,
435 ssp->base + HW_SSP_CTRL1(ssp) +
436 STMP_OFFSET_REG_SET);
439 status = mxs_spi_txrx_dma(spi, cs,
440 (void *)t->tx_buf, t->len,
443 status = mxs_spi_txrx_dma(spi, cs,
449 stmp_reset_block(ssp->base);
453 m->actual_length += t->len;
458 spi_finalize_current_message(master);
463 static const struct of_device_id mxs_spi_dt_ids[] = {
464 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
465 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
468 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
470 static int mxs_spi_probe(struct platform_device *pdev)
472 const struct of_device_id *of_id =
473 of_match_device(mxs_spi_dt_ids, &pdev->dev);
474 struct device_node *np = pdev->dev.of_node;
475 struct spi_master *master;
478 struct resource *iores;
482 int ret = 0, irq_err;
485 * Default clock speed for the SPI core. 160MHz seems to
486 * work reasonably well with most SPI flashes, so use this
487 * as a default. Override with "clock-frequency" DT prop.
489 const int clk_freq_default = 160000000;
491 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
492 irq_err = platform_get_irq(pdev, 0);
496 base = devm_ioremap_resource(&pdev->dev, iores);
498 return PTR_ERR(base);
500 clk = devm_clk_get(&pdev->dev, NULL);
504 devid = (enum mxs_ssp_id) of_id->data;
505 ret = of_property_read_u32(np, "clock-frequency",
508 clk_freq = clk_freq_default;
510 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
514 master->transfer_one_message = mxs_spi_transfer_one;
515 master->setup = mxs_spi_setup;
516 master->bits_per_word_mask = SPI_BPW_MASK(8);
517 master->mode_bits = SPI_CPOL | SPI_CPHA;
518 master->num_chipselect = 3;
519 master->dev.of_node = np;
520 master->flags = SPI_MASTER_HALF_DUPLEX;
522 spi = spi_master_get_devdata(master);
524 ssp->dev = &pdev->dev;
529 init_completion(&spi->c);
531 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
534 goto out_master_free;
536 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
538 dev_err(ssp->dev, "Failed to request DMA\n");
540 goto out_master_free;
543 ret = clk_prepare_enable(ssp->clk);
545 goto out_dma_release;
547 clk_set_rate(ssp->clk, clk_freq);
548 ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
550 ret = stmp_reset_block(ssp->base);
552 goto out_disable_clk;
554 platform_set_drvdata(pdev, master);
556 ret = spi_register_master(master);
558 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
559 goto out_disable_clk;
565 clk_disable_unprepare(ssp->clk);
567 dma_release_channel(ssp->dmach);
569 spi_master_put(master);
573 static int mxs_spi_remove(struct platform_device *pdev)
575 struct spi_master *master;
579 master = spi_master_get(platform_get_drvdata(pdev));
580 spi = spi_master_get_devdata(master);
583 spi_unregister_master(master);
584 clk_disable_unprepare(ssp->clk);
585 dma_release_channel(ssp->dmach);
586 spi_master_put(master);
591 static struct platform_driver mxs_spi_driver = {
592 .probe = mxs_spi_probe,
593 .remove = mxs_spi_remove,
596 .owner = THIS_MODULE,
597 .of_match_table = mxs_spi_dt_ids,
601 module_platform_driver(mxs_spi_driver);
603 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
604 MODULE_DESCRIPTION("MXS SPI master driver");
605 MODULE_LICENSE("GPL");
606 MODULE_ALIAS("platform:mxs-spi");