2 * Freescale MXS SPI master driver
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
34 #include <linux/of_device.h>
35 #include <linux/of_gpio.h>
36 #include <linux/platform_device.h>
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/highmem.h>
42 #include <linux/clk.h>
43 #include <linux/err.h>
44 #include <linux/completion.h>
45 #include <linux/gpio.h>
46 #include <linux/regulator/consumer.h>
47 #include <linux/module.h>
48 #include <linux/stmp_device.h>
49 #include <linux/spi/spi.h>
50 #include <linux/spi/mxs-spi.h>
52 #define DRIVER_NAME "mxs-spi"
54 /* Use 10S timeout for very long transfers, it should suffice. */
55 #define SSP_TIMEOUT 10000
57 #define SG_MAXLEN 0xff00
60 * Flags for txrx functions. More efficient that using an argument register for
63 #define TXRX_WRITE (1<<0) /* This is a write */
64 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
69 unsigned int sck; /* Rate requested (vs actual) */
72 static int mxs_spi_setup_transfer(struct spi_device *dev,
73 const struct spi_transfer *t)
75 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
76 struct mxs_ssp *ssp = &spi->ssp;
77 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
80 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
85 mxs_ssp_set_clk_rate(ssp, hz);
87 * Save requested rate, hz, rather than the actual rate,
88 * ssp->clk_rate. Otherwise we would set the rate every transfer
89 * when the actual rate is not quite the same as requested rate.
93 * Perhaps we should return an error if the actual clock is
94 * nowhere close to what was requested?
98 writel(BM_SSP_CTRL0_LOCK_CS,
99 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
101 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
102 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
103 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
104 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
105 ssp->base + HW_SSP_CTRL1(ssp));
107 writel(0x0, ssp->base + HW_SSP_CMD0);
108 writel(0x0, ssp->base + HW_SSP_CMD1);
113 static u32 mxs_spi_cs_to_reg(unsigned cs)
118 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
120 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
121 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
122 * the datasheet for further details. In SPI mode, they are used to
123 * toggle the chip-select lines (nCS pins).
126 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
128 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
133 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
135 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
136 struct mxs_ssp *ssp = &spi->ssp;
140 reg = readl_relaxed(ssp->base + offset);
149 } while (time_before(jiffies, timeout));
154 static void mxs_ssp_dma_irq_callback(void *param)
156 struct mxs_spi *spi = param;
161 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
163 struct mxs_ssp *ssp = dev_id;
165 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
167 readl(ssp->base + HW_SSP_CTRL1(ssp)),
168 readl(ssp->base + HW_SSP_STATUS(ssp)));
172 static int mxs_spi_txrx_dma(struct mxs_spi *spi,
173 unsigned char *buf, int len,
176 struct mxs_ssp *ssp = &spi->ssp;
177 struct dma_async_tx_descriptor *desc = NULL;
178 const bool vmalloced_buf = is_vmalloc_addr(buf);
179 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
180 const int sgs = DIV_ROUND_UP(len, desc_len);
184 struct page *vm_page;
187 struct scatterlist sg;
193 dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
197 reinit_completion(&spi->c);
199 /* Chip select was already programmed into CTRL0 */
200 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
201 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
203 ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
205 if (!(flags & TXRX_WRITE))
206 ctrl0 |= BM_SSP_CTRL0_READ;
208 /* Queue the DMA data transfer. */
209 for (sg_count = 0; sg_count < sgs; sg_count++) {
210 /* Prepare the transfer descriptor. */
211 min = min(len, desc_len);
214 * De-assert CS on last segment if flag is set (i.e., no more
215 * transfers will follow)
217 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
218 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
220 if (ssp->devid == IMX23_SSP) {
221 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
225 dma_xfer[sg_count].pio[0] = ctrl0;
226 dma_xfer[sg_count].pio[3] = min;
229 vm_page = vmalloc_to_page(buf);
235 sg_init_table(&dma_xfer[sg_count].sg, 1);
236 sg_set_page(&dma_xfer[sg_count].sg, vm_page,
237 min, offset_in_page(buf));
239 sg_init_one(&dma_xfer[sg_count].sg, buf, min);
242 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
243 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
248 /* Queue the PIO register write transfer. */
249 desc = dmaengine_prep_slave_sg(ssp->dmach,
250 (struct scatterlist *)dma_xfer[sg_count].pio,
251 (ssp->devid == IMX23_SSP) ? 1 : 4,
253 sg_count ? DMA_PREP_INTERRUPT : 0);
256 "Failed to get PIO reg. write descriptor.\n");
261 desc = dmaengine_prep_slave_sg(ssp->dmach,
262 &dma_xfer[sg_count].sg, 1,
263 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
264 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
268 "Failed to get DMA data write descriptor.\n");
275 * The last descriptor must have this callback,
276 * to finish the DMA transaction.
278 desc->callback = mxs_ssp_dma_irq_callback;
279 desc->callback_param = spi;
281 /* Start the transfer. */
282 dmaengine_submit(desc);
283 dma_async_issue_pending(ssp->dmach);
285 ret = wait_for_completion_timeout(&spi->c,
286 msecs_to_jiffies(SSP_TIMEOUT));
288 dev_err(ssp->dev, "DMA transfer timeout\n");
290 dmaengine_terminate_all(ssp->dmach);
297 while (--sg_count >= 0) {
299 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
300 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
308 static int mxs_spi_txrx_pio(struct mxs_spi *spi,
309 unsigned char *buf, int len,
312 struct mxs_ssp *ssp = &spi->ssp;
314 writel(BM_SSP_CTRL0_IGNORE_CRC,
315 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
318 if (len == 0 && (flags & TXRX_DEASSERT_CS))
319 writel(BM_SSP_CTRL0_IGNORE_CRC,
320 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
322 if (ssp->devid == IMX23_SSP) {
323 writel(BM_SSP_CTRL0_XFER_COUNT,
324 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
328 writel(1, ssp->base + HW_SSP_XFER_SIZE);
331 if (flags & TXRX_WRITE)
332 writel(BM_SSP_CTRL0_READ,
333 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
335 writel(BM_SSP_CTRL0_READ,
336 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
338 writel(BM_SSP_CTRL0_RUN,
339 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
341 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
344 if (flags & TXRX_WRITE)
345 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
347 writel(BM_SSP_CTRL0_DATA_XFER,
348 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
350 if (!(flags & TXRX_WRITE)) {
351 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
352 BM_SSP_STATUS_FIFO_EMPTY, 0))
355 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
358 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
370 static int mxs_spi_transfer_one(struct spi_master *master,
371 struct spi_message *m)
373 struct mxs_spi *spi = spi_master_get_devdata(master);
374 struct mxs_ssp *ssp = &spi->ssp;
375 struct spi_transfer *t;
379 /* Program CS register bits here, it will be used for all transfers. */
380 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
381 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
382 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
383 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
385 list_for_each_entry(t, &m->transfers, transfer_list) {
387 status = mxs_spi_setup_transfer(m->spi, t);
391 /* De-assert on last transfer, inverted by cs_change flag */
392 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
393 TXRX_DEASSERT_CS : 0;
396 * Small blocks can be transfered via PIO.
397 * Measured by empiric means:
399 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
401 * DMA only: 2.164808 seconds, 473.0KB/s
402 * Combined: 1.676276 seconds, 610.9KB/s
405 writel(BM_SSP_CTRL1_DMA_ENABLE,
406 ssp->base + HW_SSP_CTRL1(ssp) +
407 STMP_OFFSET_REG_CLR);
410 status = mxs_spi_txrx_pio(spi,
412 t->len, flag | TXRX_WRITE);
414 status = mxs_spi_txrx_pio(spi,
418 writel(BM_SSP_CTRL1_DMA_ENABLE,
419 ssp->base + HW_SSP_CTRL1(ssp) +
420 STMP_OFFSET_REG_SET);
423 status = mxs_spi_txrx_dma(spi,
424 (void *)t->tx_buf, t->len,
427 status = mxs_spi_txrx_dma(spi,
433 stmp_reset_block(ssp->base);
437 m->actual_length += t->len;
441 spi_finalize_current_message(master);
446 static const struct of_device_id mxs_spi_dt_ids[] = {
447 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
448 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
451 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
453 static int mxs_spi_probe(struct platform_device *pdev)
455 const struct of_device_id *of_id =
456 of_match_device(mxs_spi_dt_ids, &pdev->dev);
457 struct device_node *np = pdev->dev.of_node;
458 struct spi_master *master;
461 struct resource *iores;
465 int ret = 0, irq_err;
468 * Default clock speed for the SPI core. 160MHz seems to
469 * work reasonably well with most SPI flashes, so use this
470 * as a default. Override with "clock-frequency" DT prop.
472 const int clk_freq_default = 160000000;
474 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 irq_err = platform_get_irq(pdev, 0);
479 base = devm_ioremap_resource(&pdev->dev, iores);
481 return PTR_ERR(base);
483 clk = devm_clk_get(&pdev->dev, NULL);
487 devid = (enum mxs_ssp_id) of_id->data;
488 ret = of_property_read_u32(np, "clock-frequency",
491 clk_freq = clk_freq_default;
493 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
497 master->transfer_one_message = mxs_spi_transfer_one;
498 master->bits_per_word_mask = SPI_BPW_MASK(8);
499 master->mode_bits = SPI_CPOL | SPI_CPHA;
500 master->num_chipselect = 3;
501 master->dev.of_node = np;
502 master->flags = SPI_MASTER_HALF_DUPLEX;
504 spi = spi_master_get_devdata(master);
506 ssp->dev = &pdev->dev;
511 init_completion(&spi->c);
513 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
514 dev_name(&pdev->dev), ssp);
516 goto out_master_free;
518 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
520 dev_err(ssp->dev, "Failed to request DMA\n");
522 goto out_master_free;
525 ret = clk_prepare_enable(ssp->clk);
527 goto out_dma_release;
529 clk_set_rate(ssp->clk, clk_freq);
531 ret = stmp_reset_block(ssp->base);
533 goto out_disable_clk;
535 platform_set_drvdata(pdev, master);
537 ret = devm_spi_register_master(&pdev->dev, master);
539 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
540 goto out_disable_clk;
546 clk_disable_unprepare(ssp->clk);
548 dma_release_channel(ssp->dmach);
550 spi_master_put(master);
554 static int mxs_spi_remove(struct platform_device *pdev)
556 struct spi_master *master;
560 master = platform_get_drvdata(pdev);
561 spi = spi_master_get_devdata(master);
564 clk_disable_unprepare(ssp->clk);
565 dma_release_channel(ssp->dmach);
570 static struct platform_driver mxs_spi_driver = {
571 .probe = mxs_spi_probe,
572 .remove = mxs_spi_remove,
575 .of_match_table = mxs_spi_dt_ids,
579 module_platform_driver(mxs_spi_driver);
581 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
582 MODULE_DESCRIPTION("MXS SPI master driver");
583 MODULE_LICENSE("GPL");
584 MODULE_ALIAS("platform:mxs-spi");