2 * OMAP7xx SPI 100k controller driver
3 * Author: Fabrice Crohas <fcrohas@gmail.com>
4 * from original omap1_mcspi driver
6 * Copyright (C) 2005, 2006 Nokia Corporation
7 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
8 * Juha Yrj�l� <juha.yrjola@nokia.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/module.h>
29 #include <linux/device.h>
30 #include <linux/delay.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/slab.h>
38 #include <linux/spi/spi.h>
40 #define OMAP1_SPI100K_MAX_FREQ 48000000
42 #define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12)
44 #define SPI_SETUP1 0x00
45 #define SPI_SETUP2 0x02
47 #define SPI_STATUS 0x06
48 #define SPI_TX_LSB 0x08
49 #define SPI_TX_MSB 0x0a
50 #define SPI_RX_LSB 0x0c
51 #define SPI_RX_MSB 0x0e
53 #define SPI_SETUP1_INT_READ_ENABLE (1UL << 5)
54 #define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4)
55 #define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1)
56 #define SPI_SETUP1_CLOCK_ENABLE (1UL << 0)
58 #define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0)
59 #define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0)
60 #define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5)
61 #define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5)
62 #define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10)
63 #define SPI_SETUP2_EDGE_TRIGGER (1UL << 10)
65 #define SPI_CTRL_SEN(x) ((x) << 7)
66 #define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2)
67 #define SPI_CTRL_WR (1UL << 1)
68 #define SPI_CTRL_RD (1UL << 0)
70 #define SPI_STATUS_WE (1UL << 1)
71 #define SPI_STATUS_RD (1UL << 0)
73 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
74 * cache operations; better heuristics consider wordsize and bitrate.
76 #define DMA_MIN_BYTES 8
79 #define SPI_SHUTDOWN 1
81 struct omap1_spi100k {
85 /* Virtual base address of the controller */
89 struct omap1_spi100k_cs {
94 static void spi100k_enable_clock(struct spi_master *master)
97 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
100 val = readw(spi100k->base + SPI_SETUP1);
101 val |= SPI_SETUP1_CLOCK_ENABLE;
102 writew(val, spi100k->base + SPI_SETUP1);
105 static void spi100k_disable_clock(struct spi_master *master)
108 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
111 val = readw(spi100k->base + SPI_SETUP1);
112 val &= ~SPI_SETUP1_CLOCK_ENABLE;
113 writew(val, spi100k->base + SPI_SETUP1);
116 static void spi100k_write_data(struct spi_master *master, int len, int data)
118 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
120 /* write 16-bit word, shifting 8-bit data if necessary */
126 spi100k_enable_clock(master);
127 writew(data , spi100k->base + SPI_TX_MSB);
129 writew(SPI_CTRL_SEN(0) |
130 SPI_CTRL_WORD_SIZE(len) |
132 spi100k->base + SPI_CTRL);
134 /* Wait for bit ack send change */
135 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE)
139 spi100k_disable_clock(master);
142 static int spi100k_read_data(struct spi_master *master, int len)
145 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
147 /* Always do at least 16 bits */
151 spi100k_enable_clock(master);
152 writew(SPI_CTRL_SEN(0) |
153 SPI_CTRL_WORD_SIZE(len) |
155 spi100k->base + SPI_CTRL);
157 while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD)
161 dataL = readw(spi100k->base + SPI_RX_LSB);
162 dataH = readw(spi100k->base + SPI_RX_MSB);
163 spi100k_disable_clock(master);
168 static void spi100k_open(struct spi_master *master)
170 /* get control of SPI */
171 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
173 writew(SPI_SETUP1_INT_READ_ENABLE |
174 SPI_SETUP1_INT_WRITE_ENABLE |
175 SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
177 /* configure clock and interrupts */
178 writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
179 SPI_SETUP2_NEGATIVE_LEVEL |
180 SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
183 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
186 writew(0x05fc, spi100k->base + SPI_CTRL);
188 writew(0x05fd, spi100k->base + SPI_CTRL);
192 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
194 struct omap1_spi100k_cs *cs = spi->controller_state;
195 unsigned int count, c;
200 word_len = cs->word_len;
210 if (xfer->tx_buf != NULL)
211 spi100k_write_data(spi->master, word_len, *tx++);
212 if (xfer->rx_buf != NULL)
213 *rx++ = spi100k_read_data(spi->master, word_len);
215 } else if (word_len <= 16) {
223 if (xfer->tx_buf != NULL)
224 spi100k_write_data(spi->master, word_len, *tx++);
225 if (xfer->rx_buf != NULL)
226 *rx++ = spi100k_read_data(spi->master, word_len);
228 } else if (word_len <= 32) {
236 if (xfer->tx_buf != NULL)
237 spi100k_write_data(spi->master, word_len, *tx);
238 if (xfer->rx_buf != NULL)
239 *rx = spi100k_read_data(spi->master, word_len);
245 /* called only when no transfer is active to this device */
246 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
247 struct spi_transfer *t)
249 struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
250 struct omap1_spi100k_cs *cs = spi->controller_state;
251 u8 word_len = spi->bits_per_word;
253 if (t != NULL && t->bits_per_word)
254 word_len = t->bits_per_word;
258 if (spi->bits_per_word > 32)
260 cs->word_len = word_len;
262 /* SPI init before transfer */
263 writew(0x3e , spi100k->base + SPI_SETUP1);
264 writew(0x00 , spi100k->base + SPI_STATUS);
265 writew(0x3e , spi100k->base + SPI_CTRL);
270 /* the spi->mode bits understood by this driver: */
271 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
273 static int omap1_spi100k_setup(struct spi_device *spi)
276 struct omap1_spi100k *spi100k;
277 struct omap1_spi100k_cs *cs = spi->controller_state;
279 spi100k = spi_master_get_devdata(spi->master);
282 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
285 cs->base = spi100k->base + spi->chip_select * 0x14;
286 spi->controller_state = cs;
289 spi100k_open(spi->master);
291 clk_prepare_enable(spi100k->ick);
292 clk_prepare_enable(spi100k->fck);
294 ret = omap1_spi100k_setup_transfer(spi, NULL);
296 clk_disable_unprepare(spi100k->ick);
297 clk_disable_unprepare(spi100k->fck);
302 static int omap1_spi100k_prepare_hardware(struct spi_master *master)
304 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
306 clk_prepare_enable(spi100k->ick);
307 clk_prepare_enable(spi100k->fck);
312 static int omap1_spi100k_transfer_one_message(struct spi_master *master,
313 struct spi_message *m)
315 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
316 struct spi_device *spi = m->spi;
317 struct spi_transfer *t = NULL;
319 int par_override = 0;
322 list_for_each_entry(t, &m->transfers, transfer_list) {
323 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
327 if (par_override || t->speed_hz || t->bits_per_word) {
329 status = omap1_spi100k_setup_transfer(spi, t);
332 if (!t->speed_hz && !t->bits_per_word)
337 omap1_spi100k_force_cs(spi100k, 1);
344 count = omap1_spi100k_txrx_pio(spi, t);
345 m->actual_length += count;
347 if (count != t->len) {
354 udelay(t->delay_usecs);
356 /* ignore the "leave it on after last xfer" hint */
359 omap1_spi100k_force_cs(spi100k, 0);
364 /* Restore defaults if they were overriden */
367 status = omap1_spi100k_setup_transfer(spi, NULL);
371 omap1_spi100k_force_cs(spi100k, 0);
375 spi_finalize_current_message(master);
380 static int omap1_spi100k_unprepare_hardware(struct spi_master *master)
382 struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
384 clk_disable_unprepare(spi100k->ick);
385 clk_disable_unprepare(spi100k->fck);
390 static int omap1_spi100k_probe(struct platform_device *pdev)
392 struct spi_master *master;
393 struct omap1_spi100k *spi100k;
399 master = spi_alloc_master(&pdev->dev, sizeof(*spi100k));
400 if (master == NULL) {
401 dev_dbg(&pdev->dev, "master allocation failed\n");
406 master->bus_num = pdev->id;
408 master->setup = omap1_spi100k_setup;
409 master->transfer_one_message = omap1_spi100k_transfer_one_message;
410 master->prepare_transfer_hardware = omap1_spi100k_prepare_hardware;
411 master->unprepare_transfer_hardware = omap1_spi100k_unprepare_hardware;
412 master->cleanup = NULL;
413 master->num_chipselect = 2;
414 master->mode_bits = MODEBITS;
415 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
416 master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16);
417 master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ;
419 spi100k = spi_master_get_devdata(master);
422 * The memory region base address is taken as the platform_data.
423 * You should allocate this with ioremap() before initializing
426 spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev);
428 spi100k->ick = devm_clk_get(&pdev->dev, "ick");
429 if (IS_ERR(spi100k->ick)) {
430 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
431 status = PTR_ERR(spi100k->ick);
435 spi100k->fck = devm_clk_get(&pdev->dev, "fck");
436 if (IS_ERR(spi100k->fck)) {
437 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
438 status = PTR_ERR(spi100k->fck);
442 status = devm_spi_register_master(&pdev->dev, master);
449 spi_master_put(master);
453 static struct platform_driver omap1_spi100k_driver = {
455 .name = "omap1_spi100k",
456 .owner = THIS_MODULE,
458 .probe = omap1_spi100k_probe,
461 module_platform_driver(omap1_spi100k_driver);
463 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
464 MODULE_AUTHOR("Fabrice Crohas <fcrohas@gmail.com>");
465 MODULE_LICENSE("GPL");