drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/omap-dma.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41
  42 #include <linux/spi/spi.h>
  43
  44 #include <linux/platform_data/spi-omap2-mcspi.h>
  45
  46 #define OMAP2_MCSPI_MAX_FREQ            48000000
  47 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  48
  49 #define OMAP2_MCSPI_REVISION            0x00
  50 #define OMAP2_MCSPI_SYSSTATUS           0x14
  51 #define OMAP2_MCSPI_IRQSTATUS           0x18
  52 #define OMAP2_MCSPI_IRQENABLE           0x1c
  53 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  54 #define OMAP2_MCSPI_SYST                0x24
  55 #define OMAP2_MCSPI_MODULCTRL           0x28
  56
  57 /* per-channel banks, 0x14 bytes each, first is: */
  58 #define OMAP2_MCSPI_CHCONF0             0x2c
  59 #define OMAP2_MCSPI_CHSTAT0             0x30
  60 #define OMAP2_MCSPI_CHCTRL0             0x34
  61 #define OMAP2_MCSPI_TX0                 0x38
  62 #define OMAP2_MCSPI_RX0                 0x3c
  63
  64 /* per-register bitmasks: */
  65
  66 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  67 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  68 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  69
  70 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  71 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  72 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  73 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  74 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  75 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  76 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  77 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  78 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  79 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  80 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  81 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  82 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  83 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  84 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  85
  86 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  87 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  88 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  89
  90 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  91
  92 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
  93
  94 /* We have 2 DMA channels per CS, one for RX and one for TX */
  95 struct omap2_mcspi_dma {
  96         struct dma_chan *dma_tx;
  97         struct dma_chan *dma_rx;
  98
  99         int dma_tx_sync_dev;
 100         int dma_rx_sync_dev;
 101
 102         struct completion dma_tx_completion;
 103         struct completion dma_rx_completion;
 104 };
 105
 106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 107  * cache operations; better heuristics consider wordsize and bitrate.
 108  */
 109 #define DMA_MIN_BYTES                   160
 110
 111
 112 /*
 113  * Used for context save and restore, structure members to be updated whenever
 114  * corresponding registers are modified.
 115  */
 116 struct omap2_mcspi_regs {
 117         u32 modulctrl;
 118         u32 wakeupenable;
 119         struct list_head cs;
 120 };
 121
 122 struct omap2_mcspi {
 123         struct spi_master       *master;
 124         /* Virtual base address of the controller */
 125         void __iomem            *base;
 126         unsigned long           phys;
 127         /* SPI1 has 4 channels, while SPI2 has 2 */
 128         struct omap2_mcspi_dma  *dma_channels;
 129         struct device           *dev;
 130         struct omap2_mcspi_regs ctx;
 131         unsigned int            pin_dir:1;
 132 };
 133
 134 struct omap2_mcspi_cs {
 135         void __iomem            *base;
 136         unsigned long           phys;
 137         int                     word_len;
 138         struct list_head        node;
 139         /* Context save and restore shadow register */
 140         u32                     chconf0;
 141 };
 142
 143 static inline void mcspi_write_reg(struct spi_master *master,
 144                 int idx, u32 val)
 145 {
 146         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 147
 148         __raw_writel(val, mcspi->base + idx);
 149 }
 150
 151 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 152 {
 153         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 154
 155         return __raw_readl(mcspi->base + idx);
 156 }
 157
 158 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 159                 int idx, u32 val)
 160 {
 161         struct omap2_mcspi_cs   *cs = spi->controller_state;
 162
 163         __raw_writel(val, cs->base +  idx);
 164 }
 165
 166 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 167 {
 168         struct omap2_mcspi_cs   *cs = spi->controller_state;
 169
 170         return __raw_readl(cs->base + idx);
 171 }
 172
 173 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 174 {
 175         struct omap2_mcspi_cs *cs = spi->controller_state;
 176
 177         return cs->chconf0;
 178 }
 179
 180 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 181 {
 182         struct omap2_mcspi_cs *cs = spi->controller_state;
 183
 184         cs->chconf0 = val;
 185         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 186         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 187 }
 188
 189 static inline int mcspi_bytes_per_word(int word_len)
 190 {
 191         if (word_len <= 8)
 192                 return 1;
 193         else if (word_len <= 16)
 194                 return 2;
 195         else /* word_len <= 32 */
 196                 return 4;
 197 }
 198
 199 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 200                 int is_read, int enable)
 201 {
 202         u32 l, rw;
 203
 204         l = mcspi_cached_chconf0(spi);
 205
 206         if (is_read) /* 1 is read, 0 write */
 207                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 208         else
 209                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 210
 211         if (enable)
 212                 l |= rw;
 213         else
 214                 l &= ~rw;
 215
 216         mcspi_write_chconf0(spi, l);
 217 }
 218
 219 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 220 {
 221         u32 l;
 222
 223         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 224         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 225         /* Flash post-writes */
 226         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 227 }
 228
 229 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 230 {
 231         u32 l;
 232
 233         l = mcspi_cached_chconf0(spi);
 234         if (cs_active)
 235                 l |= OMAP2_MCSPI_CHCONF_FORCE;
 236         else
 237                 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 238
 239         mcspi_write_chconf0(spi, l);
 240 }
 241
 242 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 243 {
 244         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 245         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 246         u32 l;
 247
 248         /*
 249          * Setup when switching from (reset default) slave mode
 250          * to single-channel master mode
 251          */
 252         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 253         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 254         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 255         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 256
 257         ctx->modulctrl = l;
 258 }
 259
 260 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 261 {
 262         struct spi_master       *spi_cntrl = mcspi->master;
 263         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 264         struct omap2_mcspi_cs   *cs;
 265
 266         /* McSPI: context restore */
 267         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 268         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 269
 270         list_for_each_entry(cs, &ctx->cs, node)
 271                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 272 }
 273
 274 static int omap2_prepare_transfer(struct spi_master *master)
 275 {
 276         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 277
 278         pm_runtime_get_sync(mcspi->dev);
 279         return 0;
 280 }
 281
 282 static int omap2_unprepare_transfer(struct spi_master *master)
 283 {
 284         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 285
 286         pm_runtime_mark_last_busy(mcspi->dev);
 287         pm_runtime_put_autosuspend(mcspi->dev);
 288         return 0;
 289 }
 290
 291 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 292 {
 293         unsigned long timeout;
 294
 295         timeout = jiffies + msecs_to_jiffies(1000);
 296         while (!(__raw_readl(reg) & bit)) {
 297                 if (time_after(jiffies, timeout)) {
 298                         if (!(__raw_readl(reg) & bit))
 299                                 return -ETIMEDOUT;
 300                         else
 301                                 return 0;
 302                 }
 303                 cpu_relax();
 304         }
 305         return 0;
 306 }
 307
 308 static void omap2_mcspi_rx_callback(void *data)
 309 {
 310         struct spi_device *spi = data;
 311         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 312         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 313
 314         /* We must disable the DMA RX request */
 315         omap2_mcspi_set_dma_req(spi, 1, 0);
 316
 317         complete(&mcspi_dma->dma_rx_completion);
 318 }
 319
 320 static void omap2_mcspi_tx_callback(void *data)
 321 {
 322         struct spi_device *spi = data;
 323         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 324         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 325
 326         /* We must disable the DMA TX request */
 327         omap2_mcspi_set_dma_req(spi, 0, 0);
 328
 329         complete(&mcspi_dma->dma_tx_completion);
 330 }
 331
 332 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 333                                 struct spi_transfer *xfer,
 334                                 struct dma_slave_config cfg)
 335 {
 336         struct omap2_mcspi      *mcspi;
 337         struct omap2_mcspi_dma  *mcspi_dma;
 338         unsigned int            count;
 339
 340         mcspi = spi_master_get_devdata(spi->master);
 341         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 342         count = xfer->len;
 343
 344         if (mcspi_dma->dma_tx) {
 345                 struct dma_async_tx_descriptor *tx;
 346                 struct scatterlist sg;
 347
 348                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 349
 350                 sg_init_table(&sg, 1);
 351                 sg_dma_address(&sg) = xfer->tx_dma;
 352                 sg_dma_len(&sg) = xfer->len;
 353
 354                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 355                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 356                 if (tx) {
 357                         tx->callback = omap2_mcspi_tx_callback;
 358                         tx->callback_param = spi;
 359                         dmaengine_submit(tx);
 360                 } else {
 361                         /* FIXME: fall back to PIO? */
 362                 }
 363         }
 364         dma_async_issue_pending(mcspi_dma->dma_tx);
 365         omap2_mcspi_set_dma_req(spi, 0, 1);
 366
 367 }
 368
 369 static unsigned
 370 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 371                                 struct dma_slave_config cfg,
 372                                 unsigned es)
 373 {
 374         struct omap2_mcspi      *mcspi;
 375         struct omap2_mcspi_dma  *mcspi_dma;
 376         unsigned int            count;
 377         u32                     l;
 378         int                     elements = 0;
 379         int                     word_len, element_count;
 380         struct omap2_mcspi_cs   *cs = spi->controller_state;
 381         mcspi = spi_master_get_devdata(spi->master);
 382         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 383         count = xfer->len;
 384         word_len = cs->word_len;
 385         l = mcspi_cached_chconf0(spi);
 386
 387         if (word_len <= 8)
 388                 element_count = count;
 389         else if (word_len <= 16)
 390                 element_count = count >> 1;
 391         else /* word_len <= 32 */
 392                 element_count = count >> 2;
 393
 394         if (mcspi_dma->dma_rx) {
 395                 struct dma_async_tx_descriptor *tx;
 396                 struct scatterlist sg;
 397                 size_t len = xfer->len - es;
 398
 399                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 400
 401                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
 402                         len -= es;
 403
 404                 sg_init_table(&sg, 1);
 405                 sg_dma_address(&sg) = xfer->rx_dma;
 406                 sg_dma_len(&sg) = len;
 407
 408                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 409                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 410                                 DMA_CTRL_ACK);
 411                 if (tx) {
 412                         tx->callback = omap2_mcspi_rx_callback;
 413                         tx->callback_param = spi;
 414                         dmaengine_submit(tx);
 415                 } else {
 416                                 /* FIXME: fall back to PIO? */
 417                 }
 418         }
 419
 420         dma_async_issue_pending(mcspi_dma->dma_rx);
 421         omap2_mcspi_set_dma_req(spi, 1, 1);
 422
 423         wait_for_completion(&mcspi_dma->dma_rx_completion);
 424         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 425                          DMA_FROM_DEVICE);
 426         omap2_mcspi_set_enable(spi, 0);
 427
 428         elements = element_count - 1;
 429
 430         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 431                 elements--;
 432
 433                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 434                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 435                         u32 w;
 436
 437                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 438                         if (word_len <= 8)
 439                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 440                         else if (word_len <= 16)
 441                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 442                         else /* word_len <= 32 */
 443                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 444                 } else {
 445                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 446                         dev_err(&spi->dev, "DMA RX penultimate word empty");
 447                         count -= (bytes_per_word << 1);
 448                         omap2_mcspi_set_enable(spi, 1);
 449                         return count;
 450                 }
 451         }
 452         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 453                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 454                 u32 w;
 455
 456                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 457                 if (word_len <= 8)
 458                         ((u8 *)xfer->rx_buf)[elements] = w;
 459                 else if (word_len <= 16)
 460                         ((u16 *)xfer->rx_buf)[elements] = w;
 461                 else /* word_len <= 32 */
 462                         ((u32 *)xfer->rx_buf)[elements] = w;
 463         } else {
 464                 dev_err(&spi->dev, "DMA RX last word empty");
 465                 count -= mcspi_bytes_per_word(word_len);
 466         }
 467         omap2_mcspi_set_enable(spi, 1);
 468         return count;
 469 }
 470
 471 static unsigned
 472 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 473 {
 474         struct omap2_mcspi      *mcspi;
 475         struct omap2_mcspi_cs   *cs = spi->controller_state;
 476         struct omap2_mcspi_dma  *mcspi_dma;
 477         unsigned int            count;
 478         u32                     l;
 479         u8                      *rx;
 480         const u8                *tx;
 481         struct dma_slave_config cfg;
 482         enum dma_slave_buswidth width;
 483         unsigned es;
 484         void __iomem            *chstat_reg;
 485
 486         mcspi = spi_master_get_devdata(spi->master);
 487         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 488         l = mcspi_cached_chconf0(spi);
 489
 490
 491         if (cs->word_len <= 8) {
 492                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 493                 es = 1;
 494         } else if (cs->word_len <= 16) {
 495                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 496                 es = 2;
 497         } else {
 498                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 499                 es = 4;
 500         }
 501
 502         memset(&cfg, 0, sizeof(cfg));
 503         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 504         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 505         cfg.src_addr_width = width;
 506         cfg.dst_addr_width = width;
 507         cfg.src_maxburst = 1;
 508         cfg.dst_maxburst = 1;
 509
 510         rx = xfer->rx_buf;
 511         tx = xfer->tx_buf;
 512
 513         count = xfer->len;
 514
 515         if (tx != NULL)
 516                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 517
 518         if (rx != NULL)
 519                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 520
 521         if (tx != NULL) {
 522                 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 523                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 524                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 525                                  DMA_TO_DEVICE);
 526
 527                 /* for TX_ONLY mode, be sure all words have shifted out */
 528                 if (rx == NULL) {
 529                         if (mcspi_wait_for_reg_bit(chstat_reg,
 530                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0)
 531                                 dev_err(&spi->dev, "TXS timed out\n");
 532                         else if (mcspi_wait_for_reg_bit(chstat_reg,
 533                                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 534                                 dev_err(&spi->dev, "EOT timed out\n");
 535                 }
 536         }
 537         return count;
 538 }
 539
 540 static unsigned
 541 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 542 {
 543         struct omap2_mcspi      *mcspi;
 544         struct omap2_mcspi_cs   *cs = spi->controller_state;
 545         unsigned int            count, c;
 546         u32                     l;
 547         void __iomem            *base = cs->base;
 548         void __iomem            *tx_reg;
 549         void __iomem            *rx_reg;
 550         void __iomem            *chstat_reg;
 551         int                     word_len;
 552
 553         mcspi = spi_master_get_devdata(spi->master);
 554         count = xfer->len;
 555         c = count;
 556         word_len = cs->word_len;
 557
 558         l = mcspi_cached_chconf0(spi);
 559
 560         /* We store the pre-calculated register addresses on stack to speed
 561          * up the transfer loop. */
 562         tx_reg          = base + OMAP2_MCSPI_TX0;
 563         rx_reg          = base + OMAP2_MCSPI_RX0;
 564         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 565
 566         if (c < (word_len>>3))
 567                 return 0;
 568
 569         if (word_len <= 8) {
 570                 u8              *rx;
 571                 const u8        *tx;
 572
 573                 rx = xfer->rx_buf;
 574                 tx = xfer->tx_buf;
 575
 576                 do {
 577                         c -= 1;
 578                         if (tx != NULL) {
 579                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 580                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 581                                         dev_err(&spi->dev, "TXS timed out\n");
 582                                         goto out;
 583                                 }
 584                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 585                                                 word_len, *tx);
 586                                 __raw_writel(*tx++, tx_reg);
 587                         }
 588                         if (rx != NULL) {
 589                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 590                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 591                                         dev_err(&spi->dev, "RXS timed out\n");
 592                                         goto out;
 593                                 }
 594
 595                                 if (c == 1 && tx == NULL &&
 596                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 597                                         omap2_mcspi_set_enable(spi, 0);
 598                                         *rx++ = __raw_readl(rx_reg);
 599                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 600                                                     word_len, *(rx - 1));
 601                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 602                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 603                                                 dev_err(&spi->dev,
 604                                                         "RXS timed out\n");
 605                                                 goto out;
 606                                         }
 607                                         c = 0;
 608                                 } else if (c == 0 && tx == NULL) {
 609                                         omap2_mcspi_set_enable(spi, 0);
 610                                 }
 611
 612                                 *rx++ = __raw_readl(rx_reg);
 613                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 614                                                 word_len, *(rx - 1));
 615                         }
 616                 } while (c);
 617         } else if (word_len <= 16) {
 618                 u16             *rx;
 619                 const u16       *tx;
 620
 621                 rx = xfer->rx_buf;
 622                 tx = xfer->tx_buf;
 623                 do {
 624                         c -= 2;
 625                         if (tx != NULL) {
 626                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 627                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 628                                         dev_err(&spi->dev, "TXS timed out\n");
 629                                         goto out;
 630                                 }
 631                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 632                                                 word_len, *tx);
 633                                 __raw_writel(*tx++, tx_reg);
 634                         }
 635                         if (rx != NULL) {
 636                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 637                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 638                                         dev_err(&spi->dev, "RXS timed out\n");
 639                                         goto out;
 640                                 }
 641
 642                                 if (c == 2 && tx == NULL &&
 643                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 644                                         omap2_mcspi_set_enable(spi, 0);
 645                                         *rx++ = __raw_readl(rx_reg);
 646                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 647                                                     word_len, *(rx - 1));
 648                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 649                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 650                                                 dev_err(&spi->dev,
 651                                                         "RXS timed out\n");
 652                                                 goto out;
 653                                         }
 654                                         c = 0;
 655                                 } else if (c == 0 && tx == NULL) {
 656                                         omap2_mcspi_set_enable(spi, 0);
 657                                 }
 658
 659                                 *rx++ = __raw_readl(rx_reg);
 660                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 661                                                 word_len, *(rx - 1));
 662                         }
 663                 } while (c >= 2);
 664         } else if (word_len <= 32) {
 665                 u32             *rx;
 666                 const u32       *tx;
 667
 668                 rx = xfer->rx_buf;
 669                 tx = xfer->tx_buf;
 670                 do {
 671                         c -= 4;
 672                         if (tx != NULL) {
 673                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 674                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 675                                         dev_err(&spi->dev, "TXS timed out\n");
 676                                         goto out;
 677                                 }
 678                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 679                                                 word_len, *tx);
 680                                 __raw_writel(*tx++, tx_reg);
 681                         }
 682                         if (rx != NULL) {
 683                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 684                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 685                                         dev_err(&spi->dev, "RXS timed out\n");
 686                                         goto out;
 687                                 }
 688
 689                                 if (c == 4 && tx == NULL &&
 690                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 691                                         omap2_mcspi_set_enable(spi, 0);
 692                                         *rx++ = __raw_readl(rx_reg);
 693                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 694                                                     word_len, *(rx - 1));
 695                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 696                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 697                                                 dev_err(&spi->dev,
 698                                                         "RXS timed out\n");
 699                                                 goto out;
 700                                         }
 701                                         c = 0;
 702                                 } else if (c == 0 && tx == NULL) {
 703                                         omap2_mcspi_set_enable(spi, 0);
 704                                 }
 705
 706                                 *rx++ = __raw_readl(rx_reg);
 707                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 708                                                 word_len, *(rx - 1));
 709                         }
 710                 } while (c >= 4);
 711         }
 712
 713         /* for TX_ONLY mode, be sure all words have shifted out */
 714         if (xfer->rx_buf == NULL) {
 715                 if (mcspi_wait_for_reg_bit(chstat_reg,
 716                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 717                         dev_err(&spi->dev, "TXS timed out\n");
 718                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 719                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 720                         dev_err(&spi->dev, "EOT timed out\n");
 721
 722                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 723                  * otherwise these rx datas will affect the direct following
 724                  * RX_ONLY transfer.
 725                  */
 726                 omap2_mcspi_set_enable(spi, 0);
 727         }
 728 out:
 729         omap2_mcspi_set_enable(spi, 1);
 730         return count - c;
 731 }
 732
 733 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 734 {
 735         u32 div;
 736
 737         for (div = 0; div < 15; div++)
 738                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 739                         return div;
 740
 741         return 15;
 742 }
 743
 744 /* called only when no transfer is active to this device */
 745 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 746                 struct spi_transfer *t)
 747 {
 748         struct omap2_mcspi_cs *cs = spi->controller_state;
 749         struct omap2_mcspi *mcspi;
 750         struct spi_master *spi_cntrl;
 751         u32 l = 0, div = 0;
 752         u8 word_len = spi->bits_per_word;
 753         u32 speed_hz = spi->max_speed_hz;
 754
 755         mcspi = spi_master_get_devdata(spi->master);
 756         spi_cntrl = mcspi->master;
 757
 758         if (t != NULL && t->bits_per_word)
 759                 word_len = t->bits_per_word;
 760
 761         cs->word_len = word_len;
 762
 763         if (t && t->speed_hz)
 764                 speed_hz = t->speed_hz;
 765
 766         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 767         div = omap2_mcspi_calc_divisor(speed_hz);
 768
 769         l = mcspi_cached_chconf0(spi);
 770
 771         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 772          * REVISIT: this controller could support SPI_3WIRE mode.
 773          */
 774         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 775                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 776                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 777                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 778         } else {
 779                 l |= OMAP2_MCSPI_CHCONF_IS;
 780                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 781                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 782         }
 783
 784         /* wordlength */
 785         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 786         l |= (word_len - 1) << 7;
 787
 788         /* set chipselect polarity; manage with FORCE */
 789         if (!(spi->mode & SPI_CS_HIGH))
 790                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 791         else
 792                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 793
 794         /* set clock divisor */
 795         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 796         l |= div << 2;
 797
 798         /* set SPI mode 0..3 */
 799         if (spi->mode & SPI_CPOL)
 800                 l |= OMAP2_MCSPI_CHCONF_POL;
 801         else
 802                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 803         if (spi->mode & SPI_CPHA)
 804                 l |= OMAP2_MCSPI_CHCONF_PHA;
 805         else
 806                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 807
 808         mcspi_write_chconf0(spi, l);
 809
 810         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 811                         OMAP2_MCSPI_MAX_FREQ >> div,
 812                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 813                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 814
 815         return 0;
 816 }
 817
 818 /*
 819  * Note that we currently allow DMA only if we get a channel
 820  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 821  */
 822 static int omap2_mcspi_request_dma(struct spi_device *spi)
 823 {
 824         struct spi_master       *master = spi->master;
 825         struct omap2_mcspi      *mcspi;
 826         struct omap2_mcspi_dma  *mcspi_dma;
 827         dma_cap_mask_t mask;
 828         unsigned sig;
 829
 830         mcspi = spi_master_get_devdata(master);
 831         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 832
 833         init_completion(&mcspi_dma->dma_rx_completion);
 834         init_completion(&mcspi_dma->dma_tx_completion);
 835
 836         dma_cap_zero(mask);
 837         dma_cap_set(DMA_SLAVE, mask);
 838         sig = mcspi_dma->dma_rx_sync_dev;
 839         mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 840         if (!mcspi_dma->dma_rx)
 841                 goto no_dma;
 842
 843         sig = mcspi_dma->dma_tx_sync_dev;
 844         mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 845         if (!mcspi_dma->dma_tx) {
 846                 dma_release_channel(mcspi_dma->dma_rx);
 847                 mcspi_dma->dma_rx = NULL;
 848                 goto no_dma;
 849         }
 850
 851         return 0;
 852
 853 no_dma:
 854         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 855         return -EAGAIN;
 856 }
 857
 858 static int omap2_mcspi_setup(struct spi_device *spi)
 859 {
 860         int                     ret;
 861         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 862         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 863         struct omap2_mcspi_dma  *mcspi_dma;
 864         struct omap2_mcspi_cs   *cs = spi->controller_state;
 865
 866         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 867                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 868                         spi->bits_per_word);
 869                 return -EINVAL;
 870         }
 871
 872         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 873
 874         if (!cs) {
 875                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 876                 if (!cs)
 877                         return -ENOMEM;
 878                 cs->base = mcspi->base + spi->chip_select * 0x14;
 879                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 880                 cs->chconf0 = 0;
 881                 spi->controller_state = cs;
 882                 /* Link this to context save list */
 883                 list_add_tail(&cs->node, &ctx->cs);
 884         }
 885
 886         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
 887                 ret = omap2_mcspi_request_dma(spi);
 888                 if (ret < 0 && ret != -EAGAIN)
 889                         return ret;
 890         }
 891
 892         ret = pm_runtime_get_sync(mcspi->dev);
 893         if (ret < 0)
 894                 return ret;
 895
 896         ret = omap2_mcspi_setup_transfer(spi, NULL);
 897         pm_runtime_mark_last_busy(mcspi->dev);
 898         pm_runtime_put_autosuspend(mcspi->dev);
 899
 900         return ret;
 901 }
 902
 903 static void omap2_mcspi_cleanup(struct spi_device *spi)
 904 {
 905         struct omap2_mcspi      *mcspi;
 906         struct omap2_mcspi_dma  *mcspi_dma;
 907         struct omap2_mcspi_cs   *cs;
 908
 909         mcspi = spi_master_get_devdata(spi->master);
 910
 911         if (spi->controller_state) {
 912                 /* Unlink controller state from context save list */
 913                 cs = spi->controller_state;
 914                 list_del(&cs->node);
 915
 916                 kfree(cs);
 917         }
 918
 919         if (spi->chip_select < spi->master->num_chipselect) {
 920                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 921
 922                 if (mcspi_dma->dma_rx) {
 923                         dma_release_channel(mcspi_dma->dma_rx);
 924                         mcspi_dma->dma_rx = NULL;
 925                 }
 926                 if (mcspi_dma->dma_tx) {
 927                         dma_release_channel(mcspi_dma->dma_tx);
 928                         mcspi_dma->dma_tx = NULL;
 929                 }
 930         }
 931 }
 932
 933 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
 934 {
 935
 936         /* We only enable one channel at a time -- the one whose message is
 937          * -- although this controller would gladly
 938          * arbitrate among multiple channels.  This corresponds to "single
 939          * channel" master mode.  As a side effect, we need to manage the
 940          * chipselect with the FORCE bit ... CS != channel enable.
 941          */
 942
 943         struct spi_device               *spi;
 944         struct spi_transfer             *t = NULL;
 945         struct spi_master               *master;
 946         struct omap2_mcspi_dma          *mcspi_dma;
 947         int                             cs_active = 0;
 948         struct omap2_mcspi_cs           *cs;
 949         struct omap2_mcspi_device_config *cd;
 950         int                             par_override = 0;
 951         int                             status = 0;
 952         u32                             chconf;
 953
 954         spi = m->spi;
 955         master = spi->master;
 956         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 957         cs = spi->controller_state;
 958         cd = spi->controller_data;
 959
 960         omap2_mcspi_set_enable(spi, 1);
 961         list_for_each_entry(t, &m->transfers, transfer_list) {
 962                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 963                         status = -EINVAL;
 964                         break;
 965                 }
 966                 if (par_override || t->speed_hz || t->bits_per_word) {
 967                         par_override = 1;
 968                         status = omap2_mcspi_setup_transfer(spi, t);
 969                         if (status < 0)
 970                                 break;
 971                         if (!t->speed_hz && !t->bits_per_word)
 972                                 par_override = 0;
 973                 }
 974                 if (cd && cd->cs_per_word) {
 975                         chconf = mcspi->ctx.modulctrl;
 976                         chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
 977                         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
 978                         mcspi->ctx.modulctrl =
 979                                 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
 980                 }
 981
 982
 983                 if (!cs_active) {
 984                         omap2_mcspi_force_cs(spi, 1);
 985                         cs_active = 1;
 986                 }
 987
 988                 chconf = mcspi_cached_chconf0(spi);
 989                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 990                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 991
 992                 if (t->tx_buf == NULL)
 993                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 994                 else if (t->rx_buf == NULL)
 995                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 996
 997                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 998                         /* Turbo mode is for more than one word */
 999                         if (t->len > ((cs->word_len + 7) >> 3))
1000                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1001                 }
1002
1003                 mcspi_write_chconf0(spi, chconf);
1004
1005                 if (t->len) {
1006                         unsigned        count;
1007
1008                         /* RX_ONLY mode needs dummy data in TX reg */
1009                         if (t->tx_buf == NULL)
1010                                 __raw_writel(0, cs->base
1011                                                 + OMAP2_MCSPI_TX0);
1012
1013                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1014                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1015                                 count = omap2_mcspi_txrx_dma(spi, t);
1016                         else
1017                                 count = omap2_mcspi_txrx_pio(spi, t);
1018                         m->actual_length += count;
1019
1020                         if (count != t->len) {
1021                                 status = -EIO;
1022                                 break;
1023                         }
1024                 }
1025
1026                 if (t->delay_usecs)
1027                         udelay(t->delay_usecs);
1028
1029                 /* ignore the "leave it on after last xfer" hint */
1030                 if (t->cs_change) {
1031                         omap2_mcspi_force_cs(spi, 0);
1032                         cs_active = 0;
1033                 }
1034         }
1035         /* Restore defaults if they were overriden */
1036         if (par_override) {
1037                 par_override = 0;
1038                 status = omap2_mcspi_setup_transfer(spi, NULL);
1039         }
1040
1041         if (cs_active)
1042                 omap2_mcspi_force_cs(spi, 0);
1043
1044         if (cd && cd->cs_per_word) {
1045                 chconf = mcspi->ctx.modulctrl;
1046                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1047                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1048                 mcspi->ctx.modulctrl =
1049                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1050         }
1051
1052         omap2_mcspi_set_enable(spi, 0);
1053
1054         m->status = status;
1055
1056 }
1057
1058 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1059                 struct spi_message *m)
1060 {
1061         struct spi_device       *spi;
1062         struct omap2_mcspi      *mcspi;
1063         struct omap2_mcspi_dma  *mcspi_dma;
1064         struct spi_transfer     *t;
1065
1066         spi = m->spi;
1067         mcspi = spi_master_get_devdata(master);
1068         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1069         m->actual_length = 0;
1070         m->status = 0;
1071
1072         /* reject invalid messages and transfers */
1073         if (list_empty(&m->transfers))
1074                 return -EINVAL;
1075         list_for_each_entry(t, &m->transfers, transfer_list) {
1076                 const void      *tx_buf = t->tx_buf;
1077                 void            *rx_buf = t->rx_buf;
1078                 unsigned        len = t->len;
1079
1080                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1081                                 || (len && !(rx_buf || tx_buf))
1082                                 || (t->bits_per_word &&
1083                                         (  t->bits_per_word < 4
1084                                            || t->bits_per_word > 32))) {
1085                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1086                                         t->speed_hz,
1087                                         len,
1088                                         tx_buf ? "tx" : "",
1089                                         rx_buf ? "rx" : "",
1090                                         t->bits_per_word);
1091                         return -EINVAL;
1092                 }
1093                 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1094                         dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1095                                         t->speed_hz,
1096                                         OMAP2_MCSPI_MAX_FREQ >> 15);
1097                         return -EINVAL;
1098                 }
1099
1100                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1101                         continue;
1102
1103                 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1104                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1105                                         len, DMA_TO_DEVICE);
1106                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1107                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1108                                                 'T', len);
1109                                 return -EINVAL;
1110                         }
1111                 }
1112                 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1113                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1114                                         DMA_FROM_DEVICE);
1115                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1116                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1117                                                 'R', len);
1118                                 if (tx_buf != NULL)
1119                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1120                                                         len, DMA_TO_DEVICE);
1121                                 return -EINVAL;
1122                         }
1123                 }
1124         }
1125
1126         omap2_mcspi_work(mcspi, m);
1127         spi_finalize_current_message(master);
1128         return 0;
1129 }
1130
1131 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1132 {
1133         struct spi_master       *master = mcspi->master;
1134         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1135         int                     ret = 0;
1136
1137         ret = pm_runtime_get_sync(mcspi->dev);
1138         if (ret < 0)
1139                 return ret;
1140
1141         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1142                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1143         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1144
1145         omap2_mcspi_set_master_mode(master);
1146         pm_runtime_mark_last_busy(mcspi->dev);
1147         pm_runtime_put_autosuspend(mcspi->dev);
1148         return 0;
1149 }
1150
1151 static int omap_mcspi_runtime_resume(struct device *dev)
1152 {
1153         struct omap2_mcspi      *mcspi;
1154         struct spi_master       *master;
1155
1156         master = dev_get_drvdata(dev);
1157         mcspi = spi_master_get_devdata(master);
1158         omap2_mcspi_restore_ctx(mcspi);
1159
1160         return 0;
1161 }
1162
1163 static struct omap2_mcspi_platform_config omap2_pdata = {
1164         .regs_offset = 0,
1165 };
1166
1167 static struct omap2_mcspi_platform_config omap4_pdata = {
1168         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1169 };
1170
1171 static const struct of_device_id omap_mcspi_of_match[] = {
1172         {
1173                 .compatible = "ti,omap2-mcspi",
1174                 .data = &omap2_pdata,
1175         },
1176         {
1177                 .compatible = "ti,omap4-mcspi",
1178                 .data = &omap4_pdata,
1179         },
1180         { },
1181 };
1182 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1183
1184 static int omap2_mcspi_probe(struct platform_device *pdev)
1185 {
1186         struct spi_master       *master;
1187         const struct omap2_mcspi_platform_config *pdata;
1188         struct omap2_mcspi      *mcspi;
1189         struct resource         *r;
1190         int                     status = 0, i;
1191         u32                     regs_offset = 0;
1192         static int              bus_num = 1;
1193         struct device_node      *node = pdev->dev.of_node;
1194         const struct of_device_id *match;
1195
1196         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1197         if (master == NULL) {
1198                 dev_dbg(&pdev->dev, "master allocation failed\n");
1199                 return -ENOMEM;
1200         }
1201
1202         /* the spi->mode bits understood by this driver: */
1203         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1204
1205         master->setup = omap2_mcspi_setup;
1206         master->prepare_transfer_hardware = omap2_prepare_transfer;
1207         master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1208         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1209         master->cleanup = omap2_mcspi_cleanup;
1210         master->dev.of_node = node;
1211
1212         dev_set_drvdata(&pdev->dev, master);
1213
1214         mcspi = spi_master_get_devdata(master);
1215         mcspi->master = master;
1216
1217         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1218         if (match) {
1219                 u32 num_cs = 1; /* default number of chipselect */
1220                 pdata = match->data;
1221
1222                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1223                 master->num_chipselect = num_cs;
1224                 master->bus_num = bus_num++;
1225                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1226                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1227         } else {
1228                 pdata = pdev->dev.platform_data;
1229                 master->num_chipselect = pdata->num_cs;
1230                 if (pdev->id != -1)
1231                         master->bus_num = pdev->id;
1232                 mcspi->pin_dir = pdata->pin_dir;
1233         }
1234         regs_offset = pdata->regs_offset;
1235
1236         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1237         if (r == NULL) {
1238                 status = -ENODEV;
1239                 goto free_master;
1240         }
1241
1242         r->start += regs_offset;
1243         r->end += regs_offset;
1244         mcspi->phys = r->start;
1245
1246         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1247         if (IS_ERR(mcspi->base)) {
1248                 status = PTR_ERR(mcspi->base);
1249                 goto free_master;
1250         }
1251
1252         mcspi->dev = &pdev->dev;
1253
1254         INIT_LIST_HEAD(&mcspi->ctx.cs);
1255
1256         mcspi->dma_channels = kcalloc(master->num_chipselect,
1257                         sizeof(struct omap2_mcspi_dma),
1258                         GFP_KERNEL);
1259
1260         if (mcspi->dma_channels == NULL)
1261                 goto free_master;
1262
1263         for (i = 0; i < master->num_chipselect; i++) {
1264                 char dma_ch_name[14];
1265                 struct resource *dma_res;
1266
1267                 sprintf(dma_ch_name, "rx%d", i);
1268                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1269                                 dma_ch_name);
1270                 if (!dma_res) {
1271                         dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1272                         status = -ENODEV;
1273                         break;
1274                 }
1275
1276                 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1277                 sprintf(dma_ch_name, "tx%d", i);
1278                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1279                                 dma_ch_name);
1280                 if (!dma_res) {
1281                         dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1282                         status = -ENODEV;
1283                         break;
1284                 }
1285
1286                 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1287         }
1288
1289         if (status < 0)
1290                 goto dma_chnl_free;
1291
1292         pm_runtime_use_autosuspend(&pdev->dev);
1293         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1294         pm_runtime_enable(&pdev->dev);
1295
1296         status = omap2_mcspi_master_setup(mcspi);
1297         if (status < 0)
1298                 goto disable_pm;
1299
1300         status = spi_register_master(master);
1301         if (status < 0)
1302                 goto disable_pm;
1303
1304         return status;
1305
1306 disable_pm:
1307         pm_runtime_disable(&pdev->dev);
1308 dma_chnl_free:
1309         kfree(mcspi->dma_channels);
1310 free_master:
1311         spi_master_put(master);
1312         return status;
1313 }
1314
1315 static int omap2_mcspi_remove(struct platform_device *pdev)
1316 {
1317         struct spi_master       *master;
1318         struct omap2_mcspi      *mcspi;
1319         struct omap2_mcspi_dma  *dma_channels;
1320
1321         master = dev_get_drvdata(&pdev->dev);
1322         mcspi = spi_master_get_devdata(master);
1323         dma_channels = mcspi->dma_channels;
1324
1325         pm_runtime_put_sync(mcspi->dev);
1326         pm_runtime_disable(&pdev->dev);
1327
1328         spi_unregister_master(master);
1329         kfree(dma_channels);
1330
1331         return 0;
1332 }
1333
1334 /* work with hotplug and coldplug */
1335 MODULE_ALIAS("platform:omap2_mcspi");
1336
1337 #ifdef  CONFIG_SUSPEND
1338 /*
1339  * When SPI wake up from off-mode, CS is in activate state. If it was in
1340  * unactive state when driver was suspend, then force it to unactive state at
1341  * wake up.
1342  */
1343 static int omap2_mcspi_resume(struct device *dev)
1344 {
1345         struct spi_master       *master = dev_get_drvdata(dev);
1346         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1347         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1348         struct omap2_mcspi_cs   *cs;
1349
1350         pm_runtime_get_sync(mcspi->dev);
1351         list_for_each_entry(cs, &ctx->cs, node) {
1352                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1353                         /*
1354                          * We need to toggle CS state for OMAP take this
1355                          * change in account.
1356                          */
1357                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1358                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1359                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1360                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1361                 }
1362         }
1363         pm_runtime_mark_last_busy(mcspi->dev);
1364         pm_runtime_put_autosuspend(mcspi->dev);
1365         return 0;
1366 }
1367 #else
1368 #define omap2_mcspi_resume      NULL
1369 #endif
1370
1371 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1372         .resume = omap2_mcspi_resume,
1373         .runtime_resume = omap_mcspi_runtime_resume,
1374 };
1375
1376 static struct platform_driver omap2_mcspi_driver = {
1377         .driver = {
1378                 .name =         "omap2_mcspi",
1379                 .owner =        THIS_MODULE,
1380                 .pm =           &omap2_mcspi_pm_ops,
1381                 .of_match_table = omap_mcspi_of_match,
1382         },
1383         .probe =        omap2_mcspi_probe,
1384         .remove =       omap2_mcspi_remove,
1385 };
1386
1387 module_platform_driver(omap2_mcspi_driver);
1388 MODULE_LICENSE("GPL");