drivers/spi/spi-omap2-mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrj�l� <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/omap-dma.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/err.h>
  35 #include <linux/clk.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/gcd.h>
  42
  43 #include <linux/spi/spi.h>
  44
  45 #include <linux/platform_data/spi-omap2-mcspi.h>
  46
  47 #define OMAP2_MCSPI_MAX_FREQ            48000000
  48 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
  49 #define OMAP2_MCSPI_MAX_FIFOWCNT        0xFFFF
  50 #define SPI_AUTOSUSPEND_TIMEOUT         2000
  51
  52 #define OMAP2_MCSPI_REVISION            0x00
  53 #define OMAP2_MCSPI_SYSSTATUS           0x14
  54 #define OMAP2_MCSPI_IRQSTATUS           0x18
  55 #define OMAP2_MCSPI_IRQENABLE           0x1c
  56 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  57 #define OMAP2_MCSPI_SYST                0x24
  58 #define OMAP2_MCSPI_MODULCTRL           0x28
  59 #define OMAP2_MCSPI_XFERLEVEL           0x7c
  60
  61 /* per-channel banks, 0x14 bytes each, first is: */
  62 #define OMAP2_MCSPI_CHCONF0             0x2c
  63 #define OMAP2_MCSPI_CHSTAT0             0x30
  64 #define OMAP2_MCSPI_CHCTRL0             0x34
  65 #define OMAP2_MCSPI_TX0                 0x38
  66 #define OMAP2_MCSPI_RX0                 0x3c
  67
  68 /* per-register bitmasks: */
  69 #define OMAP2_MCSPI_IRQSTATUS_EOW       BIT(17)
  70
  71 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  72 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  73 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  74
  75 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  76 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  78 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  79 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  82 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  83 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  84 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  85 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  86 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  87 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  88 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  89 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  90 #define OMAP2_MCSPI_CHCONF_FFET         BIT(27)
  91 #define OMAP2_MCSPI_CHCONF_FFER         BIT(28)
  92
  93 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  94 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  95 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  96 #define OMAP2_MCSPI_CHSTAT_TXFFE        BIT(3)
  97
  98 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  99
 100 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
 101
 102 /* We have 2 DMA channels per CS, one for RX and one for TX */
 103 struct omap2_mcspi_dma {
 104         struct dma_chan *dma_tx;
 105         struct dma_chan *dma_rx;
 106
 107         int dma_tx_sync_dev;
 108         int dma_rx_sync_dev;
 109
 110         struct completion dma_tx_completion;
 111         struct completion dma_rx_completion;
 112 };
 113
 114 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 115  * cache operations; better heuristics consider wordsize and bitrate.
 116  */
 117 #define DMA_MIN_BYTES                   160
 118
 119
 120 /*
 121  * Used for context save and restore, structure members to be updated whenever
 122  * corresponding registers are modified.
 123  */
 124 struct omap2_mcspi_regs {
 125         u32 modulctrl;
 126         u32 wakeupenable;
 127         struct list_head cs;
 128 };
 129
 130 struct omap2_mcspi {
 131         struct spi_master       *master;
 132         /* Virtual base address of the controller */
 133         void __iomem            *base;
 134         unsigned long           phys;
 135         /* SPI1 has 4 channels, while SPI2 has 2 */
 136         struct omap2_mcspi_dma  *dma_channels;
 137         struct device           *dev;
 138         struct omap2_mcspi_regs ctx;
 139         int                     fifo_depth;
 140         unsigned int            pin_dir:1;
 141 };
 142
 143 struct omap2_mcspi_cs {
 144         void __iomem            *base;
 145         unsigned long           phys;
 146         int                     word_len;
 147         struct list_head        node;
 148         /* Context save and restore shadow register */
 149         u32                     chconf0;
 150 };
 151
 152 static inline void mcspi_write_reg(struct spi_master *master,
 153                 int idx, u32 val)
 154 {
 155         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 156
 157         __raw_writel(val, mcspi->base + idx);
 158 }
 159
 160 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 161 {
 162         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 163
 164         return __raw_readl(mcspi->base + idx);
 165 }
 166
 167 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 168                 int idx, u32 val)
 169 {
 170         struct omap2_mcspi_cs   *cs = spi->controller_state;
 171
 172         __raw_writel(val, cs->base +  idx);
 173 }
 174
 175 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 176 {
 177         struct omap2_mcspi_cs   *cs = spi->controller_state;
 178
 179         return __raw_readl(cs->base + idx);
 180 }
 181
 182 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 183 {
 184         struct omap2_mcspi_cs *cs = spi->controller_state;
 185
 186         return cs->chconf0;
 187 }
 188
 189 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 190 {
 191         struct omap2_mcspi_cs *cs = spi->controller_state;
 192
 193         cs->chconf0 = val;
 194         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 195         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 196 }
 197
 198 static inline int mcspi_bytes_per_word(int word_len)
 199 {
 200         if (word_len <= 8)
 201                 return 1;
 202         else if (word_len <= 16)
 203                 return 2;
 204         else /* word_len <= 32 */
 205                 return 4;
 206 }
 207
 208 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 209                 int is_read, int enable)
 210 {
 211         u32 l, rw;
 212
 213         l = mcspi_cached_chconf0(spi);
 214
 215         if (is_read) /* 1 is read, 0 write */
 216                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 217         else
 218                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 219
 220         if (enable)
 221                 l |= rw;
 222         else
 223                 l &= ~rw;
 224
 225         mcspi_write_chconf0(spi, l);
 226 }
 227
 228 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 229 {
 230         u32 l;
 231
 232         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 233         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 234         /* Flash post-writes */
 235         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 236 }
 237
 238 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 239 {
 240         u32 l;
 241
 242         l = mcspi_cached_chconf0(spi);
 243         if (cs_active)
 244                 l |= OMAP2_MCSPI_CHCONF_FORCE;
 245         else
 246                 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
 247
 248         mcspi_write_chconf0(spi, l);
 249 }
 250
 251 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 252 {
 253         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
 254         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 255         u32 l;
 256
 257         /*
 258          * Setup when switching from (reset default) slave mode
 259          * to single-channel master mode
 260          */
 261         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 262         l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
 263         l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
 264         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 265
 266         ctx->modulctrl = l;
 267 }
 268
 269 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
 270                                 struct spi_transfer *t, int enable)
 271 {
 272         struct spi_master *master = spi->master;
 273         struct omap2_mcspi_cs *cs = spi->controller_state;
 274         struct omap2_mcspi *mcspi;
 275         unsigned int wcnt;
 276         int fifo_depth, bytes_per_word;
 277         u32 chconf, xferlevel;
 278
 279         mcspi = spi_master_get_devdata(master);
 280
 281         chconf = mcspi_cached_chconf0(spi);
 282         if (enable) {
 283                 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
 284                 if (t->len % bytes_per_word != 0)
 285                         goto disable_fifo;
 286
 287                 fifo_depth = gcd(t->len, OMAP2_MCSPI_MAX_FIFODEPTH);
 288                 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
 289                         goto disable_fifo;
 290
 291                 wcnt = t->len / bytes_per_word;
 292                 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
 293                         goto disable_fifo;
 294
 295                 xferlevel = wcnt << 16;
 296                 if (t->rx_buf != NULL) {
 297                         chconf |= OMAP2_MCSPI_CHCONF_FFER;
 298                         xferlevel |= (fifo_depth - 1) << 8;
 299                 } else {
 300                         chconf |= OMAP2_MCSPI_CHCONF_FFET;
 301                         xferlevel |= fifo_depth - 1;
 302                 }
 303
 304                 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
 305                 mcspi_write_chconf0(spi, chconf);
 306                 mcspi->fifo_depth = fifo_depth;
 307
 308                 return;
 309         }
 310
 311 disable_fifo:
 312         if (t->rx_buf != NULL)
 313                 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
 314         else
 315                 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
 316
 317         mcspi_write_chconf0(spi, chconf);
 318         mcspi->fifo_depth = 0;
 319 }
 320
 321 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 322 {
 323         struct spi_master       *spi_cntrl = mcspi->master;
 324         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 325         struct omap2_mcspi_cs   *cs;
 326
 327         /* McSPI: context restore */
 328         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
 329         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
 330
 331         list_for_each_entry(cs, &ctx->cs, node)
 332                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 333 }
 334
 335 static int omap2_prepare_transfer(struct spi_master *master)
 336 {
 337         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 338
 339         pm_runtime_get_sync(mcspi->dev);
 340         return 0;
 341 }
 342
 343 static int omap2_unprepare_transfer(struct spi_master *master)
 344 {
 345         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 346
 347         pm_runtime_mark_last_busy(mcspi->dev);
 348         pm_runtime_put_autosuspend(mcspi->dev);
 349         return 0;
 350 }
 351
 352 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 353 {
 354         unsigned long timeout;
 355
 356         timeout = jiffies + msecs_to_jiffies(1000);
 357         while (!(__raw_readl(reg) & bit)) {
 358                 if (time_after(jiffies, timeout)) {
 359                         if (!(__raw_readl(reg) & bit))
 360                                 return -ETIMEDOUT;
 361                         else
 362                                 return 0;
 363                 }
 364                 cpu_relax();
 365         }
 366         return 0;
 367 }
 368
 369 static void omap2_mcspi_rx_callback(void *data)
 370 {
 371         struct spi_device *spi = data;
 372         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 373         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 374
 375         /* We must disable the DMA RX request */
 376         omap2_mcspi_set_dma_req(spi, 1, 0);
 377
 378         complete(&mcspi_dma->dma_rx_completion);
 379 }
 380
 381 static void omap2_mcspi_tx_callback(void *data)
 382 {
 383         struct spi_device *spi = data;
 384         struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
 385         struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 386
 387         /* We must disable the DMA TX request */
 388         omap2_mcspi_set_dma_req(spi, 0, 0);
 389
 390         complete(&mcspi_dma->dma_tx_completion);
 391 }
 392
 393 static void omap2_mcspi_tx_dma(struct spi_device *spi,
 394                                 struct spi_transfer *xfer,
 395                                 struct dma_slave_config cfg)
 396 {
 397         struct omap2_mcspi      *mcspi;
 398         struct omap2_mcspi_dma  *mcspi_dma;
 399         unsigned int            count;
 400
 401         mcspi = spi_master_get_devdata(spi->master);
 402         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 403         count = xfer->len;
 404
 405         if (mcspi_dma->dma_tx) {
 406                 struct dma_async_tx_descriptor *tx;
 407                 struct scatterlist sg;
 408
 409                 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
 410
 411                 sg_init_table(&sg, 1);
 412                 sg_dma_address(&sg) = xfer->tx_dma;
 413                 sg_dma_len(&sg) = xfer->len;
 414
 415                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
 416                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 417                 if (tx) {
 418                         tx->callback = omap2_mcspi_tx_callback;
 419                         tx->callback_param = spi;
 420                         dmaengine_submit(tx);
 421                 } else {
 422                         /* FIXME: fall back to PIO? */
 423                 }
 424         }
 425         dma_async_issue_pending(mcspi_dma->dma_tx);
 426         omap2_mcspi_set_dma_req(spi, 0, 1);
 427
 428 }
 429
 430 static unsigned
 431 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
 432                                 struct dma_slave_config cfg,
 433                                 unsigned es)
 434 {
 435         struct omap2_mcspi      *mcspi;
 436         struct omap2_mcspi_dma  *mcspi_dma;
 437         unsigned int            count, dma_count;
 438         u32                     l;
 439         int                     elements = 0;
 440         int                     word_len, element_count;
 441         struct omap2_mcspi_cs   *cs = spi->controller_state;
 442         mcspi = spi_master_get_devdata(spi->master);
 443         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 444         count = xfer->len;
 445         dma_count = xfer->len;
 446
 447         if (mcspi->fifo_depth == 0)
 448                 dma_count -= es;
 449
 450         word_len = cs->word_len;
 451         l = mcspi_cached_chconf0(spi);
 452
 453         if (word_len <= 8)
 454                 element_count = count;
 455         else if (word_len <= 16)
 456                 element_count = count >> 1;
 457         else /* word_len <= 32 */
 458                 element_count = count >> 2;
 459
 460         if (mcspi_dma->dma_rx) {
 461                 struct dma_async_tx_descriptor *tx;
 462                 struct scatterlist sg;
 463
 464                 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
 465
 466                 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
 467                         dma_count -= es;
 468
 469                 sg_init_table(&sg, 1);
 470                 sg_dma_address(&sg) = xfer->rx_dma;
 471                 sg_dma_len(&sg) = dma_count;
 472
 473                 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
 474                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
 475                                 DMA_CTRL_ACK);
 476                 if (tx) {
 477                         tx->callback = omap2_mcspi_rx_callback;
 478                         tx->callback_param = spi;
 479                         dmaengine_submit(tx);
 480                 } else {
 481                                 /* FIXME: fall back to PIO? */
 482                 }
 483         }
 484
 485         dma_async_issue_pending(mcspi_dma->dma_rx);
 486         omap2_mcspi_set_dma_req(spi, 1, 1);
 487
 488         wait_for_completion(&mcspi_dma->dma_rx_completion);
 489         dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
 490                          DMA_FROM_DEVICE);
 491
 492         if (mcspi->fifo_depth > 0)
 493                 return count;
 494
 495         omap2_mcspi_set_enable(spi, 0);
 496
 497         elements = element_count - 1;
 498
 499         if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 500                 elements--;
 501
 502                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 503                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 504                         u32 w;
 505
 506                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 507                         if (word_len <= 8)
 508                                 ((u8 *)xfer->rx_buf)[elements++] = w;
 509                         else if (word_len <= 16)
 510                                 ((u16 *)xfer->rx_buf)[elements++] = w;
 511                         else /* word_len <= 32 */
 512                                 ((u32 *)xfer->rx_buf)[elements++] = w;
 513                 } else {
 514                         int bytes_per_word = mcspi_bytes_per_word(word_len);
 515                         dev_err(&spi->dev, "DMA RX penultimate word empty");
 516                         count -= (bytes_per_word << 1);
 517                         omap2_mcspi_set_enable(spi, 1);
 518                         return count;
 519                 }
 520         }
 521         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 522                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 523                 u32 w;
 524
 525                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 526                 if (word_len <= 8)
 527                         ((u8 *)xfer->rx_buf)[elements] = w;
 528                 else if (word_len <= 16)
 529                         ((u16 *)xfer->rx_buf)[elements] = w;
 530                 else /* word_len <= 32 */
 531                         ((u32 *)xfer->rx_buf)[elements] = w;
 532         } else {
 533                 dev_err(&spi->dev, "DMA RX last word empty");
 534                 count -= mcspi_bytes_per_word(word_len);
 535         }
 536         omap2_mcspi_set_enable(spi, 1);
 537         return count;
 538 }
 539
 540 static unsigned
 541 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 542 {
 543         struct omap2_mcspi      *mcspi;
 544         struct omap2_mcspi_cs   *cs = spi->controller_state;
 545         struct omap2_mcspi_dma  *mcspi_dma;
 546         unsigned int            count;
 547         u32                     l;
 548         u8                      *rx;
 549         const u8                *tx;
 550         struct dma_slave_config cfg;
 551         enum dma_slave_buswidth width;
 552         unsigned es;
 553         u32                     burst;
 554         void __iomem            *chstat_reg;
 555         void __iomem            *irqstat_reg;
 556         int                     wait_res;
 557
 558         mcspi = spi_master_get_devdata(spi->master);
 559         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 560         l = mcspi_cached_chconf0(spi);
 561
 562
 563         if (cs->word_len <= 8) {
 564                 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 565                 es = 1;
 566         } else if (cs->word_len <= 16) {
 567                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 568                 es = 2;
 569         } else {
 570                 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 571                 es = 4;
 572         }
 573
 574         count = xfer->len;
 575         burst = 1;
 576
 577         if (mcspi->fifo_depth > 0) {
 578                 if (count > mcspi->fifo_depth)
 579                         burst = mcspi->fifo_depth / es;
 580                 else
 581                         burst = count / es;
 582         }
 583
 584         memset(&cfg, 0, sizeof(cfg));
 585         cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
 586         cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
 587         cfg.src_addr_width = width;
 588         cfg.dst_addr_width = width;
 589         cfg.src_maxburst = burst;
 590         cfg.dst_maxburst = burst;
 591
 592         rx = xfer->rx_buf;
 593         tx = xfer->tx_buf;
 594
 595         if (tx != NULL)
 596                 omap2_mcspi_tx_dma(spi, xfer, cfg);
 597
 598         if (rx != NULL)
 599                 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
 600
 601         if (tx != NULL) {
 602                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 603                 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
 604                                  DMA_TO_DEVICE);
 605
 606                 if (mcspi->fifo_depth > 0) {
 607                         irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
 608
 609                         if (mcspi_wait_for_reg_bit(irqstat_reg,
 610                                                 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
 611                                 dev_err(&spi->dev, "EOW timed out\n");
 612
 613                         mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
 614                                         OMAP2_MCSPI_IRQSTATUS_EOW);
 615                 }
 616
 617                 /* for TX_ONLY mode, be sure all words have shifted out */
 618                 if (rx == NULL) {
 619                         chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
 620                         if (mcspi->fifo_depth > 0) {
 621                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 622                                                 OMAP2_MCSPI_CHSTAT_TXFFE);
 623                                 if (wait_res < 0)
 624                                         dev_err(&spi->dev, "TXFFE timed out\n");
 625                         } else {
 626                                 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
 627                                                 OMAP2_MCSPI_CHSTAT_TXS);
 628                                 if (wait_res < 0)
 629                                         dev_err(&spi->dev, "TXS timed out\n");
 630                         }
 631                         if (wait_res >= 0 &&
 632                                 (mcspi_wait_for_reg_bit(chstat_reg,
 633                                         OMAP2_MCSPI_CHSTAT_EOT) < 0))
 634                                 dev_err(&spi->dev, "EOT timed out\n");
 635                 }
 636         }
 637         return count;
 638 }
 639
 640 static unsigned
 641 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 642 {
 643         struct omap2_mcspi      *mcspi;
 644         struct omap2_mcspi_cs   *cs = spi->controller_state;
 645         unsigned int            count, c;
 646         u32                     l;
 647         void __iomem            *base = cs->base;
 648         void __iomem            *tx_reg;
 649         void __iomem            *rx_reg;
 650         void __iomem            *chstat_reg;
 651         int                     word_len;
 652
 653         mcspi = spi_master_get_devdata(spi->master);
 654         count = xfer->len;
 655         c = count;
 656         word_len = cs->word_len;
 657
 658         l = mcspi_cached_chconf0(spi);
 659
 660         /* We store the pre-calculated register addresses on stack to speed
 661          * up the transfer loop. */
 662         tx_reg          = base + OMAP2_MCSPI_TX0;
 663         rx_reg          = base + OMAP2_MCSPI_RX0;
 664         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 665
 666         if (c < (word_len>>3))
 667                 return 0;
 668
 669         if (word_len <= 8) {
 670                 u8              *rx;
 671                 const u8        *tx;
 672
 673                 rx = xfer->rx_buf;
 674                 tx = xfer->tx_buf;
 675
 676                 do {
 677                         c -= 1;
 678                         if (tx != NULL) {
 679                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 680                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 681                                         dev_err(&spi->dev, "TXS timed out\n");
 682                                         goto out;
 683                                 }
 684                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 685                                                 word_len, *tx);
 686                                 __raw_writel(*tx++, tx_reg);
 687                         }
 688                         if (rx != NULL) {
 689                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 690                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 691                                         dev_err(&spi->dev, "RXS timed out\n");
 692                                         goto out;
 693                                 }
 694
 695                                 if (c == 1 && tx == NULL &&
 696                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 697                                         omap2_mcspi_set_enable(spi, 0);
 698                                         *rx++ = __raw_readl(rx_reg);
 699                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 700                                                     word_len, *(rx - 1));
 701                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 702                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 703                                                 dev_err(&spi->dev,
 704                                                         "RXS timed out\n");
 705                                                 goto out;
 706                                         }
 707                                         c = 0;
 708                                 } else if (c == 0 && tx == NULL) {
 709                                         omap2_mcspi_set_enable(spi, 0);
 710                                 }
 711
 712                                 *rx++ = __raw_readl(rx_reg);
 713                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 714                                                 word_len, *(rx - 1));
 715                         }
 716                 } while (c);
 717         } else if (word_len <= 16) {
 718                 u16             *rx;
 719                 const u16       *tx;
 720
 721                 rx = xfer->rx_buf;
 722                 tx = xfer->tx_buf;
 723                 do {
 724                         c -= 2;
 725                         if (tx != NULL) {
 726                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 727                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 728                                         dev_err(&spi->dev, "TXS timed out\n");
 729                                         goto out;
 730                                 }
 731                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 732                                                 word_len, *tx);
 733                                 __raw_writel(*tx++, tx_reg);
 734                         }
 735                         if (rx != NULL) {
 736                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 737                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 738                                         dev_err(&spi->dev, "RXS timed out\n");
 739                                         goto out;
 740                                 }
 741
 742                                 if (c == 2 && tx == NULL &&
 743                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 744                                         omap2_mcspi_set_enable(spi, 0);
 745                                         *rx++ = __raw_readl(rx_reg);
 746                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 747                                                     word_len, *(rx - 1));
 748                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 749                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 750                                                 dev_err(&spi->dev,
 751                                                         "RXS timed out\n");
 752                                                 goto out;
 753                                         }
 754                                         c = 0;
 755                                 } else if (c == 0 && tx == NULL) {
 756                                         omap2_mcspi_set_enable(spi, 0);
 757                                 }
 758
 759                                 *rx++ = __raw_readl(rx_reg);
 760                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 761                                                 word_len, *(rx - 1));
 762                         }
 763                 } while (c >= 2);
 764         } else if (word_len <= 32) {
 765                 u32             *rx;
 766                 const u32       *tx;
 767
 768                 rx = xfer->rx_buf;
 769                 tx = xfer->tx_buf;
 770                 do {
 771                         c -= 4;
 772                         if (tx != NULL) {
 773                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 774                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 775                                         dev_err(&spi->dev, "TXS timed out\n");
 776                                         goto out;
 777                                 }
 778                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 779                                                 word_len, *tx);
 780                                 __raw_writel(*tx++, tx_reg);
 781                         }
 782                         if (rx != NULL) {
 783                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 784                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 785                                         dev_err(&spi->dev, "RXS timed out\n");
 786                                         goto out;
 787                                 }
 788
 789                                 if (c == 4 && tx == NULL &&
 790                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 791                                         omap2_mcspi_set_enable(spi, 0);
 792                                         *rx++ = __raw_readl(rx_reg);
 793                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 794                                                     word_len, *(rx - 1));
 795                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 796                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 797                                                 dev_err(&spi->dev,
 798                                                         "RXS timed out\n");
 799                                                 goto out;
 800                                         }
 801                                         c = 0;
 802                                 } else if (c == 0 && tx == NULL) {
 803                                         omap2_mcspi_set_enable(spi, 0);
 804                                 }
 805
 806                                 *rx++ = __raw_readl(rx_reg);
 807                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 808                                                 word_len, *(rx - 1));
 809                         }
 810                 } while (c >= 4);
 811         }
 812
 813         /* for TX_ONLY mode, be sure all words have shifted out */
 814         if (xfer->rx_buf == NULL) {
 815                 if (mcspi_wait_for_reg_bit(chstat_reg,
 816                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 817                         dev_err(&spi->dev, "TXS timed out\n");
 818                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 819                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 820                         dev_err(&spi->dev, "EOT timed out\n");
 821
 822                 /* disable chan to purge rx datas received in TX_ONLY transfer,
 823                  * otherwise these rx datas will affect the direct following
 824                  * RX_ONLY transfer.
 825                  */
 826                 omap2_mcspi_set_enable(spi, 0);
 827         }
 828 out:
 829         omap2_mcspi_set_enable(spi, 1);
 830         return count - c;
 831 }
 832
 833 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
 834 {
 835         u32 div;
 836
 837         for (div = 0; div < 15; div++)
 838                 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
 839                         return div;
 840
 841         return 15;
 842 }
 843
 844 /* called only when no transfer is active to this device */
 845 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 846                 struct spi_transfer *t)
 847 {
 848         struct omap2_mcspi_cs *cs = spi->controller_state;
 849         struct omap2_mcspi *mcspi;
 850         struct spi_master *spi_cntrl;
 851         u32 l = 0, div = 0;
 852         u8 word_len = spi->bits_per_word;
 853         u32 speed_hz = spi->max_speed_hz;
 854
 855         mcspi = spi_master_get_devdata(spi->master);
 856         spi_cntrl = mcspi->master;
 857
 858         if (t != NULL && t->bits_per_word)
 859                 word_len = t->bits_per_word;
 860
 861         cs->word_len = word_len;
 862
 863         if (t && t->speed_hz)
 864                 speed_hz = t->speed_hz;
 865
 866         speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
 867         div = omap2_mcspi_calc_divisor(speed_hz);
 868
 869         l = mcspi_cached_chconf0(spi);
 870
 871         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 872          * REVISIT: this controller could support SPI_3WIRE mode.
 873          */
 874         if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
 875                 l &= ~OMAP2_MCSPI_CHCONF_IS;
 876                 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
 877                 l |= OMAP2_MCSPI_CHCONF_DPE0;
 878         } else {
 879                 l |= OMAP2_MCSPI_CHCONF_IS;
 880                 l |= OMAP2_MCSPI_CHCONF_DPE1;
 881                 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
 882         }
 883
 884         /* wordlength */
 885         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 886         l |= (word_len - 1) << 7;
 887
 888         /* set chipselect polarity; manage with FORCE */
 889         if (!(spi->mode & SPI_CS_HIGH))
 890                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 891         else
 892                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 893
 894         /* set clock divisor */
 895         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 896         l |= div << 2;
 897
 898         /* set SPI mode 0..3 */
 899         if (spi->mode & SPI_CPOL)
 900                 l |= OMAP2_MCSPI_CHCONF_POL;
 901         else
 902                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 903         if (spi->mode & SPI_CPHA)
 904                 l |= OMAP2_MCSPI_CHCONF_PHA;
 905         else
 906                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 907
 908         mcspi_write_chconf0(spi, l);
 909
 910         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 911                         OMAP2_MCSPI_MAX_FREQ >> div,
 912                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 913                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 914
 915         return 0;
 916 }
 917
 918 /*
 919  * Note that we currently allow DMA only if we get a channel
 920  * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
 921  */
 922 static int omap2_mcspi_request_dma(struct spi_device *spi)
 923 {
 924         struct spi_master       *master = spi->master;
 925         struct omap2_mcspi      *mcspi;
 926         struct omap2_mcspi_dma  *mcspi_dma;
 927         dma_cap_mask_t mask;
 928         unsigned sig;
 929
 930         mcspi = spi_master_get_devdata(master);
 931         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 932
 933         init_completion(&mcspi_dma->dma_rx_completion);
 934         init_completion(&mcspi_dma->dma_tx_completion);
 935
 936         dma_cap_zero(mask);
 937         dma_cap_set(DMA_SLAVE, mask);
 938         sig = mcspi_dma->dma_rx_sync_dev;
 939         mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 940         if (!mcspi_dma->dma_rx)
 941                 goto no_dma;
 942
 943         sig = mcspi_dma->dma_tx_sync_dev;
 944         mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
 945         if (!mcspi_dma->dma_tx) {
 946                 dma_release_channel(mcspi_dma->dma_rx);
 947                 mcspi_dma->dma_rx = NULL;
 948                 goto no_dma;
 949         }
 950
 951         return 0;
 952
 953 no_dma:
 954         dev_warn(&spi->dev, "not using DMA for McSPI\n");
 955         return -EAGAIN;
 956 }
 957
 958 static int omap2_mcspi_setup(struct spi_device *spi)
 959 {
 960         int                     ret;
 961         struct omap2_mcspi      *mcspi = spi_master_get_devdata(spi->master);
 962         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
 963         struct omap2_mcspi_dma  *mcspi_dma;
 964         struct omap2_mcspi_cs   *cs = spi->controller_state;
 965
 966         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 967                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 968                         spi->bits_per_word);
 969                 return -EINVAL;
 970         }
 971
 972         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 973
 974         if (!cs) {
 975                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 976                 if (!cs)
 977                         return -ENOMEM;
 978                 cs->base = mcspi->base + spi->chip_select * 0x14;
 979                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 980                 cs->chconf0 = 0;
 981                 spi->controller_state = cs;
 982                 /* Link this to context save list */
 983                 list_add_tail(&cs->node, &ctx->cs);
 984         }
 985
 986         if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
 987                 ret = omap2_mcspi_request_dma(spi);
 988                 if (ret < 0 && ret != -EAGAIN)
 989                         return ret;
 990         }
 991
 992         ret = pm_runtime_get_sync(mcspi->dev);
 993         if (ret < 0)
 994                 return ret;
 995
 996         ret = omap2_mcspi_setup_transfer(spi, NULL);
 997         pm_runtime_mark_last_busy(mcspi->dev);
 998         pm_runtime_put_autosuspend(mcspi->dev);
 999
1000         return ret;
1001 }
1002
1003 static void omap2_mcspi_cleanup(struct spi_device *spi)
1004 {
1005         struct omap2_mcspi      *mcspi;
1006         struct omap2_mcspi_dma  *mcspi_dma;
1007         struct omap2_mcspi_cs   *cs;
1008
1009         mcspi = spi_master_get_devdata(spi->master);
1010
1011         if (spi->controller_state) {
1012                 /* Unlink controller state from context save list */
1013                 cs = spi->controller_state;
1014                 list_del(&cs->node);
1015
1016                 kfree(cs);
1017         }
1018
1019         if (spi->chip_select < spi->master->num_chipselect) {
1020                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1021
1022                 if (mcspi_dma->dma_rx) {
1023                         dma_release_channel(mcspi_dma->dma_rx);
1024                         mcspi_dma->dma_rx = NULL;
1025                 }
1026                 if (mcspi_dma->dma_tx) {
1027                         dma_release_channel(mcspi_dma->dma_tx);
1028                         mcspi_dma->dma_tx = NULL;
1029                 }
1030         }
1031 }
1032
1033 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1034 {
1035
1036         /* We only enable one channel at a time -- the one whose message is
1037          * -- although this controller would gladly
1038          * arbitrate among multiple channels.  This corresponds to "single
1039          * channel" master mode.  As a side effect, we need to manage the
1040          * chipselect with the FORCE bit ... CS != channel enable.
1041          */
1042
1043         struct spi_device               *spi;
1044         struct spi_transfer             *t = NULL;
1045         struct spi_master               *master;
1046         struct omap2_mcspi_dma          *mcspi_dma;
1047         int                             cs_active = 0;
1048         struct omap2_mcspi_cs           *cs;
1049         struct omap2_mcspi_device_config *cd;
1050         int                             par_override = 0;
1051         int                             status = 0;
1052         u32                             chconf;
1053
1054         spi = m->spi;
1055         master = spi->master;
1056         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1057         cs = spi->controller_state;
1058         cd = spi->controller_data;
1059
1060         omap2_mcspi_set_enable(spi, 0);
1061         list_for_each_entry(t, &m->transfers, transfer_list) {
1062                 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1063                         status = -EINVAL;
1064                         break;
1065                 }
1066                 if (par_override || t->speed_hz || t->bits_per_word) {
1067                         par_override = 1;
1068                         status = omap2_mcspi_setup_transfer(spi, t);
1069                         if (status < 0)
1070                                 break;
1071                         if (!t->speed_hz && !t->bits_per_word)
1072                                 par_override = 0;
1073                 }
1074                 if (cd && cd->cs_per_word) {
1075                         chconf = mcspi->ctx.modulctrl;
1076                         chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1077                         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1078                         mcspi->ctx.modulctrl =
1079                                 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1080                 }
1081
1082
1083                 if (!cs_active) {
1084                         omap2_mcspi_force_cs(spi, 1);
1085                         cs_active = 1;
1086                 }
1087
1088                 chconf = mcspi_cached_chconf0(spi);
1089                 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1090                 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1091
1092                 if (t->tx_buf == NULL)
1093                         chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1094                 else if (t->rx_buf == NULL)
1095                         chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1096
1097                 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1098                         /* Turbo mode is for more than one word */
1099                         if (t->len > ((cs->word_len + 7) >> 3))
1100                                 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1101                 }
1102
1103                 mcspi_write_chconf0(spi, chconf);
1104
1105                 if (t->len) {
1106                         unsigned        count;
1107
1108                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1109                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1110                                 omap2_mcspi_set_fifo(spi, t, 1);
1111
1112                         omap2_mcspi_set_enable(spi, 1);
1113
1114                         /* RX_ONLY mode needs dummy data in TX reg */
1115                         if (t->tx_buf == NULL)
1116                                 __raw_writel(0, cs->base
1117                                                 + OMAP2_MCSPI_TX0);
1118
1119                         if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1120                             (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1121                                 count = omap2_mcspi_txrx_dma(spi, t);
1122                         else
1123                                 count = omap2_mcspi_txrx_pio(spi, t);
1124                         m->actual_length += count;
1125
1126                         if (count != t->len) {
1127                                 status = -EIO;
1128                                 break;
1129                         }
1130                 }
1131
1132                 if (t->delay_usecs)
1133                         udelay(t->delay_usecs);
1134
1135                 /* ignore the "leave it on after last xfer" hint */
1136                 if (t->cs_change) {
1137                         omap2_mcspi_force_cs(spi, 0);
1138                         cs_active = 0;
1139                 }
1140
1141                 omap2_mcspi_set_enable(spi, 0);
1142
1143                 if (mcspi->fifo_depth > 0)
1144                         omap2_mcspi_set_fifo(spi, t, 0);
1145         }
1146         /* Restore defaults if they were overriden */
1147         if (par_override) {
1148                 par_override = 0;
1149                 status = omap2_mcspi_setup_transfer(spi, NULL);
1150         }
1151
1152         if (cs_active)
1153                 omap2_mcspi_force_cs(spi, 0);
1154
1155         if (cd && cd->cs_per_word) {
1156                 chconf = mcspi->ctx.modulctrl;
1157                 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1158                 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1159                 mcspi->ctx.modulctrl =
1160                         mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1161         }
1162
1163         omap2_mcspi_set_enable(spi, 0);
1164
1165         if (mcspi->fifo_depth > 0 && t)
1166                 omap2_mcspi_set_fifo(spi, t, 0);
1167
1168         m->status = status;
1169 }
1170
1171 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1172                 struct spi_message *m)
1173 {
1174         struct spi_device       *spi;
1175         struct omap2_mcspi      *mcspi;
1176         struct omap2_mcspi_dma  *mcspi_dma;
1177         struct spi_transfer     *t;
1178
1179         spi = m->spi;
1180         mcspi = spi_master_get_devdata(master);
1181         mcspi_dma = mcspi->dma_channels + spi->chip_select;
1182         m->actual_length = 0;
1183         m->status = 0;
1184
1185         /* reject invalid messages and transfers */
1186         if (list_empty(&m->transfers))
1187                 return -EINVAL;
1188         list_for_each_entry(t, &m->transfers, transfer_list) {
1189                 const void      *tx_buf = t->tx_buf;
1190                 void            *rx_buf = t->rx_buf;
1191                 unsigned        len = t->len;
1192
1193                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1194                                 || (len && !(rx_buf || tx_buf))
1195                                 || (t->bits_per_word &&
1196                                         (  t->bits_per_word < 4
1197                                            || t->bits_per_word > 32))) {
1198                         dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1199                                         t->speed_hz,
1200                                         len,
1201                                         tx_buf ? "tx" : "",
1202                                         rx_buf ? "rx" : "",
1203                                         t->bits_per_word);
1204                         return -EINVAL;
1205                 }
1206                 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1207                         dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1208                                         t->speed_hz,
1209                                         OMAP2_MCSPI_MAX_FREQ >> 15);
1210                         return -EINVAL;
1211                 }
1212
1213                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1214                         continue;
1215
1216                 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1217                         t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1218                                         len, DMA_TO_DEVICE);
1219                         if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1220                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1221                                                 'T', len);
1222                                 return -EINVAL;
1223                         }
1224                 }
1225                 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1226                         t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1227                                         DMA_FROM_DEVICE);
1228                         if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1229                                 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1230                                                 'R', len);
1231                                 if (tx_buf != NULL)
1232                                         dma_unmap_single(mcspi->dev, t->tx_dma,
1233                                                         len, DMA_TO_DEVICE);
1234                                 return -EINVAL;
1235                         }
1236                 }
1237         }
1238
1239         omap2_mcspi_work(mcspi, m);
1240         spi_finalize_current_message(master);
1241         return 0;
1242 }
1243
1244 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1245 {
1246         struct spi_master       *master = mcspi->master;
1247         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1248         int                     ret = 0;
1249
1250         ret = pm_runtime_get_sync(mcspi->dev);
1251         if (ret < 0)
1252                 return ret;
1253
1254         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1255                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1256         ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1257
1258         omap2_mcspi_set_master_mode(master);
1259         pm_runtime_mark_last_busy(mcspi->dev);
1260         pm_runtime_put_autosuspend(mcspi->dev);
1261         return 0;
1262 }
1263
1264 static int omap_mcspi_runtime_resume(struct device *dev)
1265 {
1266         struct omap2_mcspi      *mcspi;
1267         struct spi_master       *master;
1268
1269         master = dev_get_drvdata(dev);
1270         mcspi = spi_master_get_devdata(master);
1271         omap2_mcspi_restore_ctx(mcspi);
1272
1273         return 0;
1274 }
1275
1276 static struct omap2_mcspi_platform_config omap2_pdata = {
1277         .regs_offset = 0,
1278 };
1279
1280 static struct omap2_mcspi_platform_config omap4_pdata = {
1281         .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1282 };
1283
1284 static const struct of_device_id omap_mcspi_of_match[] = {
1285         {
1286                 .compatible = "ti,omap2-mcspi",
1287                 .data = &omap2_pdata,
1288         },
1289         {
1290                 .compatible = "ti,omap4-mcspi",
1291                 .data = &omap4_pdata,
1292         },
1293         { },
1294 };
1295 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1296
1297 static int omap2_mcspi_probe(struct platform_device *pdev)
1298 {
1299         struct spi_master       *master;
1300         const struct omap2_mcspi_platform_config *pdata;
1301         struct omap2_mcspi      *mcspi;
1302         struct resource         *r;
1303         int                     status = 0, i;
1304         u32                     regs_offset = 0;
1305         static int              bus_num = 1;
1306         struct device_node      *node = pdev->dev.of_node;
1307         const struct of_device_id *match;
1308
1309         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1310         if (master == NULL) {
1311                 dev_dbg(&pdev->dev, "master allocation failed\n");
1312                 return -ENOMEM;
1313         }
1314
1315         /* the spi->mode bits understood by this driver: */
1316         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1317
1318         master->setup = omap2_mcspi_setup;
1319         master->prepare_transfer_hardware = omap2_prepare_transfer;
1320         master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1321         master->transfer_one_message = omap2_mcspi_transfer_one_message;
1322         master->cleanup = omap2_mcspi_cleanup;
1323         master->dev.of_node = node;
1324
1325         dev_set_drvdata(&pdev->dev, master);
1326
1327         mcspi = spi_master_get_devdata(master);
1328         mcspi->master = master;
1329
1330         match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1331         if (match) {
1332                 u32 num_cs = 1; /* default number of chipselect */
1333                 pdata = match->data;
1334
1335                 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1336                 master->num_chipselect = num_cs;
1337                 master->bus_num = bus_num++;
1338                 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1339                         mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1340         } else {
1341                 pdata = pdev->dev.platform_data;
1342                 master->num_chipselect = pdata->num_cs;
1343                 if (pdev->id != -1)
1344                         master->bus_num = pdev->id;
1345                 mcspi->pin_dir = pdata->pin_dir;
1346         }
1347         regs_offset = pdata->regs_offset;
1348
1349         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1350         if (r == NULL) {
1351                 status = -ENODEV;
1352                 goto free_master;
1353         }
1354
1355         r->start += regs_offset;
1356         r->end += regs_offset;
1357         mcspi->phys = r->start;
1358
1359         mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1360         if (IS_ERR(mcspi->base)) {
1361                 status = PTR_ERR(mcspi->base);
1362                 goto free_master;
1363         }
1364
1365         mcspi->dev = &pdev->dev;
1366
1367         INIT_LIST_HEAD(&mcspi->ctx.cs);
1368
1369         mcspi->dma_channels = kcalloc(master->num_chipselect,
1370                         sizeof(struct omap2_mcspi_dma),
1371                         GFP_KERNEL);
1372
1373         if (mcspi->dma_channels == NULL)
1374                 goto free_master;
1375
1376         for (i = 0; i < master->num_chipselect; i++) {
1377                 char dma_ch_name[14];
1378                 struct resource *dma_res;
1379
1380                 sprintf(dma_ch_name, "rx%d", i);
1381                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1382                                 dma_ch_name);
1383                 if (!dma_res) {
1384                         dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1385                         status = -ENODEV;
1386                         break;
1387                 }
1388
1389                 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1390                 sprintf(dma_ch_name, "tx%d", i);
1391                 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1392                                 dma_ch_name);
1393                 if (!dma_res) {
1394                         dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1395                         status = -ENODEV;
1396                         break;
1397                 }
1398
1399                 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1400         }
1401
1402         if (status < 0)
1403                 goto dma_chnl_free;
1404
1405         pm_runtime_use_autosuspend(&pdev->dev);
1406         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1407         pm_runtime_enable(&pdev->dev);
1408
1409         status = omap2_mcspi_master_setup(mcspi);
1410         if (status < 0)
1411                 goto disable_pm;
1412
1413         status = spi_register_master(master);
1414         if (status < 0)
1415                 goto disable_pm;
1416
1417         return status;
1418
1419 disable_pm:
1420         pm_runtime_disable(&pdev->dev);
1421 dma_chnl_free:
1422         kfree(mcspi->dma_channels);
1423 free_master:
1424         spi_master_put(master);
1425         return status;
1426 }
1427
1428 static int omap2_mcspi_remove(struct platform_device *pdev)
1429 {
1430         struct spi_master       *master;
1431         struct omap2_mcspi      *mcspi;
1432         struct omap2_mcspi_dma  *dma_channels;
1433
1434         master = dev_get_drvdata(&pdev->dev);
1435         mcspi = spi_master_get_devdata(master);
1436         dma_channels = mcspi->dma_channels;
1437
1438         pm_runtime_put_sync(mcspi->dev);
1439         pm_runtime_disable(&pdev->dev);
1440
1441         spi_unregister_master(master);
1442         kfree(dma_channels);
1443
1444         return 0;
1445 }
1446
1447 /* work with hotplug and coldplug */
1448 MODULE_ALIAS("platform:omap2_mcspi");
1449
1450 #ifdef  CONFIG_SUSPEND
1451 /*
1452  * When SPI wake up from off-mode, CS is in activate state. If it was in
1453  * unactive state when driver was suspend, then force it to unactive state at
1454  * wake up.
1455  */
1456 static int omap2_mcspi_resume(struct device *dev)
1457 {
1458         struct spi_master       *master = dev_get_drvdata(dev);
1459         struct omap2_mcspi      *mcspi = spi_master_get_devdata(master);
1460         struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1461         struct omap2_mcspi_cs   *cs;
1462
1463         pm_runtime_get_sync(mcspi->dev);
1464         list_for_each_entry(cs, &ctx->cs, node) {
1465                 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1466                         /*
1467                          * We need to toggle CS state for OMAP take this
1468                          * change in account.
1469                          */
1470                         cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1471                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1472                         cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1473                         __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1474                 }
1475         }
1476         pm_runtime_mark_last_busy(mcspi->dev);
1477         pm_runtime_put_autosuspend(mcspi->dev);
1478         return 0;
1479 }
1480 #else
1481 #define omap2_mcspi_resume      NULL
1482 #endif
1483
1484 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1485         .resume = omap2_mcspi_resume,
1486         .runtime_resume = omap_mcspi_runtime_resume,
1487 };
1488
1489 static struct platform_driver omap2_mcspi_driver = {
1490         .driver = {
1491                 .name =         "omap2_mcspi",
1492                 .owner =        THIS_MODULE,
1493                 .pm =           &omap2_mcspi_pm_ops,
1494                 .of_match_table = omap_mcspi_of_match,
1495         },
1496         .probe =        omap2_mcspi_probe,
1497         .remove =       omap2_mcspi_remove,
1498 };
1499
1500 module_platform_driver(omap2_mcspi_driver);
1501 MODULE_LICENSE("GPL");