2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
40 #include <linux/of_device.h>
41 #include <linux/gcd.h>
43 #include <linux/spi/spi.h>
45 #include <linux/platform_data/spi-omap2-mcspi.h>
47 #define OMAP2_MCSPI_MAX_FREQ 48000000
48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50 #define SPI_AUTOSUSPEND_TIMEOUT 2000
52 #define OMAP2_MCSPI_REVISION 0x00
53 #define OMAP2_MCSPI_SYSSTATUS 0x14
54 #define OMAP2_MCSPI_IRQSTATUS 0x18
55 #define OMAP2_MCSPI_IRQENABLE 0x1c
56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
57 #define OMAP2_MCSPI_SYST 0x24
58 #define OMAP2_MCSPI_MODULCTRL 0x28
59 #define OMAP2_MCSPI_XFERLEVEL 0x7c
61 /* per-channel banks, 0x14 bytes each, first is: */
62 #define OMAP2_MCSPI_CHCONF0 0x2c
63 #define OMAP2_MCSPI_CHSTAT0 0x30
64 #define OMAP2_MCSPI_CHCTRL0 0x34
65 #define OMAP2_MCSPI_TX0 0x38
66 #define OMAP2_MCSPI_RX0 0x3c
68 /* per-register bitmasks: */
69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
76 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
87 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
96 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
98 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
100 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
102 /* We have 2 DMA channels per CS, one for RX and one for TX */
103 struct omap2_mcspi_dma {
104 struct dma_chan *dma_tx;
105 struct dma_chan *dma_rx;
110 struct completion dma_tx_completion;
111 struct completion dma_rx_completion;
113 char dma_rx_ch_name[14];
114 char dma_tx_ch_name[14];
117 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
118 * cache operations; better heuristics consider wordsize and bitrate.
120 #define DMA_MIN_BYTES 160
124 * Used for context save and restore, structure members to be updated whenever
125 * corresponding registers are modified.
127 struct omap2_mcspi_regs {
134 struct spi_master *master;
135 /* Virtual base address of the controller */
138 /* SPI1 has 4 channels, while SPI2 has 2 */
139 struct omap2_mcspi_dma *dma_channels;
141 struct omap2_mcspi_regs ctx;
143 unsigned int pin_dir:1;
146 struct omap2_mcspi_cs {
150 struct list_head node;
151 /* Context save and restore shadow register */
155 static inline void mcspi_write_reg(struct spi_master *master,
158 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
160 __raw_writel(val, mcspi->base + idx);
163 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
165 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
167 return __raw_readl(mcspi->base + idx);
170 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
173 struct omap2_mcspi_cs *cs = spi->controller_state;
175 __raw_writel(val, cs->base + idx);
178 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
180 struct omap2_mcspi_cs *cs = spi->controller_state;
182 return __raw_readl(cs->base + idx);
185 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
187 struct omap2_mcspi_cs *cs = spi->controller_state;
192 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
194 struct omap2_mcspi_cs *cs = spi->controller_state;
197 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
198 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
201 static inline int mcspi_bytes_per_word(int word_len)
205 else if (word_len <= 16)
207 else /* word_len <= 32 */
211 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
212 int is_read, int enable)
216 l = mcspi_cached_chconf0(spi);
218 if (is_read) /* 1 is read, 0 write */
219 rw = OMAP2_MCSPI_CHCONF_DMAR;
221 rw = OMAP2_MCSPI_CHCONF_DMAW;
228 mcspi_write_chconf0(spi, l);
231 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
235 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
236 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
237 /* Flash post-writes */
238 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
241 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
245 l = mcspi_cached_chconf0(spi);
247 l |= OMAP2_MCSPI_CHCONF_FORCE;
249 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
251 mcspi_write_chconf0(spi, l);
254 static void omap2_mcspi_set_master_mode(struct spi_master *master)
256 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
257 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
261 * Setup when switching from (reset default) slave mode
262 * to single-channel master mode
264 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
265 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
266 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
267 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
272 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
273 struct spi_transfer *t, int enable)
275 struct spi_master *master = spi->master;
276 struct omap2_mcspi_cs *cs = spi->controller_state;
277 struct omap2_mcspi *mcspi;
279 int fifo_depth, bytes_per_word;
280 u32 chconf, xferlevel;
282 mcspi = spi_master_get_devdata(master);
284 chconf = mcspi_cached_chconf0(spi);
286 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
287 if (t->len % bytes_per_word != 0)
290 fifo_depth = gcd(t->len, OMAP2_MCSPI_MAX_FIFODEPTH);
291 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
294 wcnt = t->len / bytes_per_word;
295 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
298 xferlevel = wcnt << 16;
299 if (t->rx_buf != NULL) {
300 chconf |= OMAP2_MCSPI_CHCONF_FFER;
301 xferlevel |= (fifo_depth - 1) << 8;
303 chconf |= OMAP2_MCSPI_CHCONF_FFET;
304 xferlevel |= fifo_depth - 1;
307 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
308 mcspi_write_chconf0(spi, chconf);
309 mcspi->fifo_depth = fifo_depth;
315 if (t->rx_buf != NULL)
316 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
318 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
320 mcspi_write_chconf0(spi, chconf);
321 mcspi->fifo_depth = 0;
324 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
326 struct spi_master *spi_cntrl = mcspi->master;
327 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
328 struct omap2_mcspi_cs *cs;
330 /* McSPI: context restore */
331 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
332 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
334 list_for_each_entry(cs, &ctx->cs, node)
335 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
338 static int omap2_prepare_transfer(struct spi_master *master)
340 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
342 pm_runtime_get_sync(mcspi->dev);
346 static int omap2_unprepare_transfer(struct spi_master *master)
348 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
350 pm_runtime_mark_last_busy(mcspi->dev);
351 pm_runtime_put_autosuspend(mcspi->dev);
355 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
357 unsigned long timeout;
359 timeout = jiffies + msecs_to_jiffies(1000);
360 while (!(__raw_readl(reg) & bit)) {
361 if (time_after(jiffies, timeout)) {
362 if (!(__raw_readl(reg) & bit))
372 static void omap2_mcspi_rx_callback(void *data)
374 struct spi_device *spi = data;
375 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
376 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
378 /* We must disable the DMA RX request */
379 omap2_mcspi_set_dma_req(spi, 1, 0);
381 complete(&mcspi_dma->dma_rx_completion);
384 static void omap2_mcspi_tx_callback(void *data)
386 struct spi_device *spi = data;
387 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
388 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
390 /* We must disable the DMA TX request */
391 omap2_mcspi_set_dma_req(spi, 0, 0);
393 complete(&mcspi_dma->dma_tx_completion);
396 static void omap2_mcspi_tx_dma(struct spi_device *spi,
397 struct spi_transfer *xfer,
398 struct dma_slave_config cfg)
400 struct omap2_mcspi *mcspi;
401 struct omap2_mcspi_dma *mcspi_dma;
404 mcspi = spi_master_get_devdata(spi->master);
405 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
408 if (mcspi_dma->dma_tx) {
409 struct dma_async_tx_descriptor *tx;
410 struct scatterlist sg;
412 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
414 sg_init_table(&sg, 1);
415 sg_dma_address(&sg) = xfer->tx_dma;
416 sg_dma_len(&sg) = xfer->len;
418 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
419 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
421 tx->callback = omap2_mcspi_tx_callback;
422 tx->callback_param = spi;
423 dmaengine_submit(tx);
425 /* FIXME: fall back to PIO? */
428 dma_async_issue_pending(mcspi_dma->dma_tx);
429 omap2_mcspi_set_dma_req(spi, 0, 1);
434 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
435 struct dma_slave_config cfg,
438 struct omap2_mcspi *mcspi;
439 struct omap2_mcspi_dma *mcspi_dma;
440 unsigned int count, dma_count;
443 int word_len, element_count;
444 struct omap2_mcspi_cs *cs = spi->controller_state;
445 mcspi = spi_master_get_devdata(spi->master);
446 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
448 dma_count = xfer->len;
450 if (mcspi->fifo_depth == 0)
453 word_len = cs->word_len;
454 l = mcspi_cached_chconf0(spi);
457 element_count = count;
458 else if (word_len <= 16)
459 element_count = count >> 1;
460 else /* word_len <= 32 */
461 element_count = count >> 2;
463 if (mcspi_dma->dma_rx) {
464 struct dma_async_tx_descriptor *tx;
465 struct scatterlist sg;
467 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
469 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
472 sg_init_table(&sg, 1);
473 sg_dma_address(&sg) = xfer->rx_dma;
474 sg_dma_len(&sg) = dma_count;
476 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
477 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
480 tx->callback = omap2_mcspi_rx_callback;
481 tx->callback_param = spi;
482 dmaengine_submit(tx);
484 /* FIXME: fall back to PIO? */
488 dma_async_issue_pending(mcspi_dma->dma_rx);
489 omap2_mcspi_set_dma_req(spi, 1, 1);
491 wait_for_completion(&mcspi_dma->dma_rx_completion);
492 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
495 if (mcspi->fifo_depth > 0)
498 omap2_mcspi_set_enable(spi, 0);
500 elements = element_count - 1;
502 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
505 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
506 & OMAP2_MCSPI_CHSTAT_RXS)) {
509 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
511 ((u8 *)xfer->rx_buf)[elements++] = w;
512 else if (word_len <= 16)
513 ((u16 *)xfer->rx_buf)[elements++] = w;
514 else /* word_len <= 32 */
515 ((u32 *)xfer->rx_buf)[elements++] = w;
517 int bytes_per_word = mcspi_bytes_per_word(word_len);
518 dev_err(&spi->dev, "DMA RX penultimate word empty");
519 count -= (bytes_per_word << 1);
520 omap2_mcspi_set_enable(spi, 1);
524 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
525 & OMAP2_MCSPI_CHSTAT_RXS)) {
528 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
530 ((u8 *)xfer->rx_buf)[elements] = w;
531 else if (word_len <= 16)
532 ((u16 *)xfer->rx_buf)[elements] = w;
533 else /* word_len <= 32 */
534 ((u32 *)xfer->rx_buf)[elements] = w;
536 dev_err(&spi->dev, "DMA RX last word empty");
537 count -= mcspi_bytes_per_word(word_len);
539 omap2_mcspi_set_enable(spi, 1);
544 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
546 struct omap2_mcspi *mcspi;
547 struct omap2_mcspi_cs *cs = spi->controller_state;
548 struct omap2_mcspi_dma *mcspi_dma;
553 struct dma_slave_config cfg;
554 enum dma_slave_buswidth width;
557 void __iomem *chstat_reg;
558 void __iomem *irqstat_reg;
561 mcspi = spi_master_get_devdata(spi->master);
562 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
563 l = mcspi_cached_chconf0(spi);
566 if (cs->word_len <= 8) {
567 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
569 } else if (cs->word_len <= 16) {
570 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
573 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
580 if (mcspi->fifo_depth > 0) {
581 if (count > mcspi->fifo_depth)
582 burst = mcspi->fifo_depth / es;
587 memset(&cfg, 0, sizeof(cfg));
588 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
589 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
590 cfg.src_addr_width = width;
591 cfg.dst_addr_width = width;
592 cfg.src_maxburst = burst;
593 cfg.dst_maxburst = burst;
599 omap2_mcspi_tx_dma(spi, xfer, cfg);
602 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
605 wait_for_completion(&mcspi_dma->dma_tx_completion);
606 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
609 if (mcspi->fifo_depth > 0) {
610 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
612 if (mcspi_wait_for_reg_bit(irqstat_reg,
613 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
614 dev_err(&spi->dev, "EOW timed out\n");
616 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
617 OMAP2_MCSPI_IRQSTATUS_EOW);
620 /* for TX_ONLY mode, be sure all words have shifted out */
622 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
623 if (mcspi->fifo_depth > 0) {
624 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
625 OMAP2_MCSPI_CHSTAT_TXFFE);
627 dev_err(&spi->dev, "TXFFE timed out\n");
629 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
630 OMAP2_MCSPI_CHSTAT_TXS);
632 dev_err(&spi->dev, "TXS timed out\n");
635 (mcspi_wait_for_reg_bit(chstat_reg,
636 OMAP2_MCSPI_CHSTAT_EOT) < 0))
637 dev_err(&spi->dev, "EOT timed out\n");
644 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
646 struct omap2_mcspi *mcspi;
647 struct omap2_mcspi_cs *cs = spi->controller_state;
648 unsigned int count, c;
650 void __iomem *base = cs->base;
651 void __iomem *tx_reg;
652 void __iomem *rx_reg;
653 void __iomem *chstat_reg;
656 mcspi = spi_master_get_devdata(spi->master);
659 word_len = cs->word_len;
661 l = mcspi_cached_chconf0(spi);
663 /* We store the pre-calculated register addresses on stack to speed
664 * up the transfer loop. */
665 tx_reg = base + OMAP2_MCSPI_TX0;
666 rx_reg = base + OMAP2_MCSPI_RX0;
667 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
669 if (c < (word_len>>3))
682 if (mcspi_wait_for_reg_bit(chstat_reg,
683 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
684 dev_err(&spi->dev, "TXS timed out\n");
687 dev_vdbg(&spi->dev, "write-%d %02x\n",
689 __raw_writel(*tx++, tx_reg);
692 if (mcspi_wait_for_reg_bit(chstat_reg,
693 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
694 dev_err(&spi->dev, "RXS timed out\n");
698 if (c == 1 && tx == NULL &&
699 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
700 omap2_mcspi_set_enable(spi, 0);
701 *rx++ = __raw_readl(rx_reg);
702 dev_vdbg(&spi->dev, "read-%d %02x\n",
703 word_len, *(rx - 1));
704 if (mcspi_wait_for_reg_bit(chstat_reg,
705 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
711 } else if (c == 0 && tx == NULL) {
712 omap2_mcspi_set_enable(spi, 0);
715 *rx++ = __raw_readl(rx_reg);
716 dev_vdbg(&spi->dev, "read-%d %02x\n",
717 word_len, *(rx - 1));
720 } else if (word_len <= 16) {
729 if (mcspi_wait_for_reg_bit(chstat_reg,
730 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
731 dev_err(&spi->dev, "TXS timed out\n");
734 dev_vdbg(&spi->dev, "write-%d %04x\n",
736 __raw_writel(*tx++, tx_reg);
739 if (mcspi_wait_for_reg_bit(chstat_reg,
740 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
741 dev_err(&spi->dev, "RXS timed out\n");
745 if (c == 2 && tx == NULL &&
746 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
747 omap2_mcspi_set_enable(spi, 0);
748 *rx++ = __raw_readl(rx_reg);
749 dev_vdbg(&spi->dev, "read-%d %04x\n",
750 word_len, *(rx - 1));
751 if (mcspi_wait_for_reg_bit(chstat_reg,
752 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
758 } else if (c == 0 && tx == NULL) {
759 omap2_mcspi_set_enable(spi, 0);
762 *rx++ = __raw_readl(rx_reg);
763 dev_vdbg(&spi->dev, "read-%d %04x\n",
764 word_len, *(rx - 1));
767 } else if (word_len <= 32) {
776 if (mcspi_wait_for_reg_bit(chstat_reg,
777 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
778 dev_err(&spi->dev, "TXS timed out\n");
781 dev_vdbg(&spi->dev, "write-%d %08x\n",
783 __raw_writel(*tx++, tx_reg);
786 if (mcspi_wait_for_reg_bit(chstat_reg,
787 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
788 dev_err(&spi->dev, "RXS timed out\n");
792 if (c == 4 && tx == NULL &&
793 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
794 omap2_mcspi_set_enable(spi, 0);
795 *rx++ = __raw_readl(rx_reg);
796 dev_vdbg(&spi->dev, "read-%d %08x\n",
797 word_len, *(rx - 1));
798 if (mcspi_wait_for_reg_bit(chstat_reg,
799 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
805 } else if (c == 0 && tx == NULL) {
806 omap2_mcspi_set_enable(spi, 0);
809 *rx++ = __raw_readl(rx_reg);
810 dev_vdbg(&spi->dev, "read-%d %08x\n",
811 word_len, *(rx - 1));
816 /* for TX_ONLY mode, be sure all words have shifted out */
817 if (xfer->rx_buf == NULL) {
818 if (mcspi_wait_for_reg_bit(chstat_reg,
819 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
820 dev_err(&spi->dev, "TXS timed out\n");
821 } else if (mcspi_wait_for_reg_bit(chstat_reg,
822 OMAP2_MCSPI_CHSTAT_EOT) < 0)
823 dev_err(&spi->dev, "EOT timed out\n");
825 /* disable chan to purge rx datas received in TX_ONLY transfer,
826 * otherwise these rx datas will affect the direct following
829 omap2_mcspi_set_enable(spi, 0);
832 omap2_mcspi_set_enable(spi, 1);
836 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
840 for (div = 0; div < 15; div++)
841 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
847 /* called only when no transfer is active to this device */
848 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
849 struct spi_transfer *t)
851 struct omap2_mcspi_cs *cs = spi->controller_state;
852 struct omap2_mcspi *mcspi;
853 struct spi_master *spi_cntrl;
855 u8 word_len = spi->bits_per_word;
856 u32 speed_hz = spi->max_speed_hz;
858 mcspi = spi_master_get_devdata(spi->master);
859 spi_cntrl = mcspi->master;
861 if (t != NULL && t->bits_per_word)
862 word_len = t->bits_per_word;
864 cs->word_len = word_len;
866 if (t && t->speed_hz)
867 speed_hz = t->speed_hz;
869 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
870 div = omap2_mcspi_calc_divisor(speed_hz);
872 l = mcspi_cached_chconf0(spi);
874 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
875 * REVISIT: this controller could support SPI_3WIRE mode.
877 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
878 l &= ~OMAP2_MCSPI_CHCONF_IS;
879 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
880 l |= OMAP2_MCSPI_CHCONF_DPE0;
882 l |= OMAP2_MCSPI_CHCONF_IS;
883 l |= OMAP2_MCSPI_CHCONF_DPE1;
884 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
888 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
889 l |= (word_len - 1) << 7;
891 /* set chipselect polarity; manage with FORCE */
892 if (!(spi->mode & SPI_CS_HIGH))
893 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
895 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
897 /* set clock divisor */
898 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
901 /* set SPI mode 0..3 */
902 if (spi->mode & SPI_CPOL)
903 l |= OMAP2_MCSPI_CHCONF_POL;
905 l &= ~OMAP2_MCSPI_CHCONF_POL;
906 if (spi->mode & SPI_CPHA)
907 l |= OMAP2_MCSPI_CHCONF_PHA;
909 l &= ~OMAP2_MCSPI_CHCONF_PHA;
911 mcspi_write_chconf0(spi, l);
913 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
914 OMAP2_MCSPI_MAX_FREQ >> div,
915 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
916 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
922 * Note that we currently allow DMA only if we get a channel
923 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
925 static int omap2_mcspi_request_dma(struct spi_device *spi)
927 struct spi_master *master = spi->master;
928 struct omap2_mcspi *mcspi;
929 struct omap2_mcspi_dma *mcspi_dma;
933 mcspi = spi_master_get_devdata(master);
934 mcspi_dma = mcspi->dma_channels + spi->chip_select;
936 init_completion(&mcspi_dma->dma_rx_completion);
937 init_completion(&mcspi_dma->dma_tx_completion);
940 dma_cap_set(DMA_SLAVE, mask);
941 sig = mcspi_dma->dma_rx_sync_dev;
944 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
946 mcspi_dma->dma_rx_ch_name);
947 if (!mcspi_dma->dma_rx)
950 sig = mcspi_dma->dma_tx_sync_dev;
952 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
954 mcspi_dma->dma_tx_ch_name);
956 if (!mcspi_dma->dma_tx) {
957 dma_release_channel(mcspi_dma->dma_rx);
958 mcspi_dma->dma_rx = NULL;
965 dev_warn(&spi->dev, "not using DMA for McSPI\n");
969 static int omap2_mcspi_setup(struct spi_device *spi)
972 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
973 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
974 struct omap2_mcspi_dma *mcspi_dma;
975 struct omap2_mcspi_cs *cs = spi->controller_state;
977 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
978 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
983 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
986 cs = kzalloc(sizeof *cs, GFP_KERNEL);
989 cs->base = mcspi->base + spi->chip_select * 0x14;
990 cs->phys = mcspi->phys + spi->chip_select * 0x14;
992 spi->controller_state = cs;
993 /* Link this to context save list */
994 list_add_tail(&cs->node, &ctx->cs);
997 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
998 ret = omap2_mcspi_request_dma(spi);
999 if (ret < 0 && ret != -EAGAIN)
1003 ret = pm_runtime_get_sync(mcspi->dev);
1007 ret = omap2_mcspi_setup_transfer(spi, NULL);
1008 pm_runtime_mark_last_busy(mcspi->dev);
1009 pm_runtime_put_autosuspend(mcspi->dev);
1014 static void omap2_mcspi_cleanup(struct spi_device *spi)
1016 struct omap2_mcspi *mcspi;
1017 struct omap2_mcspi_dma *mcspi_dma;
1018 struct omap2_mcspi_cs *cs;
1020 mcspi = spi_master_get_devdata(spi->master);
1022 if (spi->controller_state) {
1023 /* Unlink controller state from context save list */
1024 cs = spi->controller_state;
1025 list_del(&cs->node);
1030 if (spi->chip_select < spi->master->num_chipselect) {
1031 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1033 if (mcspi_dma->dma_rx) {
1034 dma_release_channel(mcspi_dma->dma_rx);
1035 mcspi_dma->dma_rx = NULL;
1037 if (mcspi_dma->dma_tx) {
1038 dma_release_channel(mcspi_dma->dma_tx);
1039 mcspi_dma->dma_tx = NULL;
1044 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
1047 /* We only enable one channel at a time -- the one whose message is
1048 * -- although this controller would gladly
1049 * arbitrate among multiple channels. This corresponds to "single
1050 * channel" master mode. As a side effect, we need to manage the
1051 * chipselect with the FORCE bit ... CS != channel enable.
1054 struct spi_device *spi;
1055 struct spi_transfer *t = NULL;
1056 struct spi_master *master;
1057 struct omap2_mcspi_dma *mcspi_dma;
1059 struct omap2_mcspi_cs *cs;
1060 struct omap2_mcspi_device_config *cd;
1061 int par_override = 0;
1066 master = spi->master;
1067 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1068 cs = spi->controller_state;
1069 cd = spi->controller_data;
1071 omap2_mcspi_set_enable(spi, 0);
1072 list_for_each_entry(t, &m->transfers, transfer_list) {
1073 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
1077 if (par_override || t->speed_hz || t->bits_per_word) {
1079 status = omap2_mcspi_setup_transfer(spi, t);
1082 if (!t->speed_hz && !t->bits_per_word)
1085 if (cd && cd->cs_per_word) {
1086 chconf = mcspi->ctx.modulctrl;
1087 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1088 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1089 mcspi->ctx.modulctrl =
1090 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1095 omap2_mcspi_force_cs(spi, 1);
1099 chconf = mcspi_cached_chconf0(spi);
1100 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1101 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1103 if (t->tx_buf == NULL)
1104 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1105 else if (t->rx_buf == NULL)
1106 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1108 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1109 /* Turbo mode is for more than one word */
1110 if (t->len > ((cs->word_len + 7) >> 3))
1111 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1114 mcspi_write_chconf0(spi, chconf);
1119 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1120 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1121 omap2_mcspi_set_fifo(spi, t, 1);
1123 omap2_mcspi_set_enable(spi, 1);
1125 /* RX_ONLY mode needs dummy data in TX reg */
1126 if (t->tx_buf == NULL)
1127 __raw_writel(0, cs->base
1130 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1131 (m->is_dma_mapped || t->len >= DMA_MIN_BYTES))
1132 count = omap2_mcspi_txrx_dma(spi, t);
1134 count = omap2_mcspi_txrx_pio(spi, t);
1135 m->actual_length += count;
1137 if (count != t->len) {
1144 udelay(t->delay_usecs);
1146 /* ignore the "leave it on after last xfer" hint */
1148 omap2_mcspi_force_cs(spi, 0);
1152 omap2_mcspi_set_enable(spi, 0);
1154 if (mcspi->fifo_depth > 0)
1155 omap2_mcspi_set_fifo(spi, t, 0);
1157 /* Restore defaults if they were overriden */
1160 status = omap2_mcspi_setup_transfer(spi, NULL);
1164 omap2_mcspi_force_cs(spi, 0);
1166 if (cd && cd->cs_per_word) {
1167 chconf = mcspi->ctx.modulctrl;
1168 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1169 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1170 mcspi->ctx.modulctrl =
1171 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1174 omap2_mcspi_set_enable(spi, 0);
1176 if (mcspi->fifo_depth > 0 && t)
1177 omap2_mcspi_set_fifo(spi, t, 0);
1182 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1183 struct spi_message *m)
1185 struct spi_device *spi;
1186 struct omap2_mcspi *mcspi;
1187 struct omap2_mcspi_dma *mcspi_dma;
1188 struct spi_transfer *t;
1191 mcspi = spi_master_get_devdata(master);
1192 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1193 m->actual_length = 0;
1196 /* reject invalid messages and transfers */
1197 if (list_empty(&m->transfers))
1199 list_for_each_entry(t, &m->transfers, transfer_list) {
1200 const void *tx_buf = t->tx_buf;
1201 void *rx_buf = t->rx_buf;
1202 unsigned len = t->len;
1204 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1205 || (len && !(rx_buf || tx_buf))
1206 || (t->bits_per_word &&
1207 ( t->bits_per_word < 4
1208 || t->bits_per_word > 32))) {
1209 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1217 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1218 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1220 OMAP2_MCSPI_MAX_FREQ >> 15);
1224 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1227 if (mcspi_dma->dma_tx && tx_buf != NULL) {
1228 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1229 len, DMA_TO_DEVICE);
1230 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1231 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1236 if (mcspi_dma->dma_rx && rx_buf != NULL) {
1237 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1239 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1240 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1243 dma_unmap_single(mcspi->dev, t->tx_dma,
1244 len, DMA_TO_DEVICE);
1250 omap2_mcspi_work(mcspi, m);
1251 spi_finalize_current_message(master);
1255 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1257 struct spi_master *master = mcspi->master;
1258 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1261 ret = pm_runtime_get_sync(mcspi->dev);
1265 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1266 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1267 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1269 omap2_mcspi_set_master_mode(master);
1270 pm_runtime_mark_last_busy(mcspi->dev);
1271 pm_runtime_put_autosuspend(mcspi->dev);
1275 static int omap_mcspi_runtime_resume(struct device *dev)
1277 struct omap2_mcspi *mcspi;
1278 struct spi_master *master;
1280 master = dev_get_drvdata(dev);
1281 mcspi = spi_master_get_devdata(master);
1282 omap2_mcspi_restore_ctx(mcspi);
1287 static struct omap2_mcspi_platform_config omap2_pdata = {
1291 static struct omap2_mcspi_platform_config omap4_pdata = {
1292 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1295 static const struct of_device_id omap_mcspi_of_match[] = {
1297 .compatible = "ti,omap2-mcspi",
1298 .data = &omap2_pdata,
1301 .compatible = "ti,omap4-mcspi",
1302 .data = &omap4_pdata,
1306 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1308 static int omap2_mcspi_probe(struct platform_device *pdev)
1310 struct spi_master *master;
1311 const struct omap2_mcspi_platform_config *pdata;
1312 struct omap2_mcspi *mcspi;
1315 u32 regs_offset = 0;
1316 static int bus_num = 1;
1317 struct device_node *node = pdev->dev.of_node;
1318 const struct of_device_id *match;
1320 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1321 if (master == NULL) {
1322 dev_dbg(&pdev->dev, "master allocation failed\n");
1326 /* the spi->mode bits understood by this driver: */
1327 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1329 master->setup = omap2_mcspi_setup;
1330 master->prepare_transfer_hardware = omap2_prepare_transfer;
1331 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1332 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1333 master->cleanup = omap2_mcspi_cleanup;
1334 master->dev.of_node = node;
1336 dev_set_drvdata(&pdev->dev, master);
1338 mcspi = spi_master_get_devdata(master);
1339 mcspi->master = master;
1341 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1343 u32 num_cs = 1; /* default number of chipselect */
1344 pdata = match->data;
1346 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1347 master->num_chipselect = num_cs;
1348 master->bus_num = bus_num++;
1349 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1350 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1352 pdata = pdev->dev.platform_data;
1353 master->num_chipselect = pdata->num_cs;
1355 master->bus_num = pdev->id;
1356 mcspi->pin_dir = pdata->pin_dir;
1358 regs_offset = pdata->regs_offset;
1360 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1366 r->start += regs_offset;
1367 r->end += regs_offset;
1368 mcspi->phys = r->start;
1370 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1371 if (IS_ERR(mcspi->base)) {
1372 status = PTR_ERR(mcspi->base);
1376 mcspi->dev = &pdev->dev;
1378 INIT_LIST_HEAD(&mcspi->ctx.cs);
1380 mcspi->dma_channels = kcalloc(master->num_chipselect,
1381 sizeof(struct omap2_mcspi_dma),
1384 if (mcspi->dma_channels == NULL)
1387 for (i = 0; i < master->num_chipselect; i++) {
1388 char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name;
1389 char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name;
1390 struct resource *dma_res;
1392 sprintf(dma_rx_ch_name, "rx%d", i);
1393 if (!pdev->dev.of_node) {
1395 platform_get_resource_byname(pdev,
1400 "cannot get DMA RX channel\n");
1405 mcspi->dma_channels[i].dma_rx_sync_dev =
1408 sprintf(dma_tx_ch_name, "tx%d", i);
1409 if (!pdev->dev.of_node) {
1411 platform_get_resource_byname(pdev,
1416 "cannot get DMA TX channel\n");
1421 mcspi->dma_channels[i].dma_tx_sync_dev =
1429 pm_runtime_use_autosuspend(&pdev->dev);
1430 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1431 pm_runtime_enable(&pdev->dev);
1433 status = omap2_mcspi_master_setup(mcspi);
1437 status = spi_register_master(master);
1444 pm_runtime_disable(&pdev->dev);
1446 kfree(mcspi->dma_channels);
1448 spi_master_put(master);
1452 static int omap2_mcspi_remove(struct platform_device *pdev)
1454 struct spi_master *master;
1455 struct omap2_mcspi *mcspi;
1456 struct omap2_mcspi_dma *dma_channels;
1458 master = dev_get_drvdata(&pdev->dev);
1459 mcspi = spi_master_get_devdata(master);
1460 dma_channels = mcspi->dma_channels;
1462 pm_runtime_put_sync(mcspi->dev);
1463 pm_runtime_disable(&pdev->dev);
1465 spi_unregister_master(master);
1466 kfree(dma_channels);
1471 /* work with hotplug and coldplug */
1472 MODULE_ALIAS("platform:omap2_mcspi");
1474 #ifdef CONFIG_SUSPEND
1476 * When SPI wake up from off-mode, CS is in activate state. If it was in
1477 * unactive state when driver was suspend, then force it to unactive state at
1480 static int omap2_mcspi_resume(struct device *dev)
1482 struct spi_master *master = dev_get_drvdata(dev);
1483 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1484 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1485 struct omap2_mcspi_cs *cs;
1487 pm_runtime_get_sync(mcspi->dev);
1488 list_for_each_entry(cs, &ctx->cs, node) {
1489 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1491 * We need to toggle CS state for OMAP take this
1492 * change in account.
1494 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1495 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1496 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1497 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1500 pm_runtime_mark_last_busy(mcspi->dev);
1501 pm_runtime_put_autosuspend(mcspi->dev);
1505 #define omap2_mcspi_resume NULL
1508 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1509 .resume = omap2_mcspi_resume,
1510 .runtime_resume = omap_mcspi_runtime_resume,
1513 static struct platform_driver omap2_mcspi_driver = {
1515 .name = "omap2_mcspi",
1516 .owner = THIS_MODULE,
1517 .pm = &omap2_mcspi_pm_ops,
1518 .of_match_table = omap_mcspi_of_match,
1520 .probe = omap2_mcspi_probe,
1521 .remove = omap2_mcspi_remove,
1524 module_platform_driver(omap2_mcspi_driver);
1525 MODULE_LICENSE("GPL");