2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/of_device.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24 #include <asm/unaligned.h>
26 #define DRIVER_NAME "orion_spi"
28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
29 #define SPI_AUTOSUSPEND_TIMEOUT 200
31 #define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
32 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
34 #define ORION_SPI_IF_CTRL_REG 0x00
35 #define ORION_SPI_IF_CONFIG_REG 0x04
36 #define ORION_SPI_DATA_OUT_REG 0x08
37 #define ORION_SPI_DATA_IN_REG 0x0c
38 #define ORION_SPI_INT_CAUSE_REG 0x10
40 #define ORION_SPI_MODE_CPOL (1 << 11)
41 #define ORION_SPI_MODE_CPHA (1 << 12)
42 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
43 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
44 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
45 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
53 struct orion_spi_dev {
54 enum orion_spi_type typ;
55 unsigned int min_divisor;
56 unsigned int max_divisor;
61 struct spi_master *master;
64 const struct orion_spi_dev *devdata;
67 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
69 return orion_spi->base + reg;
73 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
75 void __iomem *reg_addr = spi_reg(orion_spi, reg);
78 val = readl(reg_addr);
80 writel(val, reg_addr);
84 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
86 void __iomem *reg_addr = spi_reg(orion_spi, reg);
89 val = readl(reg_addr);
91 writel(val, reg_addr);
94 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
100 struct orion_spi *orion_spi;
101 const struct orion_spi_dev *devdata;
103 orion_spi = spi_master_get_devdata(spi->master);
104 devdata = orion_spi->devdata;
106 tclk_hz = clk_get_rate(orion_spi->clk);
108 if (devdata->typ == ARMADA_SPI) {
109 unsigned int clk, spr, sppr, sppr2, err;
110 unsigned int best_spr, best_sppr, best_err;
116 /* Iterate over the valid range looking for best fit */
117 for (sppr = 0; sppr < 8; sppr++) {
120 spr = tclk_hz / sppr2;
121 spr = DIV_ROUND_UP(spr, speed);
122 if ((spr == 0) || (spr > 15))
125 clk = tclk_hz / (spr * sppr2);
128 if (err < best_err) {
135 if ((best_sppr == 0) && (best_spr == 0))
138 prescale = ((best_sppr & 0x6) << 5) |
139 ((best_sppr & 0x1) << 4) | best_spr;
142 * the supported rates are: 4,6,8...30
143 * round up as we look for equal or less speed
145 rate = DIV_ROUND_UP(tclk_hz, speed);
146 rate = roundup(rate, 2);
148 /* check if requested speed is too small */
155 /* Convert the rate to SPI clock divisor value. */
156 prescale = 0x10 + rate/2;
159 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
160 reg = ((reg & ~devdata->prescale_mask) | prescale);
161 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
167 orion_spi_mode_set(struct spi_device *spi)
170 struct orion_spi *orion_spi;
172 orion_spi = spi_master_get_devdata(spi->master);
174 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
175 reg &= ~ORION_SPI_MODE_MASK;
176 if (spi->mode & SPI_CPOL)
177 reg |= ORION_SPI_MODE_CPOL;
178 if (spi->mode & SPI_CPHA)
179 reg |= ORION_SPI_MODE_CPHA;
180 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
184 * called only when no transfer is active on the bus
187 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
189 struct orion_spi *orion_spi;
190 unsigned int speed = spi->max_speed_hz;
191 unsigned int bits_per_word = spi->bits_per_word;
194 orion_spi = spi_master_get_devdata(spi->master);
196 if ((t != NULL) && t->speed_hz)
199 if ((t != NULL) && t->bits_per_word)
200 bits_per_word = t->bits_per_word;
202 orion_spi_mode_set(spi);
204 rc = orion_spi_baudrate_set(spi, speed);
208 if (bits_per_word == 16)
209 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
210 ORION_SPI_IF_8_16_BIT_MODE);
212 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
213 ORION_SPI_IF_8_16_BIT_MODE);
218 static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
221 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
223 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
226 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
230 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
231 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
241 orion_spi_write_read_8bit(struct spi_device *spi,
242 const u8 **tx_buf, u8 **rx_buf)
244 void __iomem *tx_reg, *rx_reg, *int_reg;
245 struct orion_spi *orion_spi;
247 orion_spi = spi_master_get_devdata(spi->master);
248 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
249 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
250 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
252 /* clear the interrupt cause register */
253 writel(0x0, int_reg);
255 if (tx_buf && *tx_buf)
256 writel(*(*tx_buf)++, tx_reg);
260 if (orion_spi_wait_till_ready(orion_spi) < 0) {
261 dev_err(&spi->dev, "TXS timed out\n");
265 if (rx_buf && *rx_buf)
266 *(*rx_buf)++ = readl(rx_reg);
272 orion_spi_write_read_16bit(struct spi_device *spi,
273 const u16 **tx_buf, u16 **rx_buf)
275 void __iomem *tx_reg, *rx_reg, *int_reg;
276 struct orion_spi *orion_spi;
278 orion_spi = spi_master_get_devdata(spi->master);
279 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
280 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
281 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
283 /* clear the interrupt cause register */
284 writel(0x0, int_reg);
286 if (tx_buf && *tx_buf)
287 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
291 if (orion_spi_wait_till_ready(orion_spi) < 0) {
292 dev_err(&spi->dev, "TXS timed out\n");
296 if (rx_buf && *rx_buf)
297 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
303 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
308 word_len = spi->bits_per_word;
312 const u8 *tx = xfer->tx_buf;
313 u8 *rx = xfer->rx_buf;
316 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
320 } else if (word_len == 16) {
321 const u16 *tx = xfer->tx_buf;
322 u16 *rx = xfer->rx_buf;
325 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
332 return xfer->len - count;
335 static int orion_spi_transfer_one_message(struct spi_master *master,
336 struct spi_message *m)
338 struct orion_spi *orion_spi = spi_master_get_devdata(master);
339 struct spi_device *spi = m->spi;
340 struct spi_transfer *t = NULL;
341 int par_override = 0;
346 status = orion_spi_setup_transfer(spi, NULL);
351 list_for_each_entry(t, &m->transfers, transfer_list) {
352 if (par_override || t->speed_hz || t->bits_per_word) {
354 status = orion_spi_setup_transfer(spi, t);
357 if (!t->speed_hz && !t->bits_per_word)
362 orion_spi_set_cs(orion_spi, 1);
367 m->actual_length += orion_spi_write_read(spi, t);
370 udelay(t->delay_usecs);
373 orion_spi_set_cs(orion_spi, 0);
380 orion_spi_set_cs(orion_spi, 0);
383 spi_finalize_current_message(master);
388 static int orion_spi_reset(struct orion_spi *orion_spi)
390 /* Verify that the CS is deasserted */
391 orion_spi_set_cs(orion_spi, 0);
396 static const struct orion_spi_dev orion_spi_dev_data = {
400 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
403 static const struct orion_spi_dev armada_spi_dev_data = {
407 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
410 static const struct of_device_id orion_spi_of_match_table[] = {
411 { .compatible = "marvell,orion-spi", .data = &orion_spi_dev_data, },
412 { .compatible = "marvell,armada-370-spi", .data = &armada_spi_dev_data, },
415 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
417 static int orion_spi_probe(struct platform_device *pdev)
419 const struct of_device_id *of_id;
420 const struct orion_spi_dev *devdata;
421 struct spi_master *master;
422 struct orion_spi *spi;
424 unsigned long tclk_hz;
427 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
428 if (master == NULL) {
429 dev_dbg(&pdev->dev, "master allocation failed\n");
434 master->bus_num = pdev->id;
435 if (pdev->dev.of_node) {
438 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
440 master->bus_num = cell_index;
443 /* we support only mode 0, and no options */
444 master->mode_bits = SPI_CPHA | SPI_CPOL;
446 master->transfer_one_message = orion_spi_transfer_one_message;
447 master->num_chipselect = ORION_NUM_CHIPSELECTS;
448 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
449 master->auto_runtime_pm = true;
451 platform_set_drvdata(pdev, master);
453 spi = spi_master_get_devdata(master);
454 spi->master = master;
456 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
457 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
458 spi->devdata = devdata;
460 spi->clk = devm_clk_get(&pdev->dev, NULL);
461 if (IS_ERR(spi->clk)) {
462 status = PTR_ERR(spi->clk);
466 status = clk_prepare_enable(spi->clk);
470 tclk_hz = clk_get_rate(spi->clk);
471 master->max_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
472 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
474 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 spi->base = devm_ioremap_resource(&pdev->dev, r);
476 if (IS_ERR(spi->base)) {
477 status = PTR_ERR(spi->base);
481 pm_runtime_set_active(&pdev->dev);
482 pm_runtime_use_autosuspend(&pdev->dev);
483 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
484 pm_runtime_enable(&pdev->dev);
486 status = orion_spi_reset(spi);
490 pm_runtime_mark_last_busy(&pdev->dev);
491 pm_runtime_put_autosuspend(&pdev->dev);
493 master->dev.of_node = pdev->dev.of_node;
494 status = spi_register_master(master);
501 pm_runtime_disable(&pdev->dev);
503 clk_disable_unprepare(spi->clk);
505 spi_master_put(master);
510 static int orion_spi_remove(struct platform_device *pdev)
512 struct spi_master *master = platform_get_drvdata(pdev);
513 struct orion_spi *spi = spi_master_get_devdata(master);
515 pm_runtime_get_sync(&pdev->dev);
516 clk_disable_unprepare(spi->clk);
518 spi_unregister_master(master);
519 pm_runtime_disable(&pdev->dev);
524 MODULE_ALIAS("platform:" DRIVER_NAME);
526 #ifdef CONFIG_PM_RUNTIME
527 static int orion_spi_runtime_suspend(struct device *dev)
529 struct spi_master *master = dev_get_drvdata(dev);
530 struct orion_spi *spi = spi_master_get_devdata(master);
532 clk_disable_unprepare(spi->clk);
536 static int orion_spi_runtime_resume(struct device *dev)
538 struct spi_master *master = dev_get_drvdata(dev);
539 struct orion_spi *spi = spi_master_get_devdata(master);
541 return clk_prepare_enable(spi->clk);
545 static const struct dev_pm_ops orion_spi_pm_ops = {
546 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
547 orion_spi_runtime_resume,
551 static struct platform_driver orion_spi_driver = {
554 .pm = &orion_spi_pm_ops,
555 .of_match_table = of_match_ptr(orion_spi_of_match_table),
557 .probe = orion_spi_probe,
558 .remove = orion_spi_remove,
561 module_platform_driver(orion_spi_driver);
563 MODULE_DESCRIPTION("Orion SPI driver");
564 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
565 MODULE_LICENSE("GPL");