2 * Marvell Orion SPI controller driver
4 * Author: Shadi Ammouri <shadi@marvell.com>
5 * Copyright (C) 2007-2008 Marvell Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
17 #include <linux/spi/spi.h>
18 #include <linux/module.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/of_device.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24 #include <asm/unaligned.h>
26 #define DRIVER_NAME "orion_spi"
28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
29 #define SPI_AUTOSUSPEND_TIMEOUT 200
31 /* Some SoCs using this driver support up to 8 chip selects.
32 * It is up to the implementer to only use the chip selects
35 #define ORION_NUM_CHIPSELECTS 8
37 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
39 #define ORION_SPI_IF_CTRL_REG 0x00
40 #define ORION_SPI_IF_CONFIG_REG 0x04
41 #define ORION_SPI_DATA_OUT_REG 0x08
42 #define ORION_SPI_DATA_IN_REG 0x0c
43 #define ORION_SPI_INT_CAUSE_REG 0x10
44 #define ORION_SPI_TIMING_PARAMS_REG 0x18
46 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
47 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
48 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
50 #define ORION_SPI_MODE_CPOL (1 << 11)
51 #define ORION_SPI_MODE_CPHA (1 << 12)
52 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
53 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
54 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
55 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
57 #define ORION_SPI_CS_MASK 0x1C
58 #define ORION_SPI_CS_SHIFT 2
59 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
67 struct orion_spi_dev {
68 enum orion_spi_type typ;
70 * min_divisor and max_hz should be exclusive, the only we can
71 * have both is for managing the armada-370-spi case with old
75 unsigned int min_divisor;
76 unsigned int max_divisor;
78 bool is_errata_50mhz_ac;
82 struct spi_master *master;
85 const struct orion_spi_dev *devdata;
88 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
90 return orion_spi->base + reg;
94 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
96 void __iomem *reg_addr = spi_reg(orion_spi, reg);
99 val = readl(reg_addr);
101 writel(val, reg_addr);
105 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
107 void __iomem *reg_addr = spi_reg(orion_spi, reg);
110 val = readl(reg_addr);
112 writel(val, reg_addr);
115 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
121 struct orion_spi *orion_spi;
122 const struct orion_spi_dev *devdata;
124 orion_spi = spi_master_get_devdata(spi->master);
125 devdata = orion_spi->devdata;
127 tclk_hz = clk_get_rate(orion_spi->clk);
129 if (devdata->typ == ARMADA_SPI) {
131 * Given the core_clk (tclk_hz) and the target rate (speed) we
132 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
135 * core_clk / (SPR * 2 ** SPPR)
137 * is as big as possible but not bigger than speed.
140 /* best integer divider: */
141 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
145 /* This is the easy case, divider is less than 16 */
150 unsigned two_pow_sppr;
152 * Find the highest bit set in divider. This and the
153 * three next bits define SPR (apart from rounding).
154 * SPPR is then the number of zero bits that must be
157 sppr = fls(divider) - 4;
160 * As SPR only has 4 bits, we have to round divider up
161 * to the next multiple of 2 ** sppr.
163 two_pow_sppr = 1 << sppr;
164 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
167 * recalculate sppr as rounding up divider might have
168 * increased it enough to change the position of the
169 * highest set bit. In this case the bit that now
170 * doesn't make it into SPR is 0, so there is no need to
173 sppr = fls(divider) - 4;
174 spr = divider >> sppr;
177 * Now do range checking. SPR is constructed to have a
178 * width of 4 bits, so this is fine for sure. So we
179 * still need to check for sppr to fit into 3 bits:
185 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
188 * the supported rates are: 4,6,8...30
189 * round up as we look for equal or less speed
191 rate = DIV_ROUND_UP(tclk_hz, speed);
192 rate = roundup(rate, 2);
194 /* check if requested speed is too small */
201 /* Convert the rate to SPI clock divisor value. */
202 prescale = 0x10 + rate/2;
205 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
206 reg = ((reg & ~devdata->prescale_mask) | prescale);
207 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
213 orion_spi_mode_set(struct spi_device *spi)
216 struct orion_spi *orion_spi;
218 orion_spi = spi_master_get_devdata(spi->master);
220 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
221 reg &= ~ORION_SPI_MODE_MASK;
222 if (spi->mode & SPI_CPOL)
223 reg |= ORION_SPI_MODE_CPOL;
224 if (spi->mode & SPI_CPHA)
225 reg |= ORION_SPI_MODE_CPHA;
226 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
230 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
233 struct orion_spi *orion_spi;
235 orion_spi = spi_master_get_devdata(spi->master);
238 * Erratum description: (Erratum NO. FE-9144572) The device
239 * SPI interface supports frequencies of up to 50 MHz.
240 * However, due to this erratum, when the device core clock is
241 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
242 * clock and CPOL=CPHA=1 there might occur data corruption on
243 * reads from the SPI device.
244 * Erratum Workaround:
245 * Work in one of the following configurations:
246 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
248 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
249 * Register" before setting the interface.
251 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
252 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
254 if (clk_get_rate(orion_spi->clk) == 250000000 &&
255 speed == 50000000 && spi->mode & SPI_CPOL &&
256 spi->mode & SPI_CPHA)
257 reg |= ORION_SPI_TMISO_SAMPLE_2;
259 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
261 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
265 * called only when no transfer is active on the bus
268 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
270 struct orion_spi *orion_spi;
271 unsigned int speed = spi->max_speed_hz;
272 unsigned int bits_per_word = spi->bits_per_word;
275 orion_spi = spi_master_get_devdata(spi->master);
277 if ((t != NULL) && t->speed_hz)
280 if ((t != NULL) && t->bits_per_word)
281 bits_per_word = t->bits_per_word;
283 orion_spi_mode_set(spi);
285 if (orion_spi->devdata->is_errata_50mhz_ac)
286 orion_spi_50mhz_ac_timing_erratum(spi, speed);
288 rc = orion_spi_baudrate_set(spi, speed);
292 if (bits_per_word == 16)
293 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
294 ORION_SPI_IF_8_16_BIT_MODE);
296 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
297 ORION_SPI_IF_8_16_BIT_MODE);
302 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
304 struct orion_spi *orion_spi;
306 orion_spi = spi_master_get_devdata(spi->master);
308 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
309 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
310 ORION_SPI_CS(spi->chip_select));
312 /* Chip select logic is inverted from spi_set_cs */
314 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
316 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
319 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
323 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
324 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
334 orion_spi_write_read_8bit(struct spi_device *spi,
335 const u8 **tx_buf, u8 **rx_buf)
337 void __iomem *tx_reg, *rx_reg, *int_reg;
338 struct orion_spi *orion_spi;
340 orion_spi = spi_master_get_devdata(spi->master);
341 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
342 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
343 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
345 /* clear the interrupt cause register */
346 writel(0x0, int_reg);
348 if (tx_buf && *tx_buf)
349 writel(*(*tx_buf)++, tx_reg);
353 if (orion_spi_wait_till_ready(orion_spi) < 0) {
354 dev_err(&spi->dev, "TXS timed out\n");
358 if (rx_buf && *rx_buf)
359 *(*rx_buf)++ = readl(rx_reg);
365 orion_spi_write_read_16bit(struct spi_device *spi,
366 const u16 **tx_buf, u16 **rx_buf)
368 void __iomem *tx_reg, *rx_reg, *int_reg;
369 struct orion_spi *orion_spi;
371 orion_spi = spi_master_get_devdata(spi->master);
372 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
373 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
374 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
376 /* clear the interrupt cause register */
377 writel(0x0, int_reg);
379 if (tx_buf && *tx_buf)
380 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
384 if (orion_spi_wait_till_ready(orion_spi) < 0) {
385 dev_err(&spi->dev, "TXS timed out\n");
389 if (rx_buf && *rx_buf)
390 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
396 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
401 word_len = spi->bits_per_word;
405 const u8 *tx = xfer->tx_buf;
406 u8 *rx = xfer->rx_buf;
409 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
413 } else if (word_len == 16) {
414 const u16 *tx = xfer->tx_buf;
415 u16 *rx = xfer->rx_buf;
418 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
425 return xfer->len - count;
428 static int orion_spi_transfer_one(struct spi_master *master,
429 struct spi_device *spi,
430 struct spi_transfer *t)
434 status = orion_spi_setup_transfer(spi, t);
439 orion_spi_write_read(spi, t);
444 static int orion_spi_setup(struct spi_device *spi)
446 return orion_spi_setup_transfer(spi, NULL);
449 static int orion_spi_reset(struct orion_spi *orion_spi)
451 /* Verify that the CS is deasserted */
452 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
456 static const struct orion_spi_dev orion_spi_dev_data = {
460 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
463 static const struct orion_spi_dev armada_370_spi_dev_data = {
468 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
471 static const struct orion_spi_dev armada_xp_spi_dev_data = {
475 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
478 static const struct orion_spi_dev armada_375_spi_dev_data = {
482 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
485 static const struct orion_spi_dev armada_380_spi_dev_data = {
489 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
490 .is_errata_50mhz_ac = true,
493 static const struct of_device_id orion_spi_of_match_table[] = {
495 .compatible = "marvell,orion-spi",
496 .data = &orion_spi_dev_data,
499 .compatible = "marvell,armada-370-spi",
500 .data = &armada_370_spi_dev_data,
503 .compatible = "marvell,armada-375-spi",
504 .data = &armada_375_spi_dev_data,
507 .compatible = "marvell,armada-380-spi",
508 .data = &armada_380_spi_dev_data,
511 .compatible = "marvell,armada-390-spi",
512 .data = &armada_xp_spi_dev_data,
515 .compatible = "marvell,armada-xp-spi",
516 .data = &armada_xp_spi_dev_data,
521 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
523 static int orion_spi_probe(struct platform_device *pdev)
525 const struct of_device_id *of_id;
526 const struct orion_spi_dev *devdata;
527 struct spi_master *master;
528 struct orion_spi *spi;
530 unsigned long tclk_hz;
533 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
534 if (master == NULL) {
535 dev_dbg(&pdev->dev, "master allocation failed\n");
540 master->bus_num = pdev->id;
541 if (pdev->dev.of_node) {
544 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
546 master->bus_num = cell_index;
549 /* we support only mode 0, and no options */
550 master->mode_bits = SPI_CPHA | SPI_CPOL;
551 master->set_cs = orion_spi_set_cs;
552 master->transfer_one = orion_spi_transfer_one;
553 master->num_chipselect = ORION_NUM_CHIPSELECTS;
554 master->setup = orion_spi_setup;
555 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
556 master->auto_runtime_pm = true;
558 platform_set_drvdata(pdev, master);
560 spi = spi_master_get_devdata(master);
561 spi->master = master;
563 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
564 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
565 spi->devdata = devdata;
567 spi->clk = devm_clk_get(&pdev->dev, NULL);
568 if (IS_ERR(spi->clk)) {
569 status = PTR_ERR(spi->clk);
573 status = clk_prepare_enable(spi->clk);
577 tclk_hz = clk_get_rate(spi->clk);
580 * With old device tree, armada-370-spi could be used with
581 * Armada XP, however for this SoC the maximum frequency is
582 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
583 * higher than 200MHz. So, in order to be able to handle both
584 * SoCs, we can take the minimum of 50MHz and tclk/4.
586 if (of_device_is_compatible(pdev->dev.of_node,
587 "marvell,armada-370-spi"))
588 master->max_speed_hz = min(devdata->max_hz,
589 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
590 else if (devdata->min_divisor)
591 master->max_speed_hz =
592 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
594 master->max_speed_hz = devdata->max_hz;
595 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
597 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
598 spi->base = devm_ioremap_resource(&pdev->dev, r);
599 if (IS_ERR(spi->base)) {
600 status = PTR_ERR(spi->base);
604 pm_runtime_set_active(&pdev->dev);
605 pm_runtime_use_autosuspend(&pdev->dev);
606 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
607 pm_runtime_enable(&pdev->dev);
609 status = orion_spi_reset(spi);
613 pm_runtime_mark_last_busy(&pdev->dev);
614 pm_runtime_put_autosuspend(&pdev->dev);
616 master->dev.of_node = pdev->dev.of_node;
617 status = spi_register_master(master);
624 pm_runtime_disable(&pdev->dev);
626 clk_disable_unprepare(spi->clk);
628 spi_master_put(master);
633 static int orion_spi_remove(struct platform_device *pdev)
635 struct spi_master *master = platform_get_drvdata(pdev);
636 struct orion_spi *spi = spi_master_get_devdata(master);
638 pm_runtime_get_sync(&pdev->dev);
639 clk_disable_unprepare(spi->clk);
641 spi_unregister_master(master);
642 pm_runtime_disable(&pdev->dev);
647 MODULE_ALIAS("platform:" DRIVER_NAME);
650 static int orion_spi_runtime_suspend(struct device *dev)
652 struct spi_master *master = dev_get_drvdata(dev);
653 struct orion_spi *spi = spi_master_get_devdata(master);
655 clk_disable_unprepare(spi->clk);
659 static int orion_spi_runtime_resume(struct device *dev)
661 struct spi_master *master = dev_get_drvdata(dev);
662 struct orion_spi *spi = spi_master_get_devdata(master);
664 return clk_prepare_enable(spi->clk);
668 static const struct dev_pm_ops orion_spi_pm_ops = {
669 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
670 orion_spi_runtime_resume,
674 static struct platform_driver orion_spi_driver = {
677 .pm = &orion_spi_pm_ops,
678 .of_match_table = of_match_ptr(orion_spi_of_match_table),
680 .probe = orion_spi_probe,
681 .remove = orion_spi_remove,
684 module_platform_driver(orion_spi_driver);
686 MODULE_DESCRIPTION("Orion SPI driver");
687 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
688 MODULE_LICENSE("GPL");