2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2009 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/workqueue.h>
33 #include <linux/delay.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/amba/bus.h>
37 #include <linux/amba/pl022.h>
39 #include <linux/slab.h>
40 #include <linux/dmaengine.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/scatterlist.h>
43 #include <linux/pm_runtime.h>
46 * This macro is used to define some register default values.
47 * reg is masked with mask, the OR:ed with an (again masked)
48 * val shifted sb steps to the left.
50 #define SSP_WRITE_BITS(reg, val, mask, sb) \
51 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54 * This macro is also used to define some default values.
55 * It will just shift val by sb steps to the left and mask
56 * the result with mask.
58 #define GEN_MASK_BITS(val, mask, sb) \
59 (((val)<<(sb)) & (mask))
62 #define DO_NOT_DRIVE_TX 1
64 #define DO_NOT_QUEUE_DMA 0
71 * Macros to access SSP Registers with their offsets
73 #define SSP_CR0(r) (r + 0x000)
74 #define SSP_CR1(r) (r + 0x004)
75 #define SSP_DR(r) (r + 0x008)
76 #define SSP_SR(r) (r + 0x00C)
77 #define SSP_CPSR(r) (r + 0x010)
78 #define SSP_IMSC(r) (r + 0x014)
79 #define SSP_RIS(r) (r + 0x018)
80 #define SSP_MIS(r) (r + 0x01C)
81 #define SSP_ICR(r) (r + 0x020)
82 #define SSP_DMACR(r) (r + 0x024)
83 #define SSP_ITCR(r) (r + 0x080)
84 #define SSP_ITIP(r) (r + 0x084)
85 #define SSP_ITOP(r) (r + 0x088)
86 #define SSP_TDR(r) (r + 0x08C)
88 #define SSP_PID0(r) (r + 0xFE0)
89 #define SSP_PID1(r) (r + 0xFE4)
90 #define SSP_PID2(r) (r + 0xFE8)
91 #define SSP_PID3(r) (r + 0xFEC)
93 #define SSP_CID0(r) (r + 0xFF0)
94 #define SSP_CID1(r) (r + 0xFF4)
95 #define SSP_CID2(r) (r + 0xFF8)
96 #define SSP_CID3(r) (r + 0xFFC)
99 * SSP Control Register 0 - SSP_CR0
101 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
102 #define SSP_CR0_MASK_FRF (0x3UL << 4)
103 #define SSP_CR0_MASK_SPO (0x1UL << 6)
104 #define SSP_CR0_MASK_SPH (0x1UL << 7)
105 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
108 * The ST version of this block moves som bits
109 * in SSP_CR0 and extends it to 32 bits
111 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
112 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
113 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
114 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
117 * SSP Control Register 0 - SSP_CR1
119 #define SSP_CR1_MASK_LBM (0x1UL << 0)
120 #define SSP_CR1_MASK_SSE (0x1UL << 1)
121 #define SSP_CR1_MASK_MS (0x1UL << 2)
122 #define SSP_CR1_MASK_SOD (0x1UL << 3)
125 * The ST version of this block adds some bits
128 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
129 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
130 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
131 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
132 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
133 /* This one is only in the PL023 variant */
134 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
137 * SSP Status Register - SSP_SR
139 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
140 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
141 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
142 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
143 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
146 * SSP Clock Prescale Register - SSP_CPSR
148 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
151 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
153 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
154 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
155 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
156 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
159 * SSP Raw Interrupt Status Register - SSP_RIS
161 /* Receive Overrun Raw Interrupt status */
162 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
163 /* Receive Timeout Raw Interrupt status */
164 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
165 /* Receive FIFO Raw Interrupt status */
166 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
167 /* Transmit FIFO Raw Interrupt status */
168 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
171 * SSP Masked Interrupt Status Register - SSP_MIS
173 /* Receive Overrun Masked Interrupt status */
174 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
175 /* Receive Timeout Masked Interrupt status */
176 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
177 /* Receive FIFO Masked Interrupt status */
178 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
179 /* Transmit FIFO Masked Interrupt status */
180 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
183 * SSP Interrupt Clear Register - SSP_ICR
185 /* Receive Overrun Raw Clear Interrupt bit */
186 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
187 /* Receive Timeout Clear Interrupt bit */
188 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
191 * SSP DMA Control Register - SSP_DMACR
193 /* Receive DMA Enable bit */
194 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
195 /* Transmit DMA Enable bit */
196 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
199 * SSP Integration Test control Register - SSP_ITCR
201 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
202 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
205 * SSP Integration Test Input Register - SSP_ITIP
207 #define ITIP_MASK_SSPRXD (0x1UL << 0)
208 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
209 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
210 #define ITIP_MASK_RXDMAC (0x1UL << 3)
211 #define ITIP_MASK_TXDMAC (0x1UL << 4)
212 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
215 * SSP Integration Test output Register - SSP_ITOP
217 #define ITOP_MASK_SSPTXD (0x1UL << 0)
218 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
219 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
220 #define ITOP_MASK_SSPOEn (0x1UL << 3)
221 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
222 #define ITOP_MASK_RORINTR (0x1UL << 5)
223 #define ITOP_MASK_RTINTR (0x1UL << 6)
224 #define ITOP_MASK_RXINTR (0x1UL << 7)
225 #define ITOP_MASK_TXINTR (0x1UL << 8)
226 #define ITOP_MASK_INTR (0x1UL << 9)
227 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
228 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
229 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
230 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
233 * SSP Test Data Register - SSP_TDR
235 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
239 * we use the spi_message.state (void *) pointer to
240 * hold a single state value, that's why all this
241 * (void *) casting is done here.
243 #define STATE_START ((void *) 0)
244 #define STATE_RUNNING ((void *) 1)
245 #define STATE_DONE ((void *) 2)
246 #define STATE_ERROR ((void *) -1)
249 * SSP State - Whether Enabled or Disabled
251 #define SSP_DISABLED (0)
252 #define SSP_ENABLED (1)
255 * SSP DMA State - Whether DMA Enabled or Disabled
257 #define SSP_DMA_DISABLED (0)
258 #define SSP_DMA_ENABLED (1)
263 #define SSP_DEFAULT_CLKRATE 0x2
264 #define SSP_DEFAULT_PRESCALE 0x40
267 * SSP Clock Parameter ranges
269 #define CPSDVR_MIN 0x02
270 #define CPSDVR_MAX 0xFE
275 * SSP Interrupt related Macros
277 #define DEFAULT_SSP_REG_IMSC 0x0UL
278 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
279 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
281 #define CLEAR_ALL_INTERRUPTS 0x3
283 #define SPI_POLLING_TIMEOUT 1000
286 * The type of reading going on on this chip
296 * The type of writing going on on this chip
306 * struct vendor_data - vendor-specific config parameters
307 * for PL022 derivates
308 * @fifodepth: depth of FIFOs (both)
309 * @max_bpw: maximum number of bits per word
310 * @unidir: supports unidirection transfers
311 * @extended_cr: 32 bit wide control register 0 with extra
312 * features and extra features in CR1 as found in the ST variants
313 * @pl023: supports a subset of the ST extensions called "PL023"
325 * struct pl022 - This is the private SSP driver data structure
326 * @adev: AMBA device model hookup
327 * @vendor: vendor data for the IP block
328 * @phybase: the physical memory where the SSP device resides
329 * @virtbase: the virtual memory where the SSP is mapped
330 * @clk: outgoing clock "SPICLK" for the SPI bus
331 * @master: SPI framework hookup
332 * @master_info: controller-specific data from machine setup
333 * @workqueue: a workqueue on which any spi_message request is queued
334 * @pump_messages: work struct for scheduling work to the workqueue
335 * @queue_lock: spinlock to syncronise access to message queue
336 * @queue: message queue
337 * @busy: workqueue is busy
338 * @running: workqueue is running
339 * @pump_transfers: Tasklet used in Interrupt Transfer mode
340 * @cur_msg: Pointer to current spi_message being processed
341 * @cur_transfer: Pointer to current spi_transfer
342 * @cur_chip: pointer to current clients chip(assigned from controller_state)
343 * @tx: current position in TX buffer to be read
344 * @tx_end: end position in TX buffer to be read
345 * @rx: current position in RX buffer to be written
346 * @rx_end: end position in RX buffer to be written
347 * @read: the type of read currently going on
348 * @write: the type of write currently going on
349 * @exp_fifo_level: expected FIFO level
350 * @dma_rx_channel: optional channel for RX DMA
351 * @dma_tx_channel: optional channel for TX DMA
352 * @sgt_rx: scattertable for the RX transfer
353 * @sgt_tx: scattertable for the TX transfer
354 * @dummypage: a dummy page used for driving data on the bus with DMA
357 struct amba_device *adev;
358 struct vendor_data *vendor;
359 resource_size_t phybase;
360 void __iomem *virtbase;
362 struct spi_master *master;
363 struct pl022_ssp_controller *master_info;
364 /* Driver message queue */
365 struct workqueue_struct *workqueue;
366 struct work_struct pump_messages;
367 spinlock_t queue_lock;
368 struct list_head queue;
371 /* Message transfer pump */
372 struct tasklet_struct pump_transfers;
373 struct spi_message *cur_msg;
374 struct spi_transfer *cur_transfer;
375 struct chip_data *cur_chip;
380 enum ssp_reading read;
381 enum ssp_writing write;
383 enum ssp_rx_level_trig rx_lev_trig;
384 enum ssp_tx_level_trig tx_lev_trig;
386 #ifdef CONFIG_DMA_ENGINE
387 struct dma_chan *dma_rx_channel;
388 struct dma_chan *dma_tx_channel;
389 struct sg_table sgt_rx;
390 struct sg_table sgt_tx;
396 * struct chip_data - To maintain runtime state of SSP for each client chip
397 * @cr0: Value of control register CR0 of SSP - on later ST variants this
398 * register is 32 bits wide rather than just 16
399 * @cr1: Value of control register CR1 of SSP
400 * @dmacr: Value of DMA control Register of SSP
401 * @cpsr: Value of Clock prescale register
402 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
403 * @enable_dma: Whether to enable DMA or not
404 * @read: function ptr to be used to read when doing xfer for this chip
405 * @write: function ptr to be used to write when doing xfer for this chip
406 * @cs_control: chip select callback provided by chip
407 * @xfer_type: polling/interrupt/DMA
409 * Runtime state of the SSP controller, maintained per chip,
410 * This would be set according to the current message that would be served
419 enum ssp_reading read;
420 enum ssp_writing write;
421 void (*cs_control) (u32 command);
426 * null_cs_control - Dummy chip select function
427 * @command: select/delect the chip
429 * If no chip select function is provided by client this is used as dummy
432 static void null_cs_control(u32 command)
434 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
438 * giveback - current spi_message is over, schedule next message and call
439 * callback of this message. Assumes that caller already
440 * set message->status; dma and pio irqs are blocked
441 * @pl022: SSP driver private data structure
443 static void giveback(struct pl022 *pl022)
445 struct spi_transfer *last_transfer;
447 struct spi_message *msg;
448 void (*curr_cs_control) (u32 command);
451 * This local reference to the chip select function
452 * is needed because we set curr_chip to NULL
453 * as a step toward termininating the message.
455 curr_cs_control = pl022->cur_chip->cs_control;
456 spin_lock_irqsave(&pl022->queue_lock, flags);
457 msg = pl022->cur_msg;
458 pl022->cur_msg = NULL;
459 pl022->cur_transfer = NULL;
460 pl022->cur_chip = NULL;
461 queue_work(pl022->workqueue, &pl022->pump_messages);
462 spin_unlock_irqrestore(&pl022->queue_lock, flags);
464 last_transfer = list_entry(msg->transfers.prev,
468 /* Delay if requested before any change in chip select */
469 if (last_transfer->delay_usecs)
471 * FIXME: This runs in interrupt context.
472 * Is this really smart?
474 udelay(last_transfer->delay_usecs);
477 * Drop chip select UNLESS cs_change is true or we are returning
478 * a message with an error, or next message is for another chip
480 if (!last_transfer->cs_change)
481 curr_cs_control(SSP_CHIP_DESELECT);
483 struct spi_message *next_msg;
485 /* Holding of cs was hinted, but we need to make sure
486 * the next message is for the same chip. Don't waste
487 * time with the following tests unless this was hinted.
489 * We cannot postpone this until pump_messages, because
490 * after calling msg->complete (below) the driver that
491 * sent the current message could be unloaded, which
492 * could invalidate the cs_control() callback...
495 /* get a pointer to the next message, if any */
496 spin_lock_irqsave(&pl022->queue_lock, flags);
497 if (list_empty(&pl022->queue))
500 next_msg = list_entry(pl022->queue.next,
501 struct spi_message, queue);
502 spin_unlock_irqrestore(&pl022->queue_lock, flags);
504 /* see if the next and current messages point
507 if (next_msg && next_msg->spi != msg->spi)
509 if (!next_msg || msg->state == STATE_ERROR)
510 curr_cs_control(SSP_CHIP_DESELECT);
514 msg->complete(msg->context);
518 * flush - flush the FIFO to reach a clean state
519 * @pl022: SSP driver private data structure
521 static int flush(struct pl022 *pl022)
523 unsigned long limit = loops_per_jiffy << 1;
525 dev_dbg(&pl022->adev->dev, "flush\n");
527 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
528 readw(SSP_DR(pl022->virtbase));
529 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
531 pl022->exp_fifo_level = 0;
537 * restore_state - Load configuration of current chip
538 * @pl022: SSP driver private data structure
540 static void restore_state(struct pl022 *pl022)
542 struct chip_data *chip = pl022->cur_chip;
544 if (pl022->vendor->extended_cr)
545 writel(chip->cr0, SSP_CR0(pl022->virtbase));
547 writew(chip->cr0, SSP_CR0(pl022->virtbase));
548 writew(chip->cr1, SSP_CR1(pl022->virtbase));
549 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
550 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
551 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
552 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
556 * Default SSP Register Values
558 #define DEFAULT_SSP_REG_CR0 ( \
559 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
560 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
561 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
562 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
563 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
566 /* ST versions have slightly different bit layout */
567 #define DEFAULT_SSP_REG_CR0_ST ( \
568 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
569 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
570 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
571 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
572 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
573 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
574 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
577 /* The PL023 version is slightly different again */
578 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
579 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
580 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
581 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
582 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
585 #define DEFAULT_SSP_REG_CR1 ( \
586 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
587 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
588 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
589 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
592 /* ST versions extend this register to use all 16 bits */
593 #define DEFAULT_SSP_REG_CR1_ST ( \
594 DEFAULT_SSP_REG_CR1 | \
595 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
596 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
597 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
598 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
599 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
603 * The PL023 variant has further differences: no loopback mode, no microwire
604 * support, and a new clock feedback delay setting.
606 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
607 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
608 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
609 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
610 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
611 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
612 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
613 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
614 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
617 #define DEFAULT_SSP_REG_CPSR ( \
618 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
621 #define DEFAULT_SSP_REG_DMACR (\
622 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
623 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
627 * load_ssp_default_config - Load default configuration for SSP
628 * @pl022: SSP driver private data structure
630 static void load_ssp_default_config(struct pl022 *pl022)
632 if (pl022->vendor->pl023) {
633 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
634 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
635 } else if (pl022->vendor->extended_cr) {
636 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
637 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
640 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
642 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
643 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
644 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
645 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
649 * This will write to TX and read from RX according to the parameters
652 static void readwriter(struct pl022 *pl022)
656 * The FIFO depth is different between primecell variants.
657 * I believe filling in too much in the FIFO might cause
658 * errons in 8bit wide transfers on ARM variants (just 8 words
659 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
661 * To prevent this issue, the TX FIFO is only filled to the
662 * unused RX FIFO fill length, regardless of what the TX
663 * FIFO status flag indicates.
665 dev_dbg(&pl022->adev->dev,
666 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
667 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
669 /* Read as much as you can */
670 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
671 && (pl022->rx < pl022->rx_end)) {
672 switch (pl022->read) {
674 readw(SSP_DR(pl022->virtbase));
677 *(u8 *) (pl022->rx) =
678 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
681 *(u16 *) (pl022->rx) =
682 (u16) readw(SSP_DR(pl022->virtbase));
685 *(u32 *) (pl022->rx) =
686 readl(SSP_DR(pl022->virtbase));
689 pl022->rx += (pl022->cur_chip->n_bytes);
690 pl022->exp_fifo_level--;
693 * Write as much as possible up to the RX FIFO size
695 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
696 && (pl022->tx < pl022->tx_end)) {
697 switch (pl022->write) {
699 writew(0x0, SSP_DR(pl022->virtbase));
702 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
705 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
708 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
711 pl022->tx += (pl022->cur_chip->n_bytes);
712 pl022->exp_fifo_level++;
714 * This inner reader takes care of things appearing in the RX
715 * FIFO as we're transmitting. This will happen a lot since the
716 * clock starts running when you put things into the TX FIFO,
717 * and then things are continuously clocked into the RX FIFO.
719 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
720 && (pl022->rx < pl022->rx_end)) {
721 switch (pl022->read) {
723 readw(SSP_DR(pl022->virtbase));
726 *(u8 *) (pl022->rx) =
727 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
730 *(u16 *) (pl022->rx) =
731 (u16) readw(SSP_DR(pl022->virtbase));
734 *(u32 *) (pl022->rx) =
735 readl(SSP_DR(pl022->virtbase));
738 pl022->rx += (pl022->cur_chip->n_bytes);
739 pl022->exp_fifo_level--;
743 * When we exit here the TX FIFO should be full and the RX FIFO
749 * next_transfer - Move to the Next transfer in the current spi message
750 * @pl022: SSP driver private data structure
752 * This function moves though the linked list of spi transfers in the
753 * current spi message and returns with the state of current spi
754 * message i.e whether its last transfer is done(STATE_DONE) or
755 * Next transfer is ready(STATE_RUNNING)
757 static void *next_transfer(struct pl022 *pl022)
759 struct spi_message *msg = pl022->cur_msg;
760 struct spi_transfer *trans = pl022->cur_transfer;
762 /* Move to next transfer */
763 if (trans->transfer_list.next != &msg->transfers) {
764 pl022->cur_transfer =
765 list_entry(trans->transfer_list.next,
766 struct spi_transfer, transfer_list);
767 return STATE_RUNNING;
773 * This DMA functionality is only compiled in if we have
774 * access to the generic DMA devices/DMA engine.
776 #ifdef CONFIG_DMA_ENGINE
777 static void unmap_free_dma_scatter(struct pl022 *pl022)
779 /* Unmap and free the SG tables */
780 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
781 pl022->sgt_tx.nents, DMA_TO_DEVICE);
782 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
783 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
784 sg_free_table(&pl022->sgt_rx);
785 sg_free_table(&pl022->sgt_tx);
788 static void dma_callback(void *data)
790 struct pl022 *pl022 = data;
791 struct spi_message *msg = pl022->cur_msg;
793 BUG_ON(!pl022->sgt_rx.sgl);
797 * Optionally dump out buffers to inspect contents, this is
798 * good if you want to convince yourself that the loopback
799 * read/write contents are the same, when adopting to a new
803 struct scatterlist *sg;
806 dma_sync_sg_for_cpu(&pl022->adev->dev,
811 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
812 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
813 print_hex_dump(KERN_ERR, "SPI RX: ",
821 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
822 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
823 print_hex_dump(KERN_ERR, "SPI TX: ",
834 unmap_free_dma_scatter(pl022);
836 /* Update total bytes transferred */
837 msg->actual_length += pl022->cur_transfer->len;
838 if (pl022->cur_transfer->cs_change)
840 cs_control(SSP_CHIP_DESELECT);
842 /* Move to next transfer */
843 msg->state = next_transfer(pl022);
844 tasklet_schedule(&pl022->pump_transfers);
847 static void setup_dma_scatter(struct pl022 *pl022,
850 struct sg_table *sgtab)
852 struct scatterlist *sg;
853 int bytesleft = length;
859 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
861 * If there are less bytes left than what fits
862 * in the current page (plus page alignment offset)
863 * we just feed in this, else we stuff in as much
866 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
867 mapbytes = bytesleft;
869 mapbytes = PAGE_SIZE - offset_in_page(bufp);
870 sg_set_page(sg, virt_to_page(bufp),
871 mapbytes, offset_in_page(bufp));
873 bytesleft -= mapbytes;
874 dev_dbg(&pl022->adev->dev,
875 "set RX/TX target page @ %p, %d bytes, %d left\n",
876 bufp, mapbytes, bytesleft);
879 /* Map the dummy buffer on every page */
880 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
881 if (bytesleft < PAGE_SIZE)
882 mapbytes = bytesleft;
884 mapbytes = PAGE_SIZE;
885 sg_set_page(sg, virt_to_page(pl022->dummypage),
887 bytesleft -= mapbytes;
888 dev_dbg(&pl022->adev->dev,
889 "set RX/TX to dummy page %d bytes, %d left\n",
890 mapbytes, bytesleft);
898 * configure_dma - configures the channels for the next transfer
899 * @pl022: SSP driver's private data structure
901 static int configure_dma(struct pl022 *pl022)
903 struct dma_slave_config rx_conf = {
904 .src_addr = SSP_DR(pl022->phybase),
905 .direction = DMA_FROM_DEVICE,
907 struct dma_slave_config tx_conf = {
908 .dst_addr = SSP_DR(pl022->phybase),
909 .direction = DMA_TO_DEVICE,
913 int rx_sglen, tx_sglen;
914 struct dma_chan *rxchan = pl022->dma_rx_channel;
915 struct dma_chan *txchan = pl022->dma_tx_channel;
916 struct dma_async_tx_descriptor *rxdesc;
917 struct dma_async_tx_descriptor *txdesc;
919 /* Check that the channels are available */
920 if (!rxchan || !txchan)
924 * If supplied, the DMA burstsize should equal the FIFO trigger level.
925 * Notice that the DMA engine uses one-to-one mapping. Since we can
926 * not trigger on 2 elements this needs explicit mapping rather than
929 switch (pl022->rx_lev_trig) {
930 case SSP_RX_1_OR_MORE_ELEM:
931 rx_conf.src_maxburst = 1;
933 case SSP_RX_4_OR_MORE_ELEM:
934 rx_conf.src_maxburst = 4;
936 case SSP_RX_8_OR_MORE_ELEM:
937 rx_conf.src_maxburst = 8;
939 case SSP_RX_16_OR_MORE_ELEM:
940 rx_conf.src_maxburst = 16;
942 case SSP_RX_32_OR_MORE_ELEM:
943 rx_conf.src_maxburst = 32;
946 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
950 switch (pl022->tx_lev_trig) {
951 case SSP_TX_1_OR_MORE_EMPTY_LOC:
952 tx_conf.dst_maxburst = 1;
954 case SSP_TX_4_OR_MORE_EMPTY_LOC:
955 tx_conf.dst_maxburst = 4;
957 case SSP_TX_8_OR_MORE_EMPTY_LOC:
958 tx_conf.dst_maxburst = 8;
960 case SSP_TX_16_OR_MORE_EMPTY_LOC:
961 tx_conf.dst_maxburst = 16;
963 case SSP_TX_32_OR_MORE_EMPTY_LOC:
964 tx_conf.dst_maxburst = 32;
967 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
971 switch (pl022->read) {
973 /* Use the same as for writing */
974 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
977 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
980 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
983 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
987 switch (pl022->write) {
989 /* Use the same as for reading */
990 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
993 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
996 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
999 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1003 /* SPI pecularity: we need to read and write the same width */
1004 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1005 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1006 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1007 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1008 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1010 dmaengine_slave_config(rxchan, &rx_conf);
1011 dmaengine_slave_config(txchan, &tx_conf);
1013 /* Create sglists for the transfers */
1014 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1015 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1017 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1019 goto err_alloc_rx_sg;
1021 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1023 goto err_alloc_tx_sg;
1025 /* Fill in the scatterlists for the RX+TX buffers */
1026 setup_dma_scatter(pl022, pl022->rx,
1027 pl022->cur_transfer->len, &pl022->sgt_rx);
1028 setup_dma_scatter(pl022, pl022->tx,
1029 pl022->cur_transfer->len, &pl022->sgt_tx);
1031 /* Map DMA buffers */
1032 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1033 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1037 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1038 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1042 /* Send both scatterlists */
1043 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1047 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1051 txdesc = txchan->device->device_prep_slave_sg(txchan,
1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1059 /* Put the callback on the RX transfer only, that should finish last */
1060 rxdesc->callback = dma_callback;
1061 rxdesc->callback_param = pl022;
1063 /* Submit and fire RX and TX with TX last so we're ready to read! */
1064 dmaengine_submit(rxdesc);
1065 dmaengine_submit(txdesc);
1066 dma_async_issue_pending(rxchan);
1067 dma_async_issue_pending(txchan);
1072 dmaengine_terminate_all(txchan);
1074 dmaengine_terminate_all(rxchan);
1075 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1076 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1078 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1079 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1081 sg_free_table(&pl022->sgt_tx);
1083 sg_free_table(&pl022->sgt_rx);
1088 static int __init pl022_dma_probe(struct pl022 *pl022)
1090 dma_cap_mask_t mask;
1092 /* Try to acquire a generic DMA engine slave channel */
1094 dma_cap_set(DMA_SLAVE, mask);
1096 * We need both RX and TX channels to do DMA, else do none
1099 pl022->dma_rx_channel = dma_request_channel(mask,
1100 pl022->master_info->dma_filter,
1101 pl022->master_info->dma_rx_param);
1102 if (!pl022->dma_rx_channel) {
1103 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1107 pl022->dma_tx_channel = dma_request_channel(mask,
1108 pl022->master_info->dma_filter,
1109 pl022->master_info->dma_tx_param);
1110 if (!pl022->dma_tx_channel) {
1111 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1115 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1116 if (!pl022->dummypage) {
1117 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
1118 goto err_no_dummypage;
1121 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1122 dma_chan_name(pl022->dma_rx_channel),
1123 dma_chan_name(pl022->dma_tx_channel));
1128 dma_release_channel(pl022->dma_tx_channel);
1130 dma_release_channel(pl022->dma_rx_channel);
1131 pl022->dma_rx_channel = NULL;
1133 dev_err(&pl022->adev->dev,
1134 "Failed to work in dma mode, work without dma!\n");
1138 static void terminate_dma(struct pl022 *pl022)
1140 struct dma_chan *rxchan = pl022->dma_rx_channel;
1141 struct dma_chan *txchan = pl022->dma_tx_channel;
1143 dmaengine_terminate_all(rxchan);
1144 dmaengine_terminate_all(txchan);
1145 unmap_free_dma_scatter(pl022);
1148 static void pl022_dma_remove(struct pl022 *pl022)
1151 terminate_dma(pl022);
1152 if (pl022->dma_tx_channel)
1153 dma_release_channel(pl022->dma_tx_channel);
1154 if (pl022->dma_rx_channel)
1155 dma_release_channel(pl022->dma_rx_channel);
1156 kfree(pl022->dummypage);
1160 static inline int configure_dma(struct pl022 *pl022)
1165 static inline int pl022_dma_probe(struct pl022 *pl022)
1170 static inline void pl022_dma_remove(struct pl022 *pl022)
1176 * pl022_interrupt_handler - Interrupt handler for SSP controller
1178 * This function handles interrupts generated for an interrupt based transfer.
1179 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1180 * current message's state as STATE_ERROR and schedule the tasklet
1181 * pump_transfers which will do the postprocessing of the current message by
1182 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1183 * more data, and writes data in TX FIFO till it is not full. If we complete
1184 * the transfer we move to the next transfer and schedule the tasklet.
1186 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1188 struct pl022 *pl022 = dev_id;
1189 struct spi_message *msg = pl022->cur_msg;
1193 if (unlikely(!msg)) {
1194 dev_err(&pl022->adev->dev,
1195 "bad message state in interrupt handler");
1200 /* Read the Interrupt Status Register */
1201 irq_status = readw(SSP_MIS(pl022->virtbase));
1203 if (unlikely(!irq_status))
1207 * This handles the FIFO interrupts, the timeout
1208 * interrupts are flatly ignored, they cannot be
1211 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1213 * Overrun interrupt - bail out since our Data has been
1216 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1217 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1218 dev_err(&pl022->adev->dev,
1219 "RXFIFO is full\n");
1220 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1221 dev_err(&pl022->adev->dev,
1222 "TXFIFO is full\n");
1225 * Disable and clear interrupts, disable SSP,
1226 * mark message with bad status so it can be
1229 writew(DISABLE_ALL_INTERRUPTS,
1230 SSP_IMSC(pl022->virtbase));
1231 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1232 writew((readw(SSP_CR1(pl022->virtbase)) &
1233 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1234 msg->state = STATE_ERROR;
1236 /* Schedule message queue handler */
1237 tasklet_schedule(&pl022->pump_transfers);
1243 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1245 /* Disable Transmit interrupt, enable receive interrupt */
1246 writew((readw(SSP_IMSC(pl022->virtbase)) &
1247 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1248 SSP_IMSC(pl022->virtbase));
1252 * Since all transactions must write as much as shall be read,
1253 * we can conclude the entire transaction once RX is complete.
1254 * At this point, all TX will always be finished.
1256 if (pl022->rx >= pl022->rx_end) {
1257 writew(DISABLE_ALL_INTERRUPTS,
1258 SSP_IMSC(pl022->virtbase));
1259 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1260 if (unlikely(pl022->rx > pl022->rx_end)) {
1261 dev_warn(&pl022->adev->dev, "read %u surplus "
1262 "bytes (did you request an odd "
1263 "number of bytes on a 16bit bus?)\n",
1264 (u32) (pl022->rx - pl022->rx_end));
1266 /* Update total bytes transferred */
1267 msg->actual_length += pl022->cur_transfer->len;
1268 if (pl022->cur_transfer->cs_change)
1270 cs_control(SSP_CHIP_DESELECT);
1271 /* Move to next transfer */
1272 msg->state = next_transfer(pl022);
1273 tasklet_schedule(&pl022->pump_transfers);
1281 * This sets up the pointers to memory for the next message to
1282 * send out on the SPI bus.
1284 static int set_up_next_transfer(struct pl022 *pl022,
1285 struct spi_transfer *transfer)
1289 /* Sanity check the message for this bus width */
1290 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1291 if (unlikely(residue != 0)) {
1292 dev_err(&pl022->adev->dev,
1293 "message of %u bytes to transmit but the current "
1294 "chip bus has a data width of %u bytes!\n",
1295 pl022->cur_transfer->len,
1296 pl022->cur_chip->n_bytes);
1297 dev_err(&pl022->adev->dev, "skipping this message\n");
1300 pl022->tx = (void *)transfer->tx_buf;
1301 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1302 pl022->rx = (void *)transfer->rx_buf;
1303 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1305 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1306 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1311 * pump_transfers - Tasklet function which schedules next transfer
1312 * when running in interrupt or DMA transfer mode.
1313 * @data: SSP driver private data structure
1316 static void pump_transfers(unsigned long data)
1318 struct pl022 *pl022 = (struct pl022 *) data;
1319 struct spi_message *message = NULL;
1320 struct spi_transfer *transfer = NULL;
1321 struct spi_transfer *previous = NULL;
1323 /* Get current state information */
1324 message = pl022->cur_msg;
1325 transfer = pl022->cur_transfer;
1327 /* Handle for abort */
1328 if (message->state == STATE_ERROR) {
1329 message->status = -EIO;
1334 /* Handle end of message */
1335 if (message->state == STATE_DONE) {
1336 message->status = 0;
1341 /* Delay if requested at end of transfer before CS change */
1342 if (message->state == STATE_RUNNING) {
1343 previous = list_entry(transfer->transfer_list.prev,
1344 struct spi_transfer,
1346 if (previous->delay_usecs)
1348 * FIXME: This runs in interrupt context.
1349 * Is this really smart?
1351 udelay(previous->delay_usecs);
1353 /* Drop chip select only if cs_change is requested */
1354 if (previous->cs_change)
1355 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1358 message->state = STATE_RUNNING;
1361 if (set_up_next_transfer(pl022, transfer)) {
1362 message->state = STATE_ERROR;
1363 message->status = -EIO;
1367 /* Flush the FIFOs and let's go! */
1370 if (pl022->cur_chip->enable_dma) {
1371 if (configure_dma(pl022)) {
1372 dev_dbg(&pl022->adev->dev,
1373 "configuration of DMA failed, fall back to interrupt mode\n");
1374 goto err_config_dma;
1380 /* enable all interrupts except RX */
1381 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1384 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1387 * Default is to enable all interrupts except RX -
1388 * this will be enabled once TX is complete
1390 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
1392 /* Enable target chip */
1393 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1394 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1396 pl022->cur_msg->state = STATE_ERROR;
1397 pl022->cur_msg->status = -EIO;
1401 /* If we're using DMA, set up DMA here */
1402 if (pl022->cur_chip->enable_dma) {
1403 /* Configure DMA transfer */
1404 if (configure_dma(pl022)) {
1405 dev_dbg(&pl022->adev->dev,
1406 "configuration of DMA failed, fall back to interrupt mode\n");
1407 goto err_config_dma;
1409 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1410 irqflags = DISABLE_ALL_INTERRUPTS;
1413 /* Enable SSP, turn on interrupts */
1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1415 SSP_CR1(pl022->virtbase));
1416 writew(irqflags, SSP_IMSC(pl022->virtbase));
1419 static void do_polling_transfer(struct pl022 *pl022)
1421 struct spi_message *message = NULL;
1422 struct spi_transfer *transfer = NULL;
1423 struct spi_transfer *previous = NULL;
1424 struct chip_data *chip;
1425 unsigned long time, timeout;
1427 chip = pl022->cur_chip;
1428 message = pl022->cur_msg;
1430 while (message->state != STATE_DONE) {
1431 /* Handle for abort */
1432 if (message->state == STATE_ERROR)
1434 transfer = pl022->cur_transfer;
1436 /* Delay if requested at end of transfer */
1437 if (message->state == STATE_RUNNING) {
1439 list_entry(transfer->transfer_list.prev,
1440 struct spi_transfer, transfer_list);
1441 if (previous->delay_usecs)
1442 udelay(previous->delay_usecs);
1443 if (previous->cs_change)
1444 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1447 message->state = STATE_RUNNING;
1448 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1451 /* Configuration Changing Per Transfer */
1452 if (set_up_next_transfer(pl022, transfer)) {
1454 message->state = STATE_ERROR;
1457 /* Flush FIFOs and enable SSP */
1459 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1460 SSP_CR1(pl022->virtbase));
1462 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1464 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1465 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1468 if (time_after(time, timeout)) {
1469 dev_warn(&pl022->adev->dev,
1470 "%s: timeout!\n", __func__);
1471 message->state = STATE_ERROR;
1477 /* Update total byte transferred */
1478 message->actual_length += pl022->cur_transfer->len;
1479 if (pl022->cur_transfer->cs_change)
1480 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1481 /* Move to next transfer */
1482 message->state = next_transfer(pl022);
1485 /* Handle end of message */
1486 if (message->state == STATE_DONE)
1487 message->status = 0;
1489 message->status = -EIO;
1496 * pump_messages - Workqueue function which processes spi message queue
1497 * @data: pointer to private data of SSP driver
1499 * This function checks if there is any spi message in the queue that
1500 * needs processing and delegate control to appropriate function
1501 * do_polling_transfer()/do_interrupt_dma_transfer()
1502 * based on the kind of the transfer
1505 static void pump_messages(struct work_struct *work)
1507 struct pl022 *pl022 =
1508 container_of(work, struct pl022, pump_messages);
1509 unsigned long flags;
1510 bool was_busy = false;
1512 /* Lock queue and check for queue work */
1513 spin_lock_irqsave(&pl022->queue_lock, flags);
1514 if (list_empty(&pl022->queue) || !pl022->running) {
1516 /* nothing more to do - disable spi/ssp and power off */
1517 writew((readw(SSP_CR1(pl022->virtbase)) &
1518 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1519 pm_runtime_put(&pl022->adev->dev);
1521 pl022->busy = false;
1522 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1526 /* Make sure we are not already running a message */
1527 if (pl022->cur_msg) {
1528 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1531 /* Extract head of queue */
1533 list_entry(pl022->queue.next, struct spi_message, queue);
1535 list_del_init(&pl022->cur_msg->queue);
1540 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1542 /* Initial message state */
1543 pl022->cur_msg->state = STATE_START;
1544 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1545 struct spi_transfer, transfer_list);
1547 /* Setup the SPI using the per chip configuration */
1548 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1551 * We enable the core voltage and clocks here, then the clocks
1552 * and core will be disabled when this workqueue is run again
1553 * and there is no more work to be done.
1555 pm_runtime_get_sync(&pl022->adev->dev);
1557 restore_state(pl022);
1560 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1561 do_polling_transfer(pl022);
1563 do_interrupt_dma_transfer(pl022);
1566 static int __init init_queue(struct pl022 *pl022)
1568 INIT_LIST_HEAD(&pl022->queue);
1569 spin_lock_init(&pl022->queue_lock);
1571 pl022->running = false;
1572 pl022->busy = false;
1574 tasklet_init(&pl022->pump_transfers, pump_transfers,
1575 (unsigned long)pl022);
1577 INIT_WORK(&pl022->pump_messages, pump_messages);
1578 pl022->workqueue = create_singlethread_workqueue(
1579 dev_name(pl022->master->dev.parent));
1580 if (pl022->workqueue == NULL)
1586 static int start_queue(struct pl022 *pl022)
1588 unsigned long flags;
1590 spin_lock_irqsave(&pl022->queue_lock, flags);
1592 if (pl022->running || pl022->busy) {
1593 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1597 pl022->running = true;
1598 pl022->cur_msg = NULL;
1599 pl022->cur_transfer = NULL;
1600 pl022->cur_chip = NULL;
1601 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1603 queue_work(pl022->workqueue, &pl022->pump_messages);
1608 static int stop_queue(struct pl022 *pl022)
1610 unsigned long flags;
1611 unsigned limit = 500;
1614 spin_lock_irqsave(&pl022->queue_lock, flags);
1616 /* This is a bit lame, but is optimized for the common execution path.
1617 * A wait_queue on the pl022->busy could be used, but then the common
1618 * execution path (pump_messages) would be required to call wake_up or
1619 * friends on every SPI message. Do this instead */
1620 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) {
1621 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1623 spin_lock_irqsave(&pl022->queue_lock, flags);
1626 if (!list_empty(&pl022->queue) || pl022->busy)
1629 pl022->running = false;
1631 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1636 static int destroy_queue(struct pl022 *pl022)
1640 status = stop_queue(pl022);
1641 /* we are unloading the module or failing to load (only two calls
1642 * to this routine), and neither call can handle a return value.
1643 * However, destroy_workqueue calls flush_workqueue, and that will
1644 * block until all work is done. If the reason that stop_queue
1645 * timed out is that the work will never finish, then it does no
1646 * good to call destroy_workqueue, so return anyway. */
1650 destroy_workqueue(pl022->workqueue);
1655 static int verify_controller_parameters(struct pl022 *pl022,
1656 struct pl022_config_chip const *chip_info)
1658 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1659 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1660 dev_err(&pl022->adev->dev,
1661 "interface is configured incorrectly\n");
1664 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1665 (!pl022->vendor->unidir)) {
1666 dev_err(&pl022->adev->dev,
1667 "unidirectional mode not supported in this "
1668 "hardware version\n");
1671 if ((chip_info->hierarchy != SSP_MASTER)
1672 && (chip_info->hierarchy != SSP_SLAVE)) {
1673 dev_err(&pl022->adev->dev,
1674 "hierarchy is configured incorrectly\n");
1677 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1678 && (chip_info->com_mode != DMA_TRANSFER)
1679 && (chip_info->com_mode != POLLING_TRANSFER)) {
1680 dev_err(&pl022->adev->dev,
1681 "Communication mode is configured incorrectly\n");
1684 switch (chip_info->rx_lev_trig) {
1685 case SSP_RX_1_OR_MORE_ELEM:
1686 case SSP_RX_4_OR_MORE_ELEM:
1687 case SSP_RX_8_OR_MORE_ELEM:
1688 /* These are always OK, all variants can handle this */
1690 case SSP_RX_16_OR_MORE_ELEM:
1691 if (pl022->vendor->fifodepth < 16) {
1692 dev_err(&pl022->adev->dev,
1693 "RX FIFO Trigger Level is configured incorrectly\n");
1697 case SSP_RX_32_OR_MORE_ELEM:
1698 if (pl022->vendor->fifodepth < 32) {
1699 dev_err(&pl022->adev->dev,
1700 "RX FIFO Trigger Level is configured incorrectly\n");
1705 dev_err(&pl022->adev->dev,
1706 "RX FIFO Trigger Level is configured incorrectly\n");
1710 switch (chip_info->tx_lev_trig) {
1711 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1712 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1713 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1714 /* These are always OK, all variants can handle this */
1716 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1717 if (pl022->vendor->fifodepth < 16) {
1718 dev_err(&pl022->adev->dev,
1719 "TX FIFO Trigger Level is configured incorrectly\n");
1723 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1724 if (pl022->vendor->fifodepth < 32) {
1725 dev_err(&pl022->adev->dev,
1726 "TX FIFO Trigger Level is configured incorrectly\n");
1731 dev_err(&pl022->adev->dev,
1732 "TX FIFO Trigger Level is configured incorrectly\n");
1736 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1737 if ((chip_info->ctrl_len < SSP_BITS_4)
1738 || (chip_info->ctrl_len > SSP_BITS_32)) {
1739 dev_err(&pl022->adev->dev,
1740 "CTRL LEN is configured incorrectly\n");
1743 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1744 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1745 dev_err(&pl022->adev->dev,
1746 "Wait State is configured incorrectly\n");
1749 /* Half duplex is only available in the ST Micro version */
1750 if (pl022->vendor->extended_cr) {
1751 if ((chip_info->duplex !=
1752 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1753 && (chip_info->duplex !=
1754 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1755 dev_err(&pl022->adev->dev,
1756 "Microwire duplex mode is configured incorrectly\n");
1760 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1761 dev_err(&pl022->adev->dev,
1762 "Microwire half duplex mode requested,"
1763 " but this is only available in the"
1764 " ST version of PL022\n");
1772 * pl022_transfer - transfer function registered to SPI master framework
1773 * @spi: spi device which is requesting transfer
1774 * @msg: spi message which is to handled is queued to driver queue
1776 * This function is registered to the SPI framework for this SPI master
1777 * controller. It will queue the spi_message in the queue of driver if
1778 * the queue is not stopped and return.
1780 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1782 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1783 unsigned long flags;
1785 spin_lock_irqsave(&pl022->queue_lock, flags);
1787 if (!pl022->running) {
1788 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1791 msg->actual_length = 0;
1792 msg->status = -EINPROGRESS;
1793 msg->state = STATE_START;
1795 list_add_tail(&msg->queue, &pl022->queue);
1796 if (pl022->running && !pl022->busy)
1797 queue_work(pl022->workqueue, &pl022->pump_messages);
1799 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1803 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1805 return rate / (cpsdvsr * (1 + scr));
1808 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1809 ssp_clock_params * clk_freq)
1811 /* Lets calculate the frequency parameters */
1812 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1813 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1814 best_scr = 0, tmp, found = 0;
1816 rate = clk_get_rate(pl022->clk);
1817 /* cpsdvscr = 2 & scr 0 */
1818 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1819 /* cpsdvsr = 254 & scr = 255 */
1820 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1822 if (!((freq <= max_tclk) && (freq >= min_tclk))) {
1823 dev_err(&pl022->adev->dev,
1824 "controller data is incorrect: out of range frequency");
1829 * best_freq will give closest possible available rate (<= requested
1830 * freq) for all values of scr & cpsdvsr.
1832 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1833 while (scr <= SCR_MAX) {
1834 tmp = spi_rate(rate, cpsdvsr, scr);
1839 * If found exact value, update and break.
1840 * If found more closer value, update and continue.
1842 else if ((tmp == freq) || (tmp > best_freq)) {
1844 best_cpsdvsr = cpsdvsr;
1856 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1857 clk_freq->scr = (u8) (best_scr & 0xFF);
1858 dev_dbg(&pl022->adev->dev,
1859 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1861 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1862 clk_freq->cpsdvsr, clk_freq->scr);
1868 * A piece of default chip info unless the platform
1871 static const struct pl022_config_chip pl022_default_chip_info = {
1872 .com_mode = POLLING_TRANSFER,
1873 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1874 .hierarchy = SSP_SLAVE,
1875 .slave_tx_disable = DO_NOT_DRIVE_TX,
1876 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1877 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1878 .ctrl_len = SSP_BITS_8,
1879 .wait_state = SSP_MWIRE_WAIT_ZERO,
1880 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1881 .cs_control = null_cs_control,
1885 * pl022_setup - setup function registered to SPI master framework
1886 * @spi: spi device which is requesting setup
1888 * This function is registered to the SPI framework for this SPI master
1889 * controller. If it is the first time when setup is called by this device,
1890 * this function will initialize the runtime state for this chip and save
1891 * the same in the device structure. Else it will update the runtime info
1892 * with the updated chip info. Nothing is really being written to the
1893 * controller hardware here, that is not done until the actual transfer
1896 static int pl022_setup(struct spi_device *spi)
1898 struct pl022_config_chip const *chip_info;
1899 struct chip_data *chip;
1900 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1902 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1903 unsigned int bits = spi->bits_per_word;
1906 if (!spi->max_speed_hz)
1909 /* Get controller_state if one is supplied */
1910 chip = spi_get_ctldata(spi);
1913 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1916 "cannot allocate controller state\n");
1920 "allocated memory for controller's runtime state\n");
1923 /* Get controller data if one is supplied */
1924 chip_info = spi->controller_data;
1926 if (chip_info == NULL) {
1927 chip_info = &pl022_default_chip_info;
1928 /* spi_board_info.controller_data not is supplied */
1930 "using default controller_data settings\n");
1933 "using user supplied controller_data settings\n");
1936 * We can override with custom divisors, else we use the board
1939 if ((0 == chip_info->clk_freq.cpsdvsr)
1940 && (0 == chip_info->clk_freq.scr)) {
1941 status = calculate_effective_freq(pl022,
1945 goto err_config_params;
1947 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1948 if ((clk_freq.cpsdvsr % 2) != 0)
1950 clk_freq.cpsdvsr - 1;
1952 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1953 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1956 "cpsdvsr is configured incorrectly\n");
1957 goto err_config_params;
1960 status = verify_controller_parameters(pl022, chip_info);
1962 dev_err(&spi->dev, "controller data is incorrect");
1963 goto err_config_params;
1966 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1967 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1969 /* Now set controller state based on controller data */
1970 chip->xfer_type = chip_info->com_mode;
1971 if (!chip_info->cs_control) {
1972 chip->cs_control = null_cs_control;
1974 "chip select function is NULL for this chip\n");
1976 chip->cs_control = chip_info->cs_control;
1979 /* PL022 doesn't support less than 4-bits */
1981 goto err_config_params;
1982 } else if (bits <= 8) {
1983 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1985 chip->read = READING_U8;
1986 chip->write = WRITING_U8;
1987 } else if (bits <= 16) {
1988 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1990 chip->read = READING_U16;
1991 chip->write = WRITING_U16;
1993 if (pl022->vendor->max_bpw >= 32) {
1994 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1996 chip->read = READING_U32;
1997 chip->write = WRITING_U32;
2000 "illegal data size for this controller!\n");
2002 "a standard pl022 can only handle "
2003 "1 <= n <= 16 bit words\n");
2005 goto err_config_params;
2009 /* Now Initialize all register settings required for this chip */
2014 if ((chip_info->com_mode == DMA_TRANSFER)
2015 && ((pl022->master_info)->enable_dma)) {
2016 chip->enable_dma = true;
2017 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
2018 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2019 SSP_DMACR_MASK_RXDMAE, 0);
2020 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
2021 SSP_DMACR_MASK_TXDMAE, 1);
2023 chip->enable_dma = false;
2024 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
2025 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2026 SSP_DMACR_MASK_RXDMAE, 0);
2027 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
2028 SSP_DMACR_MASK_TXDMAE, 1);
2031 chip->cpsr = clk_freq.cpsdvsr;
2033 /* Special setup for the ST micro extended control registers */
2034 if (pl022->vendor->extended_cr) {
2037 if (pl022->vendor->pl023) {
2038 /* These bits are only in the PL023 */
2039 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
2040 SSP_CR1_MASK_FBCLKDEL_ST, 13);
2042 /* These bits are in the PL022 but not PL023 */
2043 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
2044 SSP_CR0_MASK_HALFDUP_ST, 5);
2045 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
2046 SSP_CR0_MASK_CSS_ST, 16);
2047 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2048 SSP_CR0_MASK_FRF_ST, 21);
2049 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2050 SSP_CR1_MASK_MWAIT_ST, 6);
2052 SSP_WRITE_BITS(chip->cr0, bits - 1,
2053 SSP_CR0_MASK_DSS_ST, 0);
2055 if (spi->mode & SPI_LSB_FIRST) {
2062 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2063 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2064 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2065 SSP_CR1_MASK_RXIFLSEL_ST, 7);
2066 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2067 SSP_CR1_MASK_TXIFLSEL_ST, 10);
2069 SSP_WRITE_BITS(chip->cr0, bits - 1,
2070 SSP_CR0_MASK_DSS, 0);
2071 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2072 SSP_CR0_MASK_FRF, 4);
2075 /* Stuff that is common for all versions */
2076 if (spi->mode & SPI_CPOL)
2077 tmp = SSP_CLK_POL_IDLE_HIGH;
2079 tmp = SSP_CLK_POL_IDLE_LOW;
2080 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2082 if (spi->mode & SPI_CPHA)
2083 tmp = SSP_CLK_SECOND_EDGE;
2085 tmp = SSP_CLK_FIRST_EDGE;
2086 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2088 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2089 /* Loopback is available on all versions except PL023 */
2090 if (pl022->vendor->loopback) {
2091 if (spi->mode & SPI_LOOP)
2092 tmp = LOOPBACK_ENABLED;
2094 tmp = LOOPBACK_DISABLED;
2095 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2097 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2098 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2099 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2102 /* Save controller_state */
2103 spi_set_ctldata(spi, chip);
2106 spi_set_ctldata(spi, NULL);
2112 * pl022_cleanup - cleanup function registered to SPI master framework
2113 * @spi: spi device which is requesting cleanup
2115 * This function is registered to the SPI framework for this SPI master
2116 * controller. It will free the runtime state of chip.
2118 static void pl022_cleanup(struct spi_device *spi)
2120 struct chip_data *chip = spi_get_ctldata(spi);
2122 spi_set_ctldata(spi, NULL);
2126 static int __devinit
2127 pl022_probe(struct amba_device *adev, const struct amba_id *id)
2129 struct device *dev = &adev->dev;
2130 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2131 struct spi_master *master;
2132 struct pl022 *pl022 = NULL; /*Data for this driver */
2135 dev_info(&adev->dev,
2136 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2137 if (platform_info == NULL) {
2138 dev_err(&adev->dev, "probe - no platform data supplied\n");
2143 /* Allocate master with space for data */
2144 master = spi_alloc_master(dev, sizeof(struct pl022));
2145 if (master == NULL) {
2146 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2151 pl022 = spi_master_get_devdata(master);
2152 pl022->master = master;
2153 pl022->master_info = platform_info;
2155 pl022->vendor = id->data;
2158 * Bus Number Which has been Assigned to this SSP controller
2161 master->bus_num = platform_info->bus_id;
2162 master->num_chipselect = platform_info->num_chipselect;
2163 master->cleanup = pl022_cleanup;
2164 master->setup = pl022_setup;
2165 master->transfer = pl022_transfer;
2168 * Supports mode 0-3, loopback, and active low CS. Transfers are
2169 * always MS bit first on the original pl022.
2171 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2172 if (pl022->vendor->extended_cr)
2173 master->mode_bits |= SPI_LSB_FIRST;
2175 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2177 status = amba_request_regions(adev, NULL);
2179 goto err_no_ioregion;
2181 pl022->phybase = adev->res.start;
2182 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2183 if (pl022->virtbase == NULL) {
2185 goto err_no_ioremap;
2187 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2188 adev->res.start, pl022->virtbase);
2190 pl022->clk = clk_get(&adev->dev, NULL);
2191 if (IS_ERR(pl022->clk)) {
2192 status = PTR_ERR(pl022->clk);
2193 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2197 status = clk_prepare(pl022->clk);
2199 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2203 status = clk_enable(pl022->clk);
2205 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2210 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2211 SSP_CR1(pl022->virtbase));
2212 load_ssp_default_config(pl022);
2214 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2217 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2221 /* Get DMA channels */
2222 if (platform_info->enable_dma) {
2223 status = pl022_dma_probe(pl022);
2225 platform_info->enable_dma = 0;
2228 /* Initialize and start queue */
2229 status = init_queue(pl022);
2231 dev_err(&adev->dev, "probe - problem initializing queue\n");
2232 goto err_init_queue;
2234 status = start_queue(pl022);
2236 dev_err(&adev->dev, "probe - problem starting queue\n");
2237 goto err_start_queue;
2239 /* Register with the SPI framework */
2240 amba_set_drvdata(adev, pl022);
2241 status = spi_register_master(master);
2244 "probe - problem registering spi master\n");
2245 goto err_spi_register;
2247 dev_dbg(dev, "probe succeeded\n");
2249 /* let runtime pm put suspend */
2250 pm_runtime_put(dev);
2256 destroy_queue(pl022);
2257 if (platform_info->enable_dma)
2258 pl022_dma_remove(pl022);
2260 free_irq(adev->irq[0], pl022);
2262 clk_disable(pl022->clk);
2264 clk_unprepare(pl022->clk);
2266 clk_put(pl022->clk);
2268 iounmap(pl022->virtbase);
2270 amba_release_regions(adev);
2272 spi_master_put(master);
2278 static int __devexit
2279 pl022_remove(struct amba_device *adev)
2281 struct pl022 *pl022 = amba_get_drvdata(adev);
2287 * undo pm_runtime_put() in probe. I assume that we're not
2288 * accessing the primecell here.
2290 pm_runtime_get_noresume(&adev->dev);
2292 /* Remove the queue */
2293 if (destroy_queue(pl022) != 0)
2294 dev_err(&adev->dev, "queue remove failed\n");
2295 load_ssp_default_config(pl022);
2296 if (pl022->master_info->enable_dma)
2297 pl022_dma_remove(pl022);
2299 free_irq(adev->irq[0], pl022);
2300 clk_disable(pl022->clk);
2301 clk_unprepare(pl022->clk);
2302 clk_put(pl022->clk);
2303 iounmap(pl022->virtbase);
2304 amba_release_regions(adev);
2305 tasklet_disable(&pl022->pump_transfers);
2306 spi_unregister_master(pl022->master);
2307 spi_master_put(pl022->master);
2308 amba_set_drvdata(adev, NULL);
2312 #ifdef CONFIG_SUSPEND
2313 static int pl022_suspend(struct device *dev)
2315 struct pl022 *pl022 = dev_get_drvdata(dev);
2318 status = stop_queue(pl022);
2320 dev_warn(dev, "suspend cannot stop queue\n");
2324 dev_dbg(dev, "suspended\n");
2328 static int pl022_resume(struct device *dev)
2330 struct pl022 *pl022 = dev_get_drvdata(dev);
2333 /* Start the queue running */
2334 status = start_queue(pl022);
2336 dev_err(dev, "problem starting queue (%d)\n", status);
2338 dev_dbg(dev, "resumed\n");
2342 #endif /* CONFIG_PM */
2344 #ifdef CONFIG_PM_RUNTIME
2345 static int pl022_runtime_suspend(struct device *dev)
2347 struct pl022 *pl022 = dev_get_drvdata(dev);
2349 clk_disable(pl022->clk);
2350 amba_vcore_disable(pl022->adev);
2355 static int pl022_runtime_resume(struct device *dev)
2357 struct pl022 *pl022 = dev_get_drvdata(dev);
2359 amba_vcore_enable(pl022->adev);
2360 clk_enable(pl022->clk);
2366 static const struct dev_pm_ops pl022_dev_pm_ops = {
2367 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2368 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2371 static struct vendor_data vendor_arm = {
2375 .extended_cr = false,
2380 static struct vendor_data vendor_st = {
2384 .extended_cr = true,
2389 static struct vendor_data vendor_st_pl023 = {
2393 .extended_cr = true,
2398 static struct vendor_data vendor_db5500_pl023 = {
2402 .extended_cr = true,
2407 static struct amba_id pl022_ids[] = {
2410 * ARM PL022 variant, this has a 16bit wide
2411 * and 8 locations deep TX/RX FIFO
2415 .data = &vendor_arm,
2419 * ST Micro derivative, this has 32bit wide
2420 * and 32 locations deep TX/RX FIFO
2428 * ST-Ericsson derivative "PL023" (this is not
2429 * an official ARM number), this is a PL022 SSP block
2430 * stripped to SPI mode only, it has 32bit wide
2431 * and 32 locations deep TX/RX FIFO but no extended
2436 .data = &vendor_st_pl023,
2441 .data = &vendor_db5500_pl023,
2446 static struct amba_driver pl022_driver = {
2448 .name = "ssp-pl022",
2449 .pm = &pl022_dev_pm_ops,
2451 .id_table = pl022_ids,
2452 .probe = pl022_probe,
2453 .remove = __devexit_p(pl022_remove),
2456 static int __init pl022_init(void)
2458 return amba_driver_register(&pl022_driver);
2460 subsys_initcall(pl022_init);
2462 static void __exit pl022_exit(void)
2464 amba_driver_unregister(&pl022_driver);
2466 module_exit(pl022_exit);
2468 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2469 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2470 MODULE_LICENSE("GPL");