2 * SPI_PPC4XX SPI controller driver.
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
8 * Based in part on drivers/spi/spi_s3c24xx.c
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/sched.h>
29 #include <linux/slab.h>
30 #include <linux/errno.h>
31 #include <linux/wait.h>
32 #include <linux/of_platform.h>
33 #include <linux/of_gpio.h>
34 #include <linux/interrupt.h>
35 #include <linux/delay.h>
37 #include <linux/gpio.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/spi_bitbang.h>
43 #include <asm/dcr-regs.h>
45 /* bits in mode register - bit 0 is MSb */
48 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
49 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
50 * Note: This is the inverse of CPHA.
52 #define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
54 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
55 #define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
58 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
59 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
60 * Note: This is identical to SPI_LSB_FIRST.
62 #define SPI_PPC4XX_MODE_RD (0x80 >> 5)
65 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
66 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
67 * Note: This is identical to CPOL.
69 #define SPI_PPC4XX_MODE_CI (0x80 >> 6)
72 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
73 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
75 #define SPI_PPC4XX_MODE_IL (0x80 >> 7)
77 /* bits in control register */
78 /* starts a transfer when set */
79 #define SPI_PPC4XX_CR_STR (0x80 >> 7)
81 /* bits in status register */
82 /* port is busy with a transfer */
83 #define SPI_PPC4XX_SR_BSY (0x80 >> 6)
85 #define SPI_PPC4XX_SR_RBR (0x80 >> 7)
87 /* clock settings (SCP and CI) for various SPI modes */
88 #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
89 #define SPI_CLK_MODE1 (0 | 0)
90 #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
91 #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
93 #define DRIVER_NAME "spi_ppc4xx_of"
95 struct spi_ppc4xx_regs {
103 * Clock divisor modulus register
104 * This uses the following formula:
105 * SCPClkOut = OPBCLK/(4(CDM + 1))
107 * CDM = (OPBCLK/4*SCPClkOut) - 1
113 /* SPI Controller driver's private data. */
115 /* bitbang has to be first */
116 struct spi_bitbang bitbang;
117 struct completion done;
122 /* need this to set the SPI clock */
123 unsigned int opb_freq;
129 const unsigned char *tx;
134 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
135 struct spi_master *master;
139 /* need this so we can set the clock in the chipselect routine */
140 struct spi_ppc4xx_cs {
144 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
146 struct ppc4xx_spi *hw;
149 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
150 t->tx_buf, t->rx_buf, t->len);
152 hw = spi_master_get_devdata(spi->master);
159 /* send the first byte */
160 data = hw->tx ? hw->tx[0] : 0;
161 out_8(&hw->regs->txd, data);
162 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
163 wait_for_completion(&hw->done);
168 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
170 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
171 struct spi_ppc4xx_cs *cs = spi->controller_state;
177 /* Start with the generic configuration for this device. */
178 bits_per_word = spi->bits_per_word;
179 speed = spi->max_speed_hz;
182 * Modify the configuration if the transfer overrides it. Do not allow
183 * the transfer to overwrite the generic configuration with zeros.
186 if (t->bits_per_word)
187 bits_per_word = t->bits_per_word;
190 speed = min(t->speed_hz, spi->max_speed_hz);
193 if (!speed || (speed > spi->max_speed_hz)) {
194 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
198 /* Write new configuration */
199 out_8(&hw->regs->mode, cs->mode);
202 /* opb_freq was already divided by 4 */
203 scr = (hw->opb_freq / speed) - 1;
205 cdm = min(scr, 0xff);
207 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
209 if (in_8(&hw->regs->cdm) != cdm)
210 out_8(&hw->regs->cdm, cdm);
212 spin_lock(&hw->bitbang.lock);
213 if (!hw->bitbang.busy) {
214 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
215 /* Need to ndelay here? */
217 spin_unlock(&hw->bitbang.lock);
222 static int spi_ppc4xx_setup(struct spi_device *spi)
224 struct spi_ppc4xx_cs *cs = spi->controller_state;
226 if (!spi->max_speed_hz) {
227 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
232 cs = kzalloc(sizeof *cs, GFP_KERNEL);
235 spi->controller_state = cs;
239 * We set all bits of the SPI0_MODE register, so,
240 * no need to read-modify-write
242 cs->mode = SPI_PPC4XX_MODE_SPE;
244 switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
246 cs->mode |= SPI_CLK_MODE0;
249 cs->mode |= SPI_CLK_MODE1;
252 cs->mode |= SPI_CLK_MODE2;
255 cs->mode |= SPI_CLK_MODE3;
259 if (spi->mode & SPI_LSB_FIRST)
260 cs->mode |= SPI_PPC4XX_MODE_RD;
265 static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
267 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
268 unsigned int cs = spi->chip_select;
272 * If there are no chip selects at all, or if this is the special
273 * case of a non-existent (dummy) chip select, do nothing.
276 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
279 cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
280 if (value == BITBANG_CS_INACTIVE)
283 gpio_set_value(hw->gpios[cs], cspol);
286 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
288 struct ppc4xx_spi *hw;
293 hw = (struct ppc4xx_spi *)dev_id;
295 status = in_8(&hw->regs->sr);
300 * BSY de-asserts one cycle after the transfer is complete. The
301 * interrupt is asserted after the transfer is complete. The exact
302 * relationship is not documented, hence this code.
305 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
309 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
312 lstatus = in_8(&hw->regs->sr);
313 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
316 dev_err(hw->dev, "busywait: too many loops!\n");
320 /* status is always 1 (RBR) here */
321 status = in_8(&hw->regs->sr);
322 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
329 /* RBR triggered this interrupt. Therefore, data must be ready. */
330 data = in_8(&hw->regs->rxd);
332 hw->rx[count] = data;
336 if (count < hw->len) {
337 data = hw->tx ? hw->tx[count] : 0;
338 out_8(&hw->regs->txd, data);
339 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
347 static void spi_ppc4xx_cleanup(struct spi_device *spi)
349 kfree(spi->controller_state);
352 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
355 * On all 4xx PPC's the SPI bus is shared/multiplexed with
356 * the 2nd I2C bus. We need to enable the the SPI bus before
360 /* need to clear bit 14 to enable SPC */
361 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
364 static void free_gpios(struct ppc4xx_spi *hw)
366 if (hw->master->num_chipselect) {
368 for (i = 0; i < hw->master->num_chipselect; i++)
369 if (gpio_is_valid(hw->gpios[i]))
370 gpio_free(hw->gpios[i]);
378 * platform_device layer stuff...
380 static int spi_ppc4xx_of_probe(struct platform_device *op)
382 struct ppc4xx_spi *hw;
383 struct spi_master *master;
384 struct spi_bitbang *bbp;
385 struct resource resource;
386 struct device_node *np = op->dev.of_node;
387 struct device *dev = &op->dev;
388 struct device_node *opbnp;
391 const unsigned int *clk;
393 master = spi_alloc_master(dev, sizeof *hw);
396 master->dev.of_node = np;
397 platform_set_drvdata(op, master);
398 hw = spi_master_get_devdata(master);
399 hw->master = spi_master_get(master);
402 init_completion(&hw->done);
405 * A count of zero implies a single SPI device without any chip-select.
406 * Note that of_gpio_count counts all gpios assigned to this spi master.
407 * This includes both "null" gpio's and real ones.
409 num_gpios = of_gpio_count(np);
413 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
419 for (i = 0; i < num_gpios; i++) {
421 enum of_gpio_flags flags;
423 gpio = of_get_gpio_flags(np, i, &flags);
426 if (gpio_is_valid(gpio)) {
427 /* Real CS - set the initial state. */
428 ret = gpio_request(gpio, np->name);
430 dev_err(dev, "can't request gpio "
431 "#%d: %d\n", i, ret);
435 gpio_direction_output(gpio,
436 !!(flags & OF_GPIO_ACTIVE_LOW));
437 } else if (gpio == -EEXIST) {
438 ; /* No CS, but that's OK. */
440 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
447 /* Setup the state for the bitbang driver */
449 bbp->master = hw->master;
450 bbp->setup_transfer = spi_ppc4xx_setupxfer;
451 bbp->chipselect = spi_ppc4xx_chipsel;
452 bbp->txrx_bufs = spi_ppc4xx_txrx;
454 bbp->master->setup = spi_ppc4xx_setup;
455 bbp->master->cleanup = spi_ppc4xx_cleanup;
456 bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
458 /* the spi->mode bits understood by this driver: */
459 bbp->master->mode_bits =
460 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
462 /* this many pins in all GPIO controllers */
463 bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0;
465 /* Get the clock for the OPB */
466 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
468 dev_err(dev, "OPB: cannot find node\n");
472 /* Get the clock (Hz) for the OPB */
473 clk = of_get_property(opbnp, "clock-frequency", NULL);
475 dev_err(dev, "OPB: no clock-frequency property set\n");
484 ret = of_address_to_resource(np, 0, &resource);
486 dev_err(dev, "error while parsing device node resource\n");
489 hw->mapbase = resource.start;
490 hw->mapsize = resource_size(&resource);
493 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
494 dev_err(dev, "too small to map registers\n");
500 hw->irqnum = irq_of_parse_and_map(np, 0);
501 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
502 0, "spi_ppc4xx_of", (void *)hw);
504 dev_err(dev, "unable to allocate interrupt\n");
508 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
509 dev_err(dev, "resource unavailable\n");
511 goto request_mem_error;
514 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
517 dev_err(dev, "unable to memory map registers\n");
522 spi_ppc4xx_enable(hw);
524 /* Finally register our spi controller */
526 ret = spi_bitbang_start(bbp);
528 dev_err(dev, "failed to register SPI master\n");
532 dev_info(dev, "driver initialized\n");
539 release_mem_region(hw->mapbase, hw->mapsize);
541 free_irq(hw->irqnum, hw);
545 spi_master_put(master);
547 dev_err(dev, "initialization failed\n");
551 static int spi_ppc4xx_of_remove(struct platform_device *op)
553 struct spi_master *master = platform_get_drvdata(op);
554 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
556 spi_bitbang_stop(&hw->bitbang);
557 release_mem_region(hw->mapbase, hw->mapsize);
558 free_irq(hw->irqnum, hw);
564 static const struct of_device_id spi_ppc4xx_of_match[] = {
565 { .compatible = "ibm,ppc4xx-spi", },
569 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
571 static struct platform_driver spi_ppc4xx_of_driver = {
572 .probe = spi_ppc4xx_of_probe,
573 .remove = spi_ppc4xx_of_remove,
576 .owner = THIS_MODULE,
577 .of_match_table = spi_ppc4xx_of_match,
580 module_platform_driver(spi_ppc4xx_of_driver);
582 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
583 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
584 MODULE_LICENSE("GPL");