2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/kthread.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/of_device.h>
36 #include <linux/spi/spi.h>
37 #include <linux/clk/tegra.h>
39 #define SLINK_COMMAND 0x000
40 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
41 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
42 #define SLINK_BOTH_EN (1 << 10)
43 #define SLINK_CS_SW (1 << 11)
44 #define SLINK_CS_VALUE (1 << 12)
45 #define SLINK_CS_POLARITY (1 << 13)
46 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
47 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
48 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
49 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
50 #define SLINK_IDLE_SDA_MASK (3 << 16)
51 #define SLINK_CS_POLARITY1 (1 << 20)
52 #define SLINK_CK_SDA (1 << 21)
53 #define SLINK_CS_POLARITY2 (1 << 22)
54 #define SLINK_CS_POLARITY3 (1 << 23)
55 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
56 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
57 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
58 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
59 #define SLINK_IDLE_SCLK_MASK (3 << 24)
60 #define SLINK_M_S (1 << 28)
61 #define SLINK_WAIT (1 << 29)
62 #define SLINK_GO (1 << 30)
63 #define SLINK_ENB (1 << 31)
65 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
67 #define SLINK_COMMAND2 0x004
68 #define SLINK_LSBFE (1 << 0)
69 #define SLINK_SSOE (1 << 1)
70 #define SLINK_SPIE (1 << 4)
71 #define SLINK_BIDIROE (1 << 6)
72 #define SLINK_MODFEN (1 << 7)
73 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
74 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
75 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
76 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
77 #define SLINK_FIFO_REFILLS_0 (0 << 22)
78 #define SLINK_FIFO_REFILLS_1 (1 << 22)
79 #define SLINK_FIFO_REFILLS_2 (2 << 22)
80 #define SLINK_FIFO_REFILLS_3 (3 << 22)
81 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
82 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
83 #define SLINK_SPC0 (1 << 29)
84 #define SLINK_TXEN (1 << 30)
85 #define SLINK_RXEN (1 << 31)
87 #define SLINK_STATUS 0x008
88 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
89 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
90 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
91 #define SLINK_MODF (1 << 16)
92 #define SLINK_RX_UNF (1 << 18)
93 #define SLINK_TX_OVF (1 << 19)
94 #define SLINK_TX_FULL (1 << 20)
95 #define SLINK_TX_EMPTY (1 << 21)
96 #define SLINK_RX_FULL (1 << 22)
97 #define SLINK_RX_EMPTY (1 << 23)
98 #define SLINK_TX_UNF (1 << 24)
99 #define SLINK_RX_OVF (1 << 25)
100 #define SLINK_TX_FLUSH (1 << 26)
101 #define SLINK_RX_FLUSH (1 << 27)
102 #define SLINK_SCLK (1 << 28)
103 #define SLINK_ERR (1 << 29)
104 #define SLINK_RDY (1 << 30)
105 #define SLINK_BSY (1 << 31)
106 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
107 SLINK_TX_UNF | SLINK_RX_OVF)
109 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
111 #define SLINK_MAS_DATA 0x010
112 #define SLINK_SLAVE_DATA 0x014
114 #define SLINK_DMA_CTL 0x018
115 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
116 #define SLINK_TX_TRIG_1 (0 << 16)
117 #define SLINK_TX_TRIG_4 (1 << 16)
118 #define SLINK_TX_TRIG_8 (2 << 16)
119 #define SLINK_TX_TRIG_16 (3 << 16)
120 #define SLINK_TX_TRIG_MASK (3 << 16)
121 #define SLINK_RX_TRIG_1 (0 << 18)
122 #define SLINK_RX_TRIG_4 (1 << 18)
123 #define SLINK_RX_TRIG_8 (2 << 18)
124 #define SLINK_RX_TRIG_16 (3 << 18)
125 #define SLINK_RX_TRIG_MASK (3 << 18)
126 #define SLINK_PACKED (1 << 20)
127 #define SLINK_PACK_SIZE_4 (0 << 21)
128 #define SLINK_PACK_SIZE_8 (1 << 21)
129 #define SLINK_PACK_SIZE_16 (2 << 21)
130 #define SLINK_PACK_SIZE_32 (3 << 21)
131 #define SLINK_PACK_SIZE_MASK (3 << 21)
132 #define SLINK_IE_TXC (1 << 26)
133 #define SLINK_IE_RXC (1 << 27)
134 #define SLINK_DMA_EN (1 << 31)
136 #define SLINK_STATUS2 0x01c
137 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
138 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
139 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
141 #define SLINK_TX_FIFO 0x100
142 #define SLINK_RX_FIFO 0x180
144 #define DATA_DIR_TX (1 << 0)
145 #define DATA_DIR_RX (1 << 1)
147 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
149 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
150 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
151 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
153 #define SLINK_STATUS2_RESET \
154 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
156 #define MAX_CHIP_SELECT 4
157 #define SLINK_FIFO_DEPTH 32
159 struct tegra_slink_chip_data {
163 struct tegra_slink_data {
165 struct spi_master *master;
166 const struct tegra_slink_chip_data *chip_data;
174 u32 spi_max_frequency;
177 struct spi_device *cur_spi;
180 unsigned words_per_32bit;
181 unsigned bytes_per_word;
182 unsigned curr_dma_words;
183 unsigned cur_direction;
188 unsigned dma_buf_size;
189 unsigned max_buf_size;
190 bool is_curr_dma_xfer;
192 struct completion rx_dma_complete;
193 struct completion tx_dma_complete;
199 unsigned long packed_size;
205 u32 def_command2_reg;
207 struct completion xfer_completion;
208 struct spi_transfer *curr_xfer;
209 struct dma_chan *rx_dma_chan;
211 dma_addr_t rx_dma_phys;
212 struct dma_async_tx_descriptor *rx_dma_desc;
214 struct dma_chan *tx_dma_chan;
216 dma_addr_t tx_dma_phys;
217 struct dma_async_tx_descriptor *tx_dma_desc;
220 static int tegra_slink_runtime_suspend(struct device *dev);
221 static int tegra_slink_runtime_resume(struct device *dev);
223 static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi,
226 return readl(tspi->base + reg);
229 static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
230 unsigned long val, unsigned long reg)
232 writel(val, tspi->base + reg);
234 /* Read back register to make sure that register writes completed */
235 if (reg != SLINK_TX_FIFO)
236 readl(tspi->base + SLINK_MAS_DATA);
239 static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
242 unsigned long val_write = 0;
244 val = tegra_slink_readl(tspi, SLINK_STATUS);
246 /* Write 1 to clear status register */
247 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
248 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
251 static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
252 struct spi_transfer *t)
256 switch (tspi->bytes_per_word) {
258 val = SLINK_PACK_SIZE_4;
261 val = SLINK_PACK_SIZE_8;
264 val = SLINK_PACK_SIZE_16;
267 val = SLINK_PACK_SIZE_32;
275 static unsigned tegra_slink_calculate_curr_xfer_param(
276 struct spi_device *spi, struct tegra_slink_data *tspi,
277 struct spi_transfer *t)
279 unsigned remain_len = t->len - tspi->cur_pos;
281 unsigned bits_per_word ;
283 unsigned total_fifo_words;
285 bits_per_word = t->bits_per_word;
286 tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
288 if (bits_per_word == 8 || bits_per_word == 16) {
290 tspi->words_per_32bit = 32/bits_per_word;
293 tspi->words_per_32bit = 1;
295 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
297 if (tspi->is_packed) {
298 max_len = min(remain_len, tspi->max_buf_size);
299 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
300 total_fifo_words = max_len/4;
302 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
303 max_word = min(max_word, tspi->max_buf_size/4);
304 tspi->curr_dma_words = max_word;
305 total_fifo_words = max_word;
307 return total_fifo_words;
310 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
311 struct tegra_slink_data *tspi, struct spi_transfer *t)
314 unsigned tx_empty_count;
315 unsigned long fifo_status;
316 unsigned max_n_32bit;
319 unsigned int written_words;
320 unsigned fifo_words_left;
321 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
323 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
324 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
326 if (tspi->is_packed) {
327 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
328 written_words = min(fifo_words_left, tspi->curr_dma_words);
329 nbytes = written_words * tspi->bytes_per_word;
330 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
331 for (count = 0; count < max_n_32bit; count++) {
333 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
334 x |= (*tx_buf++) << (i*8);
335 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
338 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
339 written_words = max_n_32bit;
340 nbytes = written_words * tspi->bytes_per_word;
341 for (count = 0; count < max_n_32bit; count++) {
343 for (i = 0; nbytes && (i < tspi->bytes_per_word);
345 x |= ((*tx_buf++) << i*8);
346 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
349 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
350 return written_words;
353 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
354 struct tegra_slink_data *tspi, struct spi_transfer *t)
356 unsigned rx_full_count;
357 unsigned long fifo_status;
360 unsigned int read_words = 0;
362 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
364 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
365 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
366 if (tspi->is_packed) {
367 len = tspi->curr_dma_words * tspi->bytes_per_word;
368 for (count = 0; count < rx_full_count; count++) {
369 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
370 for (i = 0; len && (i < 4); i++, len--)
371 *rx_buf++ = (x >> i*8) & 0xFF;
373 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
374 read_words += tspi->curr_dma_words;
376 for (count = 0; count < rx_full_count; count++) {
377 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
378 for (i = 0; (i < tspi->bytes_per_word); i++)
379 *rx_buf++ = (x >> (i*8)) & 0xFF;
381 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
382 read_words += rx_full_count;
387 static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
388 struct tegra_slink_data *tspi, struct spi_transfer *t)
392 /* Make the dma buffer to read by cpu */
393 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
394 tspi->dma_buf_size, DMA_TO_DEVICE);
396 if (tspi->is_packed) {
397 len = tspi->curr_dma_words * tspi->bytes_per_word;
398 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
402 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
403 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
406 for (count = 0; count < tspi->curr_dma_words; count++) {
408 for (i = 0; consume && (i < tspi->bytes_per_word);
410 x |= ((*tx_buf++) << i * 8);
411 tspi->tx_dma_buf[count] = x;
414 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
416 /* Make the dma buffer to read by dma */
417 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
418 tspi->dma_buf_size, DMA_TO_DEVICE);
421 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
422 struct tegra_slink_data *tspi, struct spi_transfer *t)
426 /* Make the dma buffer to read by cpu */
427 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
428 tspi->dma_buf_size, DMA_FROM_DEVICE);
430 if (tspi->is_packed) {
431 len = tspi->curr_dma_words * tspi->bytes_per_word;
432 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
436 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
438 unsigned int rx_mask, bits_per_word;
440 bits_per_word = t->bits_per_word;
441 rx_mask = (1 << bits_per_word) - 1;
442 for (count = 0; count < tspi->curr_dma_words; count++) {
443 x = tspi->rx_dma_buf[count];
445 for (i = 0; (i < tspi->bytes_per_word); i++)
446 *rx_buf++ = (x >> (i*8)) & 0xFF;
449 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
451 /* Make the dma buffer to read by dma */
452 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
453 tspi->dma_buf_size, DMA_FROM_DEVICE);
456 static void tegra_slink_dma_complete(void *args)
458 struct completion *dma_complete = args;
460 complete(dma_complete);
463 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
465 INIT_COMPLETION(tspi->tx_dma_complete);
466 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
467 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
468 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
469 if (!tspi->tx_dma_desc) {
470 dev_err(tspi->dev, "Not able to get desc for Tx\n");
474 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
475 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
477 dmaengine_submit(tspi->tx_dma_desc);
478 dma_async_issue_pending(tspi->tx_dma_chan);
482 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
484 INIT_COMPLETION(tspi->rx_dma_complete);
485 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
486 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
487 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
488 if (!tspi->rx_dma_desc) {
489 dev_err(tspi->dev, "Not able to get desc for Rx\n");
493 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
494 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
496 dmaengine_submit(tspi->rx_dma_desc);
497 dma_async_issue_pending(tspi->rx_dma_chan);
501 static int tegra_slink_start_dma_based_transfer(
502 struct tegra_slink_data *tspi, struct spi_transfer *t)
505 unsigned long test_val;
508 unsigned long status;
510 /* Make sure that Rx and Tx fifo are empty */
511 status = tegra_slink_readl(tspi, SLINK_STATUS);
512 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
514 "Rx/Tx fifo are not empty status 0x%08lx\n", status);
518 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
519 val |= tspi->packed_size;
521 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
524 len = tspi->curr_dma_words * 4;
526 /* Set attention level based on length of transfer */
528 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
529 else if (((len) >> 4) & 0x1)
530 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
532 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
534 if (tspi->cur_direction & DATA_DIR_TX)
537 if (tspi->cur_direction & DATA_DIR_RX)
540 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
541 tspi->dma_control_reg = val;
543 if (tspi->cur_direction & DATA_DIR_TX) {
544 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
546 ret = tegra_slink_start_tx_dma(tspi, len);
549 "Starting tx dma failed, err %d\n", ret);
553 /* Wait for tx fifo to be fill before starting slink */
554 test_val = tegra_slink_readl(tspi, SLINK_STATUS);
555 while (!(test_val & SLINK_TX_FULL))
556 test_val = tegra_slink_readl(tspi, SLINK_STATUS);
559 if (tspi->cur_direction & DATA_DIR_RX) {
560 /* Make the dma buffer to read by dma */
561 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
562 tspi->dma_buf_size, DMA_FROM_DEVICE);
564 ret = tegra_slink_start_rx_dma(tspi, len);
567 "Starting rx dma failed, err %d\n", ret);
568 if (tspi->cur_direction & DATA_DIR_TX)
569 dmaengine_terminate_all(tspi->tx_dma_chan);
573 tspi->is_curr_dma_xfer = true;
574 if (tspi->is_packed) {
576 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
577 /* HW need small delay after settign Packed mode */
580 tspi->dma_control_reg = val;
583 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
587 static int tegra_slink_start_cpu_based_transfer(
588 struct tegra_slink_data *tspi, struct spi_transfer *t)
593 val = tspi->packed_size;
594 if (tspi->cur_direction & DATA_DIR_TX)
597 if (tspi->cur_direction & DATA_DIR_RX)
600 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
601 tspi->dma_control_reg = val;
603 if (tspi->cur_direction & DATA_DIR_TX)
604 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
606 cur_words = tspi->curr_dma_words;
607 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
608 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
609 tspi->dma_control_reg = val;
611 tspi->is_curr_dma_xfer = false;
612 if (tspi->is_packed) {
614 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
618 tspi->dma_control_reg = val;
620 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
624 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
627 struct dma_chan *dma_chan;
631 struct dma_slave_config dma_sconfig;
635 dma_cap_set(DMA_SLAVE, mask);
636 dma_chan = dma_request_channel(mask, NULL, NULL);
639 "Dma channel is not available, will try later\n");
640 return -EPROBE_DEFER;
643 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
644 &dma_phys, GFP_KERNEL);
646 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
647 dma_release_channel(dma_chan);
651 dma_sconfig.slave_id = tspi->dma_req_sel;
653 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
654 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
655 dma_sconfig.src_maxburst = 0;
657 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
658 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
659 dma_sconfig.dst_maxburst = 0;
662 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
666 tspi->rx_dma_chan = dma_chan;
667 tspi->rx_dma_buf = dma_buf;
668 tspi->rx_dma_phys = dma_phys;
670 tspi->tx_dma_chan = dma_chan;
671 tspi->tx_dma_buf = dma_buf;
672 tspi->tx_dma_phys = dma_phys;
677 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
678 dma_release_channel(dma_chan);
682 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
687 struct dma_chan *dma_chan;
690 dma_buf = tspi->rx_dma_buf;
691 dma_chan = tspi->rx_dma_chan;
692 dma_phys = tspi->rx_dma_phys;
693 tspi->rx_dma_chan = NULL;
694 tspi->rx_dma_buf = NULL;
696 dma_buf = tspi->tx_dma_buf;
697 dma_chan = tspi->tx_dma_chan;
698 dma_phys = tspi->tx_dma_phys;
699 tspi->tx_dma_buf = NULL;
700 tspi->tx_dma_chan = NULL;
705 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
706 dma_release_channel(dma_chan);
709 static int tegra_slink_start_transfer_one(struct spi_device *spi,
710 struct spi_transfer *t, bool is_first_of_msg,
713 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
716 unsigned total_fifo_words;
718 unsigned long command;
719 unsigned long command2;
721 bits_per_word = t->bits_per_word;
723 if (speed != tspi->cur_speed) {
724 clk_set_rate(tspi->clk, speed * 4);
725 tspi->cur_speed = speed;
730 tspi->cur_rx_pos = 0;
731 tspi->cur_tx_pos = 0;
733 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
735 if (is_first_of_msg) {
736 tegra_slink_clear_status(tspi);
738 command = tspi->def_command_reg;
739 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
740 command |= SLINK_CS_SW | SLINK_CS_VALUE;
742 command2 = tspi->def_command2_reg;
743 command2 |= SLINK_SS_EN_CS(spi->chip_select);
745 command &= ~SLINK_MODES;
746 if (spi->mode & SPI_CPHA)
747 command |= SLINK_CK_SDA;
749 if (spi->mode & SPI_CPOL)
750 command |= SLINK_IDLE_SCLK_DRIVE_HIGH;
752 command |= SLINK_IDLE_SCLK_DRIVE_LOW;
754 command = tspi->command_reg;
755 command &= ~SLINK_BIT_LENGTH(~0);
756 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
758 command2 = tspi->command2_reg;
759 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
762 tegra_slink_writel(tspi, command, SLINK_COMMAND);
763 tspi->command_reg = command;
765 tspi->cur_direction = 0;
767 command2 |= SLINK_RXEN;
768 tspi->cur_direction |= DATA_DIR_RX;
771 command2 |= SLINK_TXEN;
772 tspi->cur_direction |= DATA_DIR_TX;
774 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
775 tspi->command2_reg = command2;
777 if (total_fifo_words > SLINK_FIFO_DEPTH)
778 ret = tegra_slink_start_dma_based_transfer(tspi, t);
780 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
784 static int tegra_slink_setup(struct spi_device *spi)
786 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
790 unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
797 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
799 spi->mode & SPI_CPOL ? "" : "~",
800 spi->mode & SPI_CPHA ? "" : "~",
803 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
805 /* Set speed to the spi max fequency if spi device has not set */
806 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
807 ret = pm_runtime_get_sync(tspi->dev);
809 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
813 spin_lock_irqsave(&tspi->lock, flags);
814 val = tspi->def_command_reg;
815 if (spi->mode & SPI_CS_HIGH)
816 val |= cs_pol_bit[spi->chip_select];
818 val &= ~cs_pol_bit[spi->chip_select];
819 tspi->def_command_reg = val;
820 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
821 spin_unlock_irqrestore(&tspi->lock, flags);
823 pm_runtime_put(tspi->dev);
827 static int tegra_slink_transfer_one_message(struct spi_master *master,
828 struct spi_message *msg)
830 bool is_first_msg = true;
832 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
833 struct spi_transfer *xfer;
834 struct spi_device *spi = msg->spi;
838 msg->actual_length = 0;
840 single_xfer = list_is_singular(&msg->transfers);
841 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
842 INIT_COMPLETION(tspi->xfer_completion);
843 ret = tegra_slink_start_transfer_one(spi, xfer,
844 is_first_msg, single_xfer);
847 "spi can not start transfer, err %d\n", ret);
850 is_first_msg = false;
851 ret = wait_for_completion_timeout(&tspi->xfer_completion,
853 if (WARN_ON(ret == 0)) {
855 "spi trasfer timeout, err %d\n", ret);
860 if (tspi->tx_status || tspi->rx_status) {
861 dev_err(tspi->dev, "Error in Transfer\n");
865 msg->actual_length += xfer->len;
866 if (xfer->cs_change && xfer->delay_usecs) {
867 tegra_slink_writel(tspi, tspi->def_command_reg,
869 udelay(xfer->delay_usecs);
874 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
875 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
877 spi_finalize_current_message(master);
881 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
883 struct spi_transfer *t = tspi->curr_xfer;
886 spin_lock_irqsave(&tspi->lock, flags);
887 if (tspi->tx_status || tspi->rx_status ||
888 (tspi->status_reg & SLINK_BSY)) {
890 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
892 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
893 tspi->command2_reg, tspi->dma_control_reg);
894 tegra_periph_reset_assert(tspi->clk);
896 tegra_periph_reset_deassert(tspi->clk);
897 complete(&tspi->xfer_completion);
901 if (tspi->cur_direction & DATA_DIR_RX)
902 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
904 if (tspi->cur_direction & DATA_DIR_TX)
905 tspi->cur_pos = tspi->cur_tx_pos;
907 tspi->cur_pos = tspi->cur_rx_pos;
909 if (tspi->cur_pos == t->len) {
910 complete(&tspi->xfer_completion);
914 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
915 tegra_slink_start_cpu_based_transfer(tspi, t);
917 spin_unlock_irqrestore(&tspi->lock, flags);
921 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
923 struct spi_transfer *t = tspi->curr_xfer;
926 unsigned total_fifo_words;
929 /* Abort dmas if any error */
930 if (tspi->cur_direction & DATA_DIR_TX) {
931 if (tspi->tx_status) {
932 dmaengine_terminate_all(tspi->tx_dma_chan);
935 wait_status = wait_for_completion_interruptible_timeout(
936 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
937 if (wait_status <= 0) {
938 dmaengine_terminate_all(tspi->tx_dma_chan);
939 dev_err(tspi->dev, "TxDma Xfer failed\n");
945 if (tspi->cur_direction & DATA_DIR_RX) {
946 if (tspi->rx_status) {
947 dmaengine_terminate_all(tspi->rx_dma_chan);
950 wait_status = wait_for_completion_interruptible_timeout(
951 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
952 if (wait_status <= 0) {
953 dmaengine_terminate_all(tspi->rx_dma_chan);
954 dev_err(tspi->dev, "RxDma Xfer failed\n");
960 spin_lock_irqsave(&tspi->lock, flags);
963 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
965 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
966 tspi->command2_reg, tspi->dma_control_reg);
967 tegra_periph_reset_assert(tspi->clk);
969 tegra_periph_reset_deassert(tspi->clk);
970 complete(&tspi->xfer_completion);
971 spin_unlock_irqrestore(&tspi->lock, flags);
975 if (tspi->cur_direction & DATA_DIR_RX)
976 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
978 if (tspi->cur_direction & DATA_DIR_TX)
979 tspi->cur_pos = tspi->cur_tx_pos;
981 tspi->cur_pos = tspi->cur_rx_pos;
983 if (tspi->cur_pos == t->len) {
984 complete(&tspi->xfer_completion);
988 /* Continue transfer in current message */
989 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
991 if (total_fifo_words > SLINK_FIFO_DEPTH)
992 err = tegra_slink_start_dma_based_transfer(tspi, t);
994 err = tegra_slink_start_cpu_based_transfer(tspi, t);
997 spin_unlock_irqrestore(&tspi->lock, flags);
1001 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
1003 struct tegra_slink_data *tspi = context_data;
1005 if (!tspi->is_curr_dma_xfer)
1006 return handle_cpu_based_xfer(tspi);
1007 return handle_dma_based_xfer(tspi);
1010 static irqreturn_t tegra_slink_isr(int irq, void *context_data)
1012 struct tegra_slink_data *tspi = context_data;
1014 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
1015 if (tspi->cur_direction & DATA_DIR_TX)
1016 tspi->tx_status = tspi->status_reg &
1017 (SLINK_TX_OVF | SLINK_TX_UNF);
1019 if (tspi->cur_direction & DATA_DIR_RX)
1020 tspi->rx_status = tspi->status_reg &
1021 (SLINK_RX_OVF | SLINK_RX_UNF);
1022 tegra_slink_clear_status(tspi);
1024 return IRQ_WAKE_THREAD;
1027 static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
1029 struct device_node *np = tspi->dev->of_node;
1032 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1034 tspi->dma_req_sel = of_dma[1];
1036 if (of_property_read_u32(np, "spi-max-frequency",
1037 &tspi->spi_max_frequency))
1038 tspi->spi_max_frequency = 25000000; /* 25MHz */
1041 static const struct tegra_slink_chip_data tegra30_spi_cdata = {
1042 .cs_hold_time = true,
1045 static const struct tegra_slink_chip_data tegra20_spi_cdata = {
1046 .cs_hold_time = false,
1049 static struct of_device_id tegra_slink_of_match[] = {
1050 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
1051 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
1054 MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1056 static int tegra_slink_probe(struct platform_device *pdev)
1058 struct spi_master *master;
1059 struct tegra_slink_data *tspi;
1062 const struct tegra_slink_chip_data *cdata = NULL;
1063 const struct of_device_id *match;
1065 match = of_match_device(tegra_slink_of_match, &pdev->dev);
1067 dev_err(&pdev->dev, "Error: No device match found\n");
1070 cdata = match->data;
1072 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1074 dev_err(&pdev->dev, "master allocation failed\n");
1078 /* the spi->mode bits understood by this driver: */
1079 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1080 master->setup = tegra_slink_setup;
1081 master->transfer_one_message = tegra_slink_transfer_one_message;
1082 master->auto_runtime_pm = true;
1083 master->num_chipselect = MAX_CHIP_SELECT;
1084 master->bus_num = -1;
1086 platform_set_drvdata(pdev, master);
1087 tspi = spi_master_get_devdata(master);
1088 tspi->master = master;
1089 tspi->dev = &pdev->dev;
1090 tspi->chip_data = cdata;
1091 spin_lock_init(&tspi->lock);
1093 tegra_slink_parse_dt(tspi);
1095 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1097 dev_err(&pdev->dev, "No IO memory resource\n");
1099 goto exit_free_master;
1101 tspi->phys = r->start;
1102 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1103 if (IS_ERR(tspi->base)) {
1104 ret = PTR_ERR(tspi->base);
1105 goto exit_free_master;
1108 spi_irq = platform_get_irq(pdev, 0);
1109 tspi->irq = spi_irq;
1110 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1111 tegra_slink_isr_thread, IRQF_ONESHOT,
1112 dev_name(&pdev->dev), tspi);
1114 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1116 goto exit_free_master;
1119 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1120 if (IS_ERR(tspi->clk)) {
1121 dev_err(&pdev->dev, "can not get clock\n");
1122 ret = PTR_ERR(tspi->clk);
1126 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1127 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1129 if (tspi->dma_req_sel) {
1130 ret = tegra_slink_init_dma_param(tspi, true);
1132 dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
1136 ret = tegra_slink_init_dma_param(tspi, false);
1138 dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1139 goto exit_rx_dma_free;
1141 tspi->max_buf_size = tspi->dma_buf_size;
1142 init_completion(&tspi->tx_dma_complete);
1143 init_completion(&tspi->rx_dma_complete);
1146 init_completion(&tspi->xfer_completion);
1148 pm_runtime_enable(&pdev->dev);
1149 if (!pm_runtime_enabled(&pdev->dev)) {
1150 ret = tegra_slink_runtime_resume(&pdev->dev);
1152 goto exit_pm_disable;
1155 ret = pm_runtime_get_sync(&pdev->dev);
1157 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1158 goto exit_pm_disable;
1160 tspi->def_command_reg = SLINK_M_S;
1161 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1162 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1163 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1164 pm_runtime_put(&pdev->dev);
1166 master->dev.of_node = pdev->dev.of_node;
1167 ret = spi_register_master(master);
1169 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1170 goto exit_pm_disable;
1175 pm_runtime_disable(&pdev->dev);
1176 if (!pm_runtime_status_suspended(&pdev->dev))
1177 tegra_slink_runtime_suspend(&pdev->dev);
1178 tegra_slink_deinit_dma_param(tspi, false);
1180 tegra_slink_deinit_dma_param(tspi, true);
1182 free_irq(spi_irq, tspi);
1184 spi_master_put(master);
1188 static int tegra_slink_remove(struct platform_device *pdev)
1190 struct spi_master *master = platform_get_drvdata(pdev);
1191 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1193 free_irq(tspi->irq, tspi);
1194 spi_unregister_master(master);
1196 if (tspi->tx_dma_chan)
1197 tegra_slink_deinit_dma_param(tspi, false);
1199 if (tspi->rx_dma_chan)
1200 tegra_slink_deinit_dma_param(tspi, true);
1202 pm_runtime_disable(&pdev->dev);
1203 if (!pm_runtime_status_suspended(&pdev->dev))
1204 tegra_slink_runtime_suspend(&pdev->dev);
1209 #ifdef CONFIG_PM_SLEEP
1210 static int tegra_slink_suspend(struct device *dev)
1212 struct spi_master *master = dev_get_drvdata(dev);
1214 return spi_master_suspend(master);
1217 static int tegra_slink_resume(struct device *dev)
1219 struct spi_master *master = dev_get_drvdata(dev);
1220 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1223 ret = pm_runtime_get_sync(dev);
1225 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1228 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1229 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1230 pm_runtime_put(dev);
1232 return spi_master_resume(master);
1236 static int tegra_slink_runtime_suspend(struct device *dev)
1238 struct spi_master *master = dev_get_drvdata(dev);
1239 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1241 /* Flush all write which are in PPSB queue by reading back */
1242 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1244 clk_disable_unprepare(tspi->clk);
1248 static int tegra_slink_runtime_resume(struct device *dev)
1250 struct spi_master *master = dev_get_drvdata(dev);
1251 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1254 ret = clk_prepare_enable(tspi->clk);
1256 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1262 static const struct dev_pm_ops slink_pm_ops = {
1263 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1264 tegra_slink_runtime_resume, NULL)
1265 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1267 static struct platform_driver tegra_slink_driver = {
1269 .name = "spi-tegra-slink",
1270 .owner = THIS_MODULE,
1271 .pm = &slink_pm_ops,
1272 .of_match_table = tegra_slink_of_match,
1274 .probe = tegra_slink_probe,
1275 .remove = tegra_slink_remove,
1277 module_platform_driver(tegra_slink_driver);
1279 MODULE_ALIAS("platform:spi-tegra-slink");
1280 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1281 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1282 MODULE_LICENSE("GPL v2");