4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
35 #include <linux/spi/spi.h>
42 struct completion transfer_complete;
44 /* list synchronization */
45 struct mutex list_lock;
47 struct spi_master *master;
49 void __iomem *ctrl_base;
50 void __iomem *mmap_base;
54 struct ti_qspi_regs ctx_reg;
56 u32 spi_max_frequency;
63 #define QSPI_PID (0x0)
64 #define QSPI_SYSCONFIG (0x10)
65 #define QSPI_INTR_STATUS_RAW_SET (0x20)
66 #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
67 #define QSPI_INTR_ENABLE_SET_REG (0x28)
68 #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
69 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
70 #define QSPI_SPI_DC_REG (0x44)
71 #define QSPI_SPI_CMD_REG (0x48)
72 #define QSPI_SPI_STATUS_REG (0x4c)
73 #define QSPI_SPI_DATA_REG (0x50)
74 #define QSPI_SPI_SETUP0_REG (0x54)
75 #define QSPI_SPI_SWITCH_REG (0x64)
76 #define QSPI_SPI_SETUP1_REG (0x58)
77 #define QSPI_SPI_SETUP2_REG (0x5c)
78 #define QSPI_SPI_SETUP3_REG (0x60)
79 #define QSPI_SPI_DATA_REG_1 (0x68)
80 #define QSPI_SPI_DATA_REG_2 (0x6c)
81 #define QSPI_SPI_DATA_REG_3 (0x70)
83 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
85 #define QSPI_FCLK 192000000
88 #define QSPI_CLK_EN (1 << 31)
89 #define QSPI_CLK_DIV_MAX 0xffff
92 #define QSPI_EN_CS(n) (n << 28)
93 #define QSPI_WLEN(n) ((n - 1) << 19)
94 #define QSPI_3_PIN (1 << 18)
95 #define QSPI_RD_SNGL (1 << 16)
96 #define QSPI_WR_SNGL (2 << 16)
97 #define QSPI_RD_DUAL (3 << 16)
98 #define QSPI_RD_QUAD (7 << 16)
99 #define QSPI_INVAL (4 << 16)
100 #define QSPI_WC_CMD_INT_EN (1 << 14)
101 #define QSPI_FLEN(n) ((n - 1) << 0)
103 /* STATUS REGISTER */
106 /* INTERRUPT REGISTER */
107 #define QSPI_WC_INT_EN (1 << 1)
108 #define QSPI_WC_INT_DISABLE (1 << 1)
111 #define QSPI_DD(m, n) (m << (3 + n * 8))
112 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
113 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
114 #define QSPI_CKPOL(n) (1 << (n * 8))
116 #define QSPI_FRAME 4096
118 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
120 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
123 return readl(qspi->base + reg);
126 static inline void ti_qspi_write(struct ti_qspi *qspi,
127 unsigned long val, unsigned long reg)
129 writel(val, qspi->base + reg);
132 static int ti_qspi_setup(struct spi_device *spi)
134 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
135 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
136 int clk_div = 0, ret;
137 u32 clk_ctrl_reg, clk_rate, clk_mask;
139 if (spi->master->busy) {
140 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
144 if (!qspi->spi_max_frequency) {
145 dev_err(qspi->dev, "spi max frequency not defined\n");
149 clk_rate = clk_get_rate(qspi->fclk);
151 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
154 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
158 if (clk_div > QSPI_CLK_DIV_MAX) {
159 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
160 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
164 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
165 qspi->spi_max_frequency, clk_div);
167 ret = pm_runtime_get_sync(qspi->dev);
169 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
173 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
175 clk_ctrl_reg &= ~QSPI_CLK_EN;
178 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
181 clk_mask = QSPI_CLK_EN | clk_div;
182 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
183 ctx_reg->clkctrl = clk_mask;
185 pm_runtime_mark_last_busy(qspi->dev);
186 ret = pm_runtime_put_autosuspend(qspi->dev);
188 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
195 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
197 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
199 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
202 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
204 int wlen, count, ret;
209 cmd = qspi->cmd | QSPI_WR_SNGL;
211 wlen = t->bits_per_word >> 3; /* in bytes */
216 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
217 cmd, qspi->dc, *txbuf);
218 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
221 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
222 cmd, qspi->dc, *txbuf);
223 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
226 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
227 cmd, qspi->dc, *txbuf);
228 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
232 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
233 ret = wait_for_completion_timeout(&qspi->transfer_complete,
234 QSPI_COMPLETION_TIMEOUT);
236 dev_err(qspi->dev, "write timed out\n");
246 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
248 int wlen, count, ret;
254 switch (t->rx_nbits) {
266 wlen = t->bits_per_word >> 3; /* in bytes */
269 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
270 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
271 ret = wait_for_completion_timeout(&qspi->transfer_complete,
272 QSPI_COMPLETION_TIMEOUT);
274 dev_err(qspi->dev, "read timed out\n");
279 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
282 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
285 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
295 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
300 ret = qspi_write_msg(qspi, t);
302 dev_dbg(qspi->dev, "Error while writing\n");
308 ret = qspi_read_msg(qspi, t);
310 dev_dbg(qspi->dev, "Error while reading\n");
318 static int ti_qspi_start_transfer_one(struct spi_master *master,
319 struct spi_message *m)
321 struct ti_qspi *qspi = spi_master_get_devdata(master);
322 struct spi_device *spi = m->spi;
323 struct spi_transfer *t;
327 /* setup device control reg */
330 if (spi->mode & SPI_CPHA)
331 qspi->dc |= QSPI_CKPHA(spi->chip_select);
332 if (spi->mode & SPI_CPOL)
333 qspi->dc |= QSPI_CKPOL(spi->chip_select);
334 if (spi->mode & SPI_CS_HIGH)
335 qspi->dc |= QSPI_CSPOL(spi->chip_select);
337 frame_length = (m->frame_length << 3) / spi->bits_per_word;
339 frame_length = clamp(frame_length, 0, QSPI_FRAME);
341 /* setup command reg */
343 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
344 qspi->cmd |= QSPI_FLEN(frame_length);
345 qspi->cmd |= QSPI_WC_CMD_INT_EN;
347 ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
348 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
350 mutex_lock(&qspi->list_lock);
352 list_for_each_entry(t, &m->transfers, transfer_list) {
353 qspi->cmd |= QSPI_WLEN(t->bits_per_word);
355 ret = qspi_transfer_msg(qspi, t);
357 dev_dbg(qspi->dev, "transfer message failed\n");
358 mutex_unlock(&qspi->list_lock);
362 m->actual_length += t->len;
365 mutex_unlock(&qspi->list_lock);
368 spi_finalize_current_message(master);
370 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
375 static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
377 struct ti_qspi *qspi = dev_id;
381 irqreturn_t ret = IRQ_HANDLED;
383 int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
384 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
387 dev_dbg(qspi->dev, "No IRQ triggered\n");
392 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
393 QSPI_INTR_STATUS_ENABLED_CLEAR);
395 complete(&qspi->transfer_complete);
400 static int ti_qspi_runtime_resume(struct device *dev)
402 struct ti_qspi *qspi;
404 qspi = dev_get_drvdata(dev);
405 ti_qspi_restore_ctx(qspi);
410 static const struct of_device_id ti_qspi_match[] = {
411 {.compatible = "ti,dra7xxx-qspi" },
412 {.compatible = "ti,am4372-qspi" },
415 MODULE_DEVICE_TABLE(of, ti_qspi_match);
417 static int ti_qspi_probe(struct platform_device *pdev)
419 struct ti_qspi *qspi;
420 struct spi_master *master;
421 struct resource *r, *res_ctrl, *res_mmap;
422 struct device_node *np = pdev->dev.of_node;
424 int ret = 0, num_cs, irq;
426 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
430 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
432 master->flags = SPI_MASTER_HALF_DUPLEX;
433 master->setup = ti_qspi_setup;
434 master->auto_runtime_pm = true;
435 master->transfer_one_message = ti_qspi_start_transfer_one;
436 master->dev.of_node = pdev->dev.of_node;
437 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
440 if (!of_property_read_u32(np, "num-cs", &num_cs))
441 master->num_chipselect = num_cs;
443 qspi = spi_master_get_devdata(master);
444 qspi->master = master;
445 qspi->dev = &pdev->dev;
446 platform_set_drvdata(pdev, qspi);
448 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
450 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
452 dev_err(&pdev->dev, "missing platform data\n");
457 res_mmap = platform_get_resource_byname(pdev,
458 IORESOURCE_MEM, "qspi_mmap");
459 if (res_mmap == NULL) {
460 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
461 if (res_mmap == NULL) {
463 "memory mapped resource not required\n");
467 res_ctrl = platform_get_resource_byname(pdev,
468 IORESOURCE_MEM, "qspi_ctrlmod");
469 if (res_ctrl == NULL) {
470 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
471 if (res_ctrl == NULL) {
473 "control module resources not required\n");
477 irq = platform_get_irq(pdev, 0);
479 dev_err(&pdev->dev, "no irq resource?\n");
483 mutex_init(&qspi->list_lock);
485 qspi->base = devm_ioremap_resource(&pdev->dev, r);
486 if (IS_ERR(qspi->base)) {
487 ret = PTR_ERR(qspi->base);
492 qspi->ctrl_mod = true;
493 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
494 if (IS_ERR(qspi->ctrl_base)) {
495 ret = PTR_ERR(qspi->ctrl_base);
501 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
502 if (IS_ERR(qspi->mmap_base)) {
503 ret = PTR_ERR(qspi->mmap_base);
508 ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
509 dev_name(&pdev->dev), qspi);
511 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
516 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
517 if (IS_ERR(qspi->fclk)) {
518 ret = PTR_ERR(qspi->fclk);
519 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
522 init_completion(&qspi->transfer_complete);
524 pm_runtime_use_autosuspend(&pdev->dev);
525 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
526 pm_runtime_enable(&pdev->dev);
528 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
529 qspi->spi_max_frequency = max_freq;
531 ret = devm_spi_register_master(&pdev->dev, master);
538 spi_master_put(master);
542 static int ti_qspi_remove(struct platform_device *pdev)
544 struct ti_qspi *qspi = platform_get_drvdata(pdev);
547 ret = pm_runtime_get_sync(qspi->dev);
549 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
553 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
555 pm_runtime_put(qspi->dev);
556 pm_runtime_disable(&pdev->dev);
561 static const struct dev_pm_ops ti_qspi_pm_ops = {
562 .runtime_resume = ti_qspi_runtime_resume,
565 static struct platform_driver ti_qspi_driver = {
566 .probe = ti_qspi_probe,
567 .remove = ti_qspi_remove,
570 .owner = THIS_MODULE,
571 .pm = &ti_qspi_pm_ops,
572 .of_match_table = ti_qspi_match,
576 module_platform_driver(ti_qspi_driver);
578 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
579 MODULE_LICENSE("GPL v2");
580 MODULE_DESCRIPTION("TI QSPI controller driver");
581 MODULE_ALIAS("platform:ti-qspi");