4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
35 #include <linux/spi/spi.h>
42 /* list synchronization */
43 struct mutex list_lock;
45 struct spi_master *master;
47 void __iomem *ctrl_base;
48 void __iomem *mmap_base;
52 struct ti_qspi_regs ctx_reg;
54 u32 spi_max_frequency;
61 #define QSPI_PID (0x0)
62 #define QSPI_SYSCONFIG (0x10)
63 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
64 #define QSPI_SPI_DC_REG (0x44)
65 #define QSPI_SPI_CMD_REG (0x48)
66 #define QSPI_SPI_STATUS_REG (0x4c)
67 #define QSPI_SPI_DATA_REG (0x50)
68 #define QSPI_SPI_SETUP0_REG (0x54)
69 #define QSPI_SPI_SWITCH_REG (0x64)
70 #define QSPI_SPI_SETUP1_REG (0x58)
71 #define QSPI_SPI_SETUP2_REG (0x5c)
72 #define QSPI_SPI_SETUP3_REG (0x60)
73 #define QSPI_SPI_DATA_REG_1 (0x68)
74 #define QSPI_SPI_DATA_REG_2 (0x6c)
75 #define QSPI_SPI_DATA_REG_3 (0x70)
77 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
79 #define QSPI_FCLK 192000000
82 #define QSPI_CLK_EN (1 << 31)
83 #define QSPI_CLK_DIV_MAX 0xffff
86 #define QSPI_EN_CS(n) (n << 28)
87 #define QSPI_WLEN(n) ((n - 1) << 19)
88 #define QSPI_3_PIN (1 << 18)
89 #define QSPI_RD_SNGL (1 << 16)
90 #define QSPI_WR_SNGL (2 << 16)
91 #define QSPI_RD_DUAL (3 << 16)
92 #define QSPI_RD_QUAD (7 << 16)
93 #define QSPI_INVAL (4 << 16)
94 #define QSPI_FLEN(n) ((n - 1) << 0)
95 #define QSPI_WLEN_MAX_BITS 128
96 #define QSPI_WLEN_MAX_BYTES 16
97 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
104 #define QSPI_DD(m, n) (m << (3 + n * 8))
105 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
106 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
107 #define QSPI_CKPOL(n) (1 << (n * 8))
109 #define QSPI_FRAME 4096
111 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
113 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
116 return readl(qspi->base + reg);
119 static inline void ti_qspi_write(struct ti_qspi *qspi,
120 unsigned long val, unsigned long reg)
122 writel(val, qspi->base + reg);
125 static int ti_qspi_setup(struct spi_device *spi)
127 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
128 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
129 int clk_div = 0, ret;
130 u32 clk_ctrl_reg, clk_rate, clk_mask;
132 if (spi->master->busy) {
133 dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
137 if (!qspi->spi_max_frequency) {
138 dev_err(qspi->dev, "spi max frequency not defined\n");
142 clk_rate = clk_get_rate(qspi->fclk);
144 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
147 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
151 if (clk_div > QSPI_CLK_DIV_MAX) {
152 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
153 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
157 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
158 qspi->spi_max_frequency, clk_div);
160 ret = pm_runtime_get_sync(qspi->dev);
162 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
166 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
168 clk_ctrl_reg &= ~QSPI_CLK_EN;
171 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
174 clk_mask = QSPI_CLK_EN | clk_div;
175 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
176 ctx_reg->clkctrl = clk_mask;
178 pm_runtime_mark_last_busy(qspi->dev);
179 ret = pm_runtime_put_autosuspend(qspi->dev);
181 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
188 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
190 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
192 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
195 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
198 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
200 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
201 while ((stat & BUSY) && time_after(timeout, jiffies)) {
203 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
206 WARN(stat & BUSY, "qspi busy\n");
210 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
213 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
216 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
220 } while (time_after(timeout, jiffies));
222 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
228 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
230 int wlen, count, xfer_len;
236 cmd = qspi->cmd | QSPI_WR_SNGL;
238 wlen = t->bits_per_word >> 3; /* in bytes */
242 if (qspi_is_busy(qspi))
247 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
248 cmd, qspi->dc, *txbuf);
249 if (count >= QSPI_WLEN_MAX_BYTES) {
250 u32 *txp = (u32 *)txbuf;
252 data = cpu_to_be32(*txp++);
253 writel(data, qspi->base +
254 QSPI_SPI_DATA_REG_3);
255 data = cpu_to_be32(*txp++);
256 writel(data, qspi->base +
257 QSPI_SPI_DATA_REG_2);
258 data = cpu_to_be32(*txp++);
259 writel(data, qspi->base +
260 QSPI_SPI_DATA_REG_1);
261 data = cpu_to_be32(*txp++);
262 writel(data, qspi->base +
264 xfer_len = QSPI_WLEN_MAX_BYTES;
265 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
267 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
268 cmd = qspi->cmd | QSPI_WR_SNGL;
270 cmd |= QSPI_WLEN(wlen);
274 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
275 cmd, qspi->dc, *txbuf);
276 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
279 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
280 cmd, qspi->dc, *txbuf);
281 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
285 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
286 if (ti_qspi_poll_wc(qspi)) {
287 dev_err(qspi->dev, "write timed out\n");
297 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
305 switch (t->rx_nbits) {
317 wlen = t->bits_per_word >> 3; /* in bytes */
320 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
321 if (qspi_is_busy(qspi))
324 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
325 if (ti_qspi_poll_wc(qspi)) {
326 dev_err(qspi->dev, "read timed out\n");
331 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
334 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
337 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
347 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
352 ret = qspi_write_msg(qspi, t);
354 dev_dbg(qspi->dev, "Error while writing\n");
360 ret = qspi_read_msg(qspi, t);
362 dev_dbg(qspi->dev, "Error while reading\n");
370 static int ti_qspi_start_transfer_one(struct spi_master *master,
371 struct spi_message *m)
373 struct ti_qspi *qspi = spi_master_get_devdata(master);
374 struct spi_device *spi = m->spi;
375 struct spi_transfer *t;
377 unsigned int frame_len_words;
379 /* setup device control reg */
382 if (spi->mode & SPI_CPHA)
383 qspi->dc |= QSPI_CKPHA(spi->chip_select);
384 if (spi->mode & SPI_CPOL)
385 qspi->dc |= QSPI_CKPOL(spi->chip_select);
386 if (spi->mode & SPI_CS_HIGH)
387 qspi->dc |= QSPI_CSPOL(spi->chip_select);
390 list_for_each_entry(t, &m->transfers, transfer_list)
391 frame_len_words += t->len / (t->bits_per_word >> 3);
392 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
394 /* setup command reg */
396 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
397 qspi->cmd |= QSPI_FLEN(frame_len_words);
399 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
401 mutex_lock(&qspi->list_lock);
403 list_for_each_entry(t, &m->transfers, transfer_list) {
404 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
405 QSPI_WLEN(t->bits_per_word));
407 ret = qspi_transfer_msg(qspi, t);
409 dev_dbg(qspi->dev, "transfer message failed\n");
410 mutex_unlock(&qspi->list_lock);
414 m->actual_length += t->len;
417 mutex_unlock(&qspi->list_lock);
419 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
421 spi_finalize_current_message(master);
426 static int ti_qspi_runtime_resume(struct device *dev)
428 struct ti_qspi *qspi;
430 qspi = dev_get_drvdata(dev);
431 ti_qspi_restore_ctx(qspi);
436 static const struct of_device_id ti_qspi_match[] = {
437 {.compatible = "ti,dra7xxx-qspi" },
438 {.compatible = "ti,am4372-qspi" },
441 MODULE_DEVICE_TABLE(of, ti_qspi_match);
443 static int ti_qspi_probe(struct platform_device *pdev)
445 struct ti_qspi *qspi;
446 struct spi_master *master;
447 struct resource *r, *res_ctrl, *res_mmap;
448 struct device_node *np = pdev->dev.of_node;
450 int ret = 0, num_cs, irq;
452 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
456 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
458 master->flags = SPI_MASTER_HALF_DUPLEX;
459 master->setup = ti_qspi_setup;
460 master->auto_runtime_pm = true;
461 master->transfer_one_message = ti_qspi_start_transfer_one;
462 master->dev.of_node = pdev->dev.of_node;
463 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
466 if (!of_property_read_u32(np, "num-cs", &num_cs))
467 master->num_chipselect = num_cs;
469 qspi = spi_master_get_devdata(master);
470 qspi->master = master;
471 qspi->dev = &pdev->dev;
472 platform_set_drvdata(pdev, qspi);
474 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
476 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 dev_err(&pdev->dev, "missing platform data\n");
483 res_mmap = platform_get_resource_byname(pdev,
484 IORESOURCE_MEM, "qspi_mmap");
485 if (res_mmap == NULL) {
486 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
487 if (res_mmap == NULL) {
489 "memory mapped resource not required\n");
493 res_ctrl = platform_get_resource_byname(pdev,
494 IORESOURCE_MEM, "qspi_ctrlmod");
495 if (res_ctrl == NULL) {
496 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
497 if (res_ctrl == NULL) {
499 "control module resources not required\n");
503 irq = platform_get_irq(pdev, 0);
505 dev_err(&pdev->dev, "no irq resource?\n");
509 mutex_init(&qspi->list_lock);
511 qspi->base = devm_ioremap_resource(&pdev->dev, r);
512 if (IS_ERR(qspi->base)) {
513 ret = PTR_ERR(qspi->base);
518 qspi->ctrl_mod = true;
519 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
520 if (IS_ERR(qspi->ctrl_base)) {
521 ret = PTR_ERR(qspi->ctrl_base);
527 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
528 if (IS_ERR(qspi->mmap_base)) {
529 ret = PTR_ERR(qspi->mmap_base);
534 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
535 if (IS_ERR(qspi->fclk)) {
536 ret = PTR_ERR(qspi->fclk);
537 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
540 pm_runtime_use_autosuspend(&pdev->dev);
541 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
542 pm_runtime_enable(&pdev->dev);
544 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
545 qspi->spi_max_frequency = max_freq;
547 ret = devm_spi_register_master(&pdev->dev, master);
554 spi_master_put(master);
558 static int ti_qspi_remove(struct platform_device *pdev)
560 pm_runtime_put_sync(&pdev->dev);
561 pm_runtime_disable(&pdev->dev);
566 static const struct dev_pm_ops ti_qspi_pm_ops = {
567 .runtime_resume = ti_qspi_runtime_resume,
570 static struct platform_driver ti_qspi_driver = {
571 .probe = ti_qspi_probe,
572 .remove = ti_qspi_remove,
575 .pm = &ti_qspi_pm_ops,
576 .of_match_table = ti_qspi_match,
580 module_platform_driver(ti_qspi_driver);
582 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
583 MODULE_LICENSE("GPL v2");
584 MODULE_DESCRIPTION("TI QSPI controller driver");
585 MODULE_ALIAS("platform:ti-qspi");