2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
46 /* Driver model hookup */
47 struct platform_device *pdev;
49 /* SPI framework hookup */
50 struct spi_master *master;
52 /* Regs base of SPI controller */
53 void __iomem *regs_base;
55 /* Pin request list */
59 struct bfin5xx_spi_master *master_info;
61 /* Driver message queue */
62 struct workqueue_struct *workqueue;
63 struct work_struct pump_messages;
65 struct list_head queue;
69 /* Message Transfer pump */
70 struct tasklet_struct pump_transfers;
72 /* Current message transfer state info */
73 struct spi_message *cur_msg;
74 struct spi_transfer *cur_transfer;
75 struct chip_data *cur_chip;
97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
109 u8 width; /* 0 or 1 */
111 u8 bits_per_word; /* 8 or 16 */
112 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
115 u8 pio_interrupt; /* use spi data irq */
116 void (*write) (struct driver_data *);
117 void (*read) (struct driver_data *);
118 void (*duplex) (struct driver_data *);
121 #define DEFINE_SPI_REG(reg, off) \
122 static inline u16 read_##reg(struct driver_data *drv_data) \
123 { return bfin_read16(drv_data->regs_base + off); } \
124 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
125 { bfin_write16(drv_data->regs_base + off, v); }
127 DEFINE_SPI_REG(CTRL, 0x00)
128 DEFINE_SPI_REG(FLAG, 0x04)
129 DEFINE_SPI_REG(STAT, 0x08)
130 DEFINE_SPI_REG(TDBR, 0x0C)
131 DEFINE_SPI_REG(RDBR, 0x10)
132 DEFINE_SPI_REG(BAUD, 0x14)
133 DEFINE_SPI_REG(SHAW, 0x18)
135 static void bfin_spi_enable(struct driver_data *drv_data)
139 cr = read_CTRL(drv_data);
140 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
143 static void bfin_spi_disable(struct driver_data *drv_data)
147 cr = read_CTRL(drv_data);
148 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
151 /* Caculate the SPI_BAUD register value based on input HZ */
152 static u16 hz_to_spi_baud(u32 speed_hz)
154 u_long sclk = get_sclk();
155 u16 spi_baud = (sclk / (2 * speed_hz));
157 if ((sclk % (2 * speed_hz)) > 0)
160 if (spi_baud < MIN_SPI_BAUD_VAL)
161 spi_baud = MIN_SPI_BAUD_VAL;
166 static int bfin_spi_flush(struct driver_data *drv_data)
168 unsigned long limit = loops_per_jiffy << 1;
170 /* wait for stop and clear stat */
171 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
174 write_STAT(drv_data, BIT_STAT_CLR);
179 /* Chip select operation functions for cs_change flag */
180 static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
182 if (likely(chip->chip_select_num)) {
183 u16 flag = read_FLAG(drv_data);
187 write_FLAG(drv_data, flag);
189 gpio_set_value(chip->cs_gpio, 0);
193 static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
195 if (likely(chip->chip_select_num)) {
196 u16 flag = read_FLAG(drv_data);
200 write_FLAG(drv_data, flag);
202 gpio_set_value(chip->cs_gpio, 1);
205 /* Move delay here for consistency */
206 if (chip->cs_chg_udelay)
207 udelay(chip->cs_chg_udelay);
210 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
211 static inline void bfin_spi_cs_enable(struct driver_data *drv_data, struct chip_data *chip)
213 u16 flag = read_FLAG(drv_data);
215 flag |= (chip->flag >> 8);
217 write_FLAG(drv_data, flag);
220 static inline void bfin_spi_cs_disable(struct driver_data *drv_data, struct chip_data *chip)
222 u16 flag = read_FLAG(drv_data);
224 flag &= ~(chip->flag >> 8);
226 write_FLAG(drv_data, flag);
229 /* stop controller and re-config current chip*/
230 static void bfin_spi_restore_state(struct driver_data *drv_data)
232 struct chip_data *chip = drv_data->cur_chip;
234 /* Clear status and disable clock */
235 write_STAT(drv_data, BIT_STAT_CLR);
236 bfin_spi_disable(drv_data);
237 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
239 /* Load the registers */
240 write_CTRL(drv_data, chip->ctl_reg);
241 write_BAUD(drv_data, chip->baud);
243 bfin_spi_enable(drv_data);
244 bfin_spi_cs_active(drv_data, chip);
247 /* used to kick off transfer in rx mode and read unwanted RX data */
248 static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
250 (void) read_RDBR(drv_data);
253 static void bfin_spi_u8_writer(struct driver_data *drv_data)
255 /* clear RXS (we check for RXS inside the loop) */
256 bfin_spi_dummy_read(drv_data);
258 while (drv_data->tx < drv_data->tx_end) {
259 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
260 /* wait until transfer finished.
261 checking SPIF or TXS may not guarantee transfer completion */
262 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
264 /* discard RX data and clear RXS */
265 bfin_spi_dummy_read(drv_data);
269 static void bfin_spi_u8_reader(struct driver_data *drv_data)
271 u16 tx_val = drv_data->cur_chip->idle_tx_val;
273 /* discard old RX data and clear RXS */
274 bfin_spi_dummy_read(drv_data);
276 while (drv_data->rx < drv_data->rx_end) {
277 write_TDBR(drv_data, tx_val);
278 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
280 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
284 static void bfin_spi_u8_duplex(struct driver_data *drv_data)
286 /* discard old RX data and clear RXS */
287 bfin_spi_dummy_read(drv_data);
289 while (drv_data->rx < drv_data->rx_end) {
290 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
291 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
293 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
297 static void bfin_spi_u16_writer(struct driver_data *drv_data)
299 /* clear RXS (we check for RXS inside the loop) */
300 bfin_spi_dummy_read(drv_data);
302 while (drv_data->tx < drv_data->tx_end) {
303 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
305 /* wait until transfer finished.
306 checking SPIF or TXS may not guarantee transfer completion */
307 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
309 /* discard RX data and clear RXS */
310 bfin_spi_dummy_read(drv_data);
314 static void bfin_spi_u16_reader(struct driver_data *drv_data)
316 u16 tx_val = drv_data->cur_chip->idle_tx_val;
318 /* discard old RX data and clear RXS */
319 bfin_spi_dummy_read(drv_data);
321 while (drv_data->rx < drv_data->rx_end) {
322 write_TDBR(drv_data, tx_val);
323 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
325 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
330 static void bfin_spi_u16_duplex(struct driver_data *drv_data)
332 /* discard old RX data and clear RXS */
333 bfin_spi_dummy_read(drv_data);
335 while (drv_data->rx < drv_data->rx_end) {
336 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
338 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
340 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
345 /* test if ther is more transfer to be done */
346 static void *bfin_spi_next_transfer(struct driver_data *drv_data)
348 struct spi_message *msg = drv_data->cur_msg;
349 struct spi_transfer *trans = drv_data->cur_transfer;
351 /* Move to next transfer */
352 if (trans->transfer_list.next != &msg->transfers) {
353 drv_data->cur_transfer =
354 list_entry(trans->transfer_list.next,
355 struct spi_transfer, transfer_list);
356 return RUNNING_STATE;
362 * caller already set message->status;
363 * dma and pio irqs are blocked give finished message back
365 static void bfin_spi_giveback(struct driver_data *drv_data)
367 struct chip_data *chip = drv_data->cur_chip;
368 struct spi_transfer *last_transfer;
370 struct spi_message *msg;
372 spin_lock_irqsave(&drv_data->lock, flags);
373 msg = drv_data->cur_msg;
374 drv_data->cur_msg = NULL;
375 drv_data->cur_transfer = NULL;
376 drv_data->cur_chip = NULL;
377 queue_work(drv_data->workqueue, &drv_data->pump_messages);
378 spin_unlock_irqrestore(&drv_data->lock, flags);
380 last_transfer = list_entry(msg->transfers.prev,
381 struct spi_transfer, transfer_list);
385 if (!drv_data->cs_change)
386 bfin_spi_cs_deactive(drv_data, chip);
388 /* Not stop spi in autobuffer mode */
389 if (drv_data->tx_dma != 0xFFFF)
390 bfin_spi_disable(drv_data);
393 msg->complete(msg->context);
396 /* spi data irq handler */
397 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
399 struct driver_data *drv_data = dev_id;
400 struct chip_data *chip = drv_data->cur_chip;
401 struct spi_message *msg = drv_data->cur_msg;
402 int n_bytes = drv_data->n_bytes;
404 /* wait until transfer finished. */
405 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
408 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
409 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
412 dev_dbg(&drv_data->pdev->dev, "last read\n");
414 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
415 else if (n_bytes == 1)
416 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
417 drv_data->rx += n_bytes;
420 msg->actual_length += drv_data->len_in_bytes;
421 if (drv_data->cs_change)
422 bfin_spi_cs_deactive(drv_data, chip);
423 /* Move to next transfer */
424 msg->state = bfin_spi_next_transfer(drv_data);
426 disable_irq(drv_data->spi_irq);
428 /* Schedule transfer tasklet */
429 tasklet_schedule(&drv_data->pump_transfers);
433 if (drv_data->rx && drv_data->tx) {
435 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
436 if (drv_data->n_bytes == 2) {
437 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
438 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
439 } else if (drv_data->n_bytes == 1) {
440 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
441 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
443 } else if (drv_data->rx) {
445 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
446 if (drv_data->n_bytes == 2)
447 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
448 else if (drv_data->n_bytes == 1)
449 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
450 write_TDBR(drv_data, chip->idle_tx_val);
451 } else if (drv_data->tx) {
453 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
454 bfin_spi_dummy_read(drv_data);
455 if (drv_data->n_bytes == 2)
456 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
457 else if (drv_data->n_bytes == 1)
458 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
462 drv_data->tx += n_bytes;
464 drv_data->rx += n_bytes;
469 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
471 struct driver_data *drv_data = dev_id;
472 struct chip_data *chip = drv_data->cur_chip;
473 struct spi_message *msg = drv_data->cur_msg;
474 unsigned long timeout;
475 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
476 u16 spistat = read_STAT(drv_data);
478 dev_dbg(&drv_data->pdev->dev,
479 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
482 clear_dma_irqstat(drv_data->dma_channel);
485 * wait for the last transaction shifted out. HRM states:
486 * at this point there may still be data in the SPI DMA FIFO waiting
487 * to be transmitted ... software needs to poll TXS in the SPI_STAT
488 * register until it goes low for 2 successive reads
490 if (drv_data->tx != NULL) {
491 while ((read_STAT(drv_data) & TXS) ||
492 (read_STAT(drv_data) & TXS))
496 dev_dbg(&drv_data->pdev->dev,
497 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
498 dmastat, read_STAT(drv_data));
500 timeout = jiffies + HZ;
501 while (!(read_STAT(drv_data) & SPIF))
502 if (!time_before(jiffies, timeout)) {
503 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
508 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
509 msg->state = ERROR_STATE;
510 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
512 msg->actual_length += drv_data->len_in_bytes;
514 if (drv_data->cs_change)
515 bfin_spi_cs_deactive(drv_data, chip);
517 /* Move to next transfer */
518 msg->state = bfin_spi_next_transfer(drv_data);
521 /* Schedule transfer tasklet */
522 tasklet_schedule(&drv_data->pump_transfers);
524 /* free the irq handler before next transfer */
525 dev_dbg(&drv_data->pdev->dev,
526 "disable dma channel irq%d\n",
527 drv_data->dma_channel);
528 dma_disable_irq(drv_data->dma_channel);
533 static void bfin_spi_pump_transfers(unsigned long data)
535 struct driver_data *drv_data = (struct driver_data *)data;
536 struct spi_message *message = NULL;
537 struct spi_transfer *transfer = NULL;
538 struct spi_transfer *previous = NULL;
539 struct chip_data *chip = NULL;
541 u16 cr, dma_width, dma_config;
542 u32 tranf_success = 1;
545 /* Get current state information */
546 message = drv_data->cur_msg;
547 transfer = drv_data->cur_transfer;
548 chip = drv_data->cur_chip;
551 * if msg is error or done, report it back using complete() callback
554 /* Handle for abort */
555 if (message->state == ERROR_STATE) {
556 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
557 message->status = -EIO;
558 bfin_spi_giveback(drv_data);
562 /* Handle end of message */
563 if (message->state == DONE_STATE) {
564 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
566 bfin_spi_giveback(drv_data);
570 /* Delay if requested at end of transfer */
571 if (message->state == RUNNING_STATE) {
572 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
573 previous = list_entry(transfer->transfer_list.prev,
574 struct spi_transfer, transfer_list);
575 if (previous->delay_usecs)
576 udelay(previous->delay_usecs);
579 /* Flush any existing transfers that may be sitting in the hardware */
580 if (bfin_spi_flush(drv_data) == 0) {
581 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
582 message->status = -EIO;
583 bfin_spi_giveback(drv_data);
587 if (transfer->len == 0) {
588 /* Move to next transfer of this msg */
589 message->state = bfin_spi_next_transfer(drv_data);
590 /* Schedule next transfer tasklet */
591 tasklet_schedule(&drv_data->pump_transfers);
594 if (transfer->tx_buf != NULL) {
595 drv_data->tx = (void *)transfer->tx_buf;
596 drv_data->tx_end = drv_data->tx + transfer->len;
597 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
598 transfer->tx_buf, drv_data->tx_end);
603 if (transfer->rx_buf != NULL) {
604 full_duplex = transfer->tx_buf != NULL;
605 drv_data->rx = transfer->rx_buf;
606 drv_data->rx_end = drv_data->rx + transfer->len;
607 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
608 transfer->rx_buf, drv_data->rx_end);
613 drv_data->rx_dma = transfer->rx_dma;
614 drv_data->tx_dma = transfer->tx_dma;
615 drv_data->len_in_bytes = transfer->len;
616 drv_data->cs_change = transfer->cs_change;
618 /* Bits per word setup */
619 switch (transfer->bits_per_word) {
621 drv_data->n_bytes = 1;
622 width = CFG_SPI_WORDSIZE8;
623 drv_data->read = bfin_spi_u8_reader;
624 drv_data->write = bfin_spi_u8_writer;
625 drv_data->duplex = bfin_spi_u8_duplex;
629 drv_data->n_bytes = 2;
630 width = CFG_SPI_WORDSIZE16;
631 drv_data->read = bfin_spi_u16_reader;
632 drv_data->write = bfin_spi_u16_writer;
633 drv_data->duplex = bfin_spi_u16_duplex;
637 /* No change, the same as default setting */
638 transfer->bits_per_word = chip->bits_per_word;
639 drv_data->n_bytes = chip->n_bytes;
641 drv_data->write = chip->write;
642 drv_data->read = chip->read;
643 drv_data->duplex = chip->duplex;
646 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
648 write_CTRL(drv_data, cr);
650 if (width == CFG_SPI_WORDSIZE16) {
651 drv_data->len = (transfer->len) >> 1;
653 drv_data->len = transfer->len;
655 dev_dbg(&drv_data->pdev->dev,
656 "transfer: drv_data->write is %p, chip->write is %p\n",
657 drv_data->write, chip->write);
659 message->state = RUNNING_STATE;
662 /* Speed setup (surely valid because already checked) */
663 if (transfer->speed_hz)
664 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
666 write_BAUD(drv_data, chip->baud);
668 write_STAT(drv_data, BIT_STAT_CLR);
669 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
670 if (drv_data->cs_change)
671 bfin_spi_cs_active(drv_data, chip);
673 dev_dbg(&drv_data->pdev->dev,
674 "now pumping a transfer: width is %d, len is %d\n",
675 width, transfer->len);
678 * Try to map dma buffer and do a dma transfer. If successful use,
679 * different way to r/w according to the enable_dma settings and if
680 * we are not doing a full duplex transfer (since the hardware does
681 * not support full duplex DMA transfers).
683 if (!full_duplex && drv_data->cur_chip->enable_dma
684 && drv_data->len > 6) {
686 unsigned long dma_start_addr, flags;
688 disable_dma(drv_data->dma_channel);
689 clear_dma_irqstat(drv_data->dma_channel);
691 /* config dma channel */
692 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
693 set_dma_x_count(drv_data->dma_channel, drv_data->len);
694 if (width == CFG_SPI_WORDSIZE16) {
695 set_dma_x_modify(drv_data->dma_channel, 2);
696 dma_width = WDSIZE_16;
698 set_dma_x_modify(drv_data->dma_channel, 1);
699 dma_width = WDSIZE_8;
702 /* poll for SPI completion before start */
703 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
706 /* dirty hack for autobuffer DMA mode */
707 if (drv_data->tx_dma == 0xFFFF) {
708 dev_dbg(&drv_data->pdev->dev,
709 "doing autobuffer DMA out.\n");
711 /* no irq in autobuffer mode */
713 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
714 set_dma_config(drv_data->dma_channel, dma_config);
715 set_dma_start_addr(drv_data->dma_channel,
716 (unsigned long)drv_data->tx);
717 enable_dma(drv_data->dma_channel);
719 /* start SPI transfer */
720 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
722 /* just return here, there can only be one transfer
726 bfin_spi_giveback(drv_data);
730 /* In dma mode, rx or tx must be NULL in one transfer */
731 dma_config = (RESTART | dma_width | DI_EN);
732 if (drv_data->rx != NULL) {
733 /* set transfer mode, and enable SPI */
734 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
735 drv_data->rx, drv_data->len_in_bytes);
737 /* invalidate caches, if needed */
738 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
739 invalidate_dcache_range((unsigned long) drv_data->rx,
740 (unsigned long) (drv_data->rx +
741 drv_data->len_in_bytes));
744 dma_start_addr = (unsigned long)drv_data->rx;
745 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
747 } else if (drv_data->tx != NULL) {
748 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
750 /* flush caches, if needed */
751 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
752 flush_dcache_range((unsigned long) drv_data->tx,
753 (unsigned long) (drv_data->tx +
754 drv_data->len_in_bytes));
756 dma_start_addr = (unsigned long)drv_data->tx;
757 cr |= BIT_CTL_TIMOD_DMA_TX;
762 /* oh man, here there be monsters ... and i dont mean the
763 * fluffy cute ones from pixar, i mean the kind that'll eat
764 * your data, kick your dog, and love it all. do *not* try
765 * and change these lines unless you (1) heavily test DMA
766 * with SPI flashes on a loaded system (e.g. ping floods),
767 * (2) know just how broken the DMA engine interaction with
768 * the SPI peripheral is, and (3) have someone else to blame
769 * when you screw it all up anyways.
771 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
772 set_dma_config(drv_data->dma_channel, dma_config);
773 local_irq_save(flags);
775 write_CTRL(drv_data, cr);
776 enable_dma(drv_data->dma_channel);
777 dma_enable_irq(drv_data->dma_channel);
778 local_irq_restore(flags);
783 if (chip->pio_interrupt) {
784 /* use write mode. spi irq should have been disabled */
785 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
786 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
788 /* discard old RX data and clear RXS */
789 bfin_spi_dummy_read(drv_data);
792 if (drv_data->tx == NULL)
793 write_TDBR(drv_data, chip->idle_tx_val);
795 if (transfer->bits_per_word == 8)
796 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
797 else if (transfer->bits_per_word == 16)
798 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
799 drv_data->tx += drv_data->n_bytes;
802 /* once TDBR is empty, interrupt is triggered */
803 enable_irq(drv_data->spi_irq);
808 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
810 /* we always use SPI_WRITE mode. SPI_READ mode
811 seems to have problems with setting up the
812 output value in TDBR prior to the transfer. */
813 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
816 /* full duplex mode */
817 BUG_ON((drv_data->tx_end - drv_data->tx) !=
818 (drv_data->rx_end - drv_data->rx));
819 dev_dbg(&drv_data->pdev->dev,
820 "IO duplex: cr is 0x%x\n", cr);
822 drv_data->duplex(drv_data);
824 if (drv_data->tx != drv_data->tx_end)
826 } else if (drv_data->tx != NULL) {
827 /* write only half duplex */
828 dev_dbg(&drv_data->pdev->dev,
829 "IO write: cr is 0x%x\n", cr);
831 drv_data->write(drv_data);
833 if (drv_data->tx != drv_data->tx_end)
835 } else if (drv_data->rx != NULL) {
836 /* read only half duplex */
837 dev_dbg(&drv_data->pdev->dev,
838 "IO read: cr is 0x%x\n", cr);
840 drv_data->read(drv_data);
841 if (drv_data->rx != drv_data->rx_end)
845 if (!tranf_success) {
846 dev_dbg(&drv_data->pdev->dev,
847 "IO write error!\n");
848 message->state = ERROR_STATE;
850 /* Update total byte transfered */
851 message->actual_length += drv_data->len_in_bytes;
852 /* Move to next transfer of this msg */
853 message->state = bfin_spi_next_transfer(drv_data);
854 if (drv_data->cs_change)
855 bfin_spi_cs_deactive(drv_data, chip);
858 /* Schedule next transfer tasklet */
859 tasklet_schedule(&drv_data->pump_transfers);
862 /* pop a msg from queue and kick off real transfer */
863 static void bfin_spi_pump_messages(struct work_struct *work)
865 struct driver_data *drv_data;
868 drv_data = container_of(work, struct driver_data, pump_messages);
870 /* Lock queue and check for queue work */
871 spin_lock_irqsave(&drv_data->lock, flags);
872 if (list_empty(&drv_data->queue) || !drv_data->running) {
873 /* pumper kicked off but no work to do */
875 spin_unlock_irqrestore(&drv_data->lock, flags);
879 /* Make sure we are not already running a message */
880 if (drv_data->cur_msg) {
881 spin_unlock_irqrestore(&drv_data->lock, flags);
885 /* Extract head of queue */
886 drv_data->cur_msg = list_entry(drv_data->queue.next,
887 struct spi_message, queue);
889 /* Setup the SSP using the per chip configuration */
890 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
891 bfin_spi_restore_state(drv_data);
893 list_del_init(&drv_data->cur_msg->queue);
895 /* Initial message state */
896 drv_data->cur_msg->state = START_STATE;
897 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
898 struct spi_transfer, transfer_list);
900 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
901 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
902 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
903 drv_data->cur_chip->ctl_reg);
905 dev_dbg(&drv_data->pdev->dev,
906 "the first transfer len is %d\n",
907 drv_data->cur_transfer->len);
909 /* Mark as busy and launch transfers */
910 tasklet_schedule(&drv_data->pump_transfers);
913 spin_unlock_irqrestore(&drv_data->lock, flags);
917 * got a msg to transfer, queue it in drv_data->queue.
918 * And kick off message pumper
920 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
922 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
925 spin_lock_irqsave(&drv_data->lock, flags);
927 if (!drv_data->running) {
928 spin_unlock_irqrestore(&drv_data->lock, flags);
932 msg->actual_length = 0;
933 msg->status = -EINPROGRESS;
934 msg->state = START_STATE;
936 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
937 list_add_tail(&msg->queue, &drv_data->queue);
939 if (drv_data->running && !drv_data->busy)
940 queue_work(drv_data->workqueue, &drv_data->pump_messages);
942 spin_unlock_irqrestore(&drv_data->lock, flags);
947 #define MAX_SPI_SSEL 7
949 static u16 ssel[][MAX_SPI_SSEL] = {
950 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
951 P_SPI0_SSEL4, P_SPI0_SSEL5,
952 P_SPI0_SSEL6, P_SPI0_SSEL7},
954 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
955 P_SPI1_SSEL4, P_SPI1_SSEL5,
956 P_SPI1_SSEL6, P_SPI1_SSEL7},
958 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
959 P_SPI2_SSEL4, P_SPI2_SSEL5,
960 P_SPI2_SSEL6, P_SPI2_SSEL7},
963 /* setup for devices (may be called multiple times -- not just first setup) */
964 static int bfin_spi_setup(struct spi_device *spi)
966 struct bfin5xx_spi_chip *chip_info;
967 struct chip_data *chip = NULL;
968 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
971 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
974 /* Only alloc (or use chip_info) on first setup */
976 chip = spi_get_ctldata(spi);
978 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
980 dev_err(&spi->dev, "cannot allocate chip data\n");
985 chip->enable_dma = 0;
986 chip_info = spi->controller_data;
989 /* chip_info isn't always needed */
991 /* Make sure people stop trying to set fields via ctl_reg
992 * when they should actually be using common SPI framework.
993 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
994 * Not sure if a user actually needs/uses any of these,
995 * but let's assume (for now) they do.
997 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
998 dev_err(&spi->dev, "do not set bits in ctl_reg "
999 "that the SPI framework manages\n");
1003 chip->enable_dma = chip_info->enable_dma != 0
1004 && drv_data->master_info->enable_dma;
1005 chip->ctl_reg = chip_info->ctl_reg;
1006 chip->bits_per_word = chip_info->bits_per_word;
1007 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1008 chip->cs_gpio = chip_info->cs_gpio;
1009 chip->idle_tx_val = chip_info->idle_tx_val;
1010 chip->pio_interrupt = chip_info->pio_interrupt;
1013 /* translate common spi framework into our register */
1014 if (spi->mode & SPI_CPOL)
1015 chip->ctl_reg |= CPOL;
1016 if (spi->mode & SPI_CPHA)
1017 chip->ctl_reg |= CPHA;
1018 if (spi->mode & SPI_LSB_FIRST)
1019 chip->ctl_reg |= LSBF;
1020 /* we dont support running in slave mode (yet?) */
1021 chip->ctl_reg |= MSTR;
1024 * Notice: for blackfin, the speed_hz is the value of register
1025 * SPI_BAUD, not the real baudrate
1027 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1028 chip->flag = (1 << (spi->chip_select)) << 8;
1029 chip->chip_select_num = spi->chip_select;
1031 switch (chip->bits_per_word) {
1034 chip->width = CFG_SPI_WORDSIZE8;
1035 chip->read = bfin_spi_u8_reader;
1036 chip->write = bfin_spi_u8_writer;
1037 chip->duplex = bfin_spi_u8_duplex;
1042 chip->width = CFG_SPI_WORDSIZE16;
1043 chip->read = bfin_spi_u16_reader;
1044 chip->write = bfin_spi_u16_writer;
1045 chip->duplex = bfin_spi_u16_duplex;
1049 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1050 chip->bits_per_word);
1054 if (chip->enable_dma && chip->pio_interrupt) {
1055 dev_err(&spi->dev, "enable_dma is set, "
1056 "do not set pio_interrupt\n");
1060 * if any one SPI chip is registered and wants DMA, request the
1061 * DMA channel for it
1063 if (chip->enable_dma && !drv_data->dma_requested) {
1064 /* register dma irq handler */
1065 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1068 "Unable to request BlackFin SPI DMA channel\n");
1071 drv_data->dma_requested = 1;
1073 ret = set_dma_callback(drv_data->dma_channel,
1074 bfin_spi_dma_irq_handler, drv_data);
1076 dev_err(&spi->dev, "Unable to set dma callback\n");
1079 dma_disable_irq(drv_data->dma_channel);
1082 if (chip->pio_interrupt && !drv_data->irq_requested) {
1083 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1084 IRQF_DISABLED, "BFIN_SPI", drv_data);
1086 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1089 drv_data->irq_requested = 1;
1090 /* we use write mode, spi irq has to be disabled here */
1091 disable_irq(drv_data->spi_irq);
1094 if (chip->chip_select_num == 0) {
1095 ret = gpio_request(chip->cs_gpio, spi->modalias);
1097 dev_err(&spi->dev, "gpio_request() error\n");
1100 gpio_direction_output(chip->cs_gpio, 1);
1103 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1104 spi->modalias, chip->width, chip->enable_dma);
1105 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1106 chip->ctl_reg, chip->flag);
1108 spi_set_ctldata(spi, chip);
1110 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1111 if (chip->chip_select_num > 0 &&
1112 chip->chip_select_num <= spi->master->num_chipselect) {
1113 ret = peripheral_request(ssel[spi->master->bus_num]
1114 [chip->chip_select_num-1], spi->modalias);
1116 dev_err(&spi->dev, "peripheral_request() error\n");
1121 bfin_spi_cs_enable(drv_data, chip);
1122 bfin_spi_cs_deactive(drv_data, chip);
1127 if (chip->chip_select_num == 0)
1128 gpio_free(chip->cs_gpio);
1130 peripheral_free(ssel[spi->master->bus_num]
1131 [chip->chip_select_num - 1]);
1134 if (drv_data->dma_requested)
1135 free_dma(drv_data->dma_channel);
1136 drv_data->dma_requested = 0;
1139 /* prevent free 'chip' twice */
1140 spi_set_ctldata(spi, NULL);
1147 * callback for spi framework.
1148 * clean driver specific data
1150 static void bfin_spi_cleanup(struct spi_device *spi)
1152 struct chip_data *chip = spi_get_ctldata(spi);
1153 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1158 if ((chip->chip_select_num > 0)
1159 && (chip->chip_select_num <= spi->master->num_chipselect)) {
1160 peripheral_free(ssel[spi->master->bus_num]
1161 [chip->chip_select_num-1]);
1162 bfin_spi_cs_disable(drv_data, chip);
1165 if (chip->chip_select_num == 0)
1166 gpio_free(chip->cs_gpio);
1169 /* prevent free 'chip' twice */
1170 spi_set_ctldata(spi, NULL);
1173 static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1175 INIT_LIST_HEAD(&drv_data->queue);
1176 spin_lock_init(&drv_data->lock);
1178 drv_data->running = false;
1181 /* init transfer tasklet */
1182 tasklet_init(&drv_data->pump_transfers,
1183 bfin_spi_pump_transfers, (unsigned long)drv_data);
1185 /* init messages workqueue */
1186 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1187 drv_data->workqueue = create_singlethread_workqueue(
1188 dev_name(drv_data->master->dev.parent));
1189 if (drv_data->workqueue == NULL)
1195 static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1197 unsigned long flags;
1199 spin_lock_irqsave(&drv_data->lock, flags);
1201 if (drv_data->running || drv_data->busy) {
1202 spin_unlock_irqrestore(&drv_data->lock, flags);
1206 drv_data->running = true;
1207 drv_data->cur_msg = NULL;
1208 drv_data->cur_transfer = NULL;
1209 drv_data->cur_chip = NULL;
1210 spin_unlock_irqrestore(&drv_data->lock, flags);
1212 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1217 static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1219 unsigned long flags;
1220 unsigned limit = 500;
1223 spin_lock_irqsave(&drv_data->lock, flags);
1226 * This is a bit lame, but is optimized for the common execution path.
1227 * A wait_queue on the drv_data->busy could be used, but then the common
1228 * execution path (pump_messages) would be required to call wake_up or
1229 * friends on every SPI message. Do this instead
1231 drv_data->running = false;
1232 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1233 spin_unlock_irqrestore(&drv_data->lock, flags);
1235 spin_lock_irqsave(&drv_data->lock, flags);
1238 if (!list_empty(&drv_data->queue) || drv_data->busy)
1241 spin_unlock_irqrestore(&drv_data->lock, flags);
1246 static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1250 status = bfin_spi_stop_queue(drv_data);
1254 destroy_workqueue(drv_data->workqueue);
1259 static int __init bfin_spi_probe(struct platform_device *pdev)
1261 struct device *dev = &pdev->dev;
1262 struct bfin5xx_spi_master *platform_info;
1263 struct spi_master *master;
1264 struct driver_data *drv_data = 0;
1265 struct resource *res;
1268 platform_info = dev->platform_data;
1270 /* Allocate master with space for drv_data */
1271 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1273 dev_err(&pdev->dev, "can not alloc spi_master\n");
1277 drv_data = spi_master_get_devdata(master);
1278 drv_data->master = master;
1279 drv_data->master_info = platform_info;
1280 drv_data->pdev = pdev;
1281 drv_data->pin_req = platform_info->pin_req;
1283 /* the spi->mode bits supported by this driver: */
1284 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1286 master->bus_num = pdev->id;
1287 master->num_chipselect = platform_info->num_chipselect;
1288 master->cleanup = bfin_spi_cleanup;
1289 master->setup = bfin_spi_setup;
1290 master->transfer = bfin_spi_transfer;
1292 /* Find and map our resources */
1293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1295 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1297 goto out_error_get_res;
1300 drv_data->regs_base = ioremap(res->start, resource_size(res));
1301 if (drv_data->regs_base == NULL) {
1302 dev_err(dev, "Cannot map IO\n");
1304 goto out_error_ioremap;
1307 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1309 dev_err(dev, "No DMA channel specified\n");
1311 goto out_error_free_io;
1313 drv_data->dma_channel = res->start;
1315 drv_data->spi_irq = platform_get_irq(pdev, 0);
1316 if (drv_data->spi_irq < 0) {
1317 dev_err(dev, "No spi pio irq specified\n");
1319 goto out_error_free_io;
1322 /* Initial and start queue */
1323 status = bfin_spi_init_queue(drv_data);
1325 dev_err(dev, "problem initializing queue\n");
1326 goto out_error_queue_alloc;
1329 status = bfin_spi_start_queue(drv_data);
1331 dev_err(dev, "problem starting queue\n");
1332 goto out_error_queue_alloc;
1335 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1337 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1338 goto out_error_queue_alloc;
1341 /* Reset SPI registers. If these registers were used by the boot loader,
1342 * the sky may fall on your head if you enable the dma controller.
1344 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1345 write_FLAG(drv_data, 0xFF00);
1347 /* Register with the SPI framework */
1348 platform_set_drvdata(pdev, drv_data);
1349 status = spi_register_master(master);
1351 dev_err(dev, "problem registering spi master\n");
1352 goto out_error_queue_alloc;
1355 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1356 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1357 drv_data->dma_channel);
1360 out_error_queue_alloc:
1361 bfin_spi_destroy_queue(drv_data);
1363 iounmap((void *) drv_data->regs_base);
1366 spi_master_put(master);
1371 /* stop hardware and remove the driver */
1372 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1374 struct driver_data *drv_data = platform_get_drvdata(pdev);
1380 /* Remove the queue */
1381 status = bfin_spi_destroy_queue(drv_data);
1385 /* Disable the SSP at the peripheral and SOC level */
1386 bfin_spi_disable(drv_data);
1389 if (drv_data->master_info->enable_dma) {
1390 if (dma_channel_active(drv_data->dma_channel))
1391 free_dma(drv_data->dma_channel);
1394 if (drv_data->irq_requested) {
1395 free_irq(drv_data->spi_irq, drv_data);
1396 drv_data->irq_requested = 0;
1399 /* Disconnect from the SPI framework */
1400 spi_unregister_master(drv_data->master);
1402 peripheral_free_list(drv_data->pin_req);
1404 /* Prevent double remove */
1405 platform_set_drvdata(pdev, NULL);
1411 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1413 struct driver_data *drv_data = platform_get_drvdata(pdev);
1416 status = bfin_spi_stop_queue(drv_data);
1421 bfin_spi_disable(drv_data);
1426 static int bfin_spi_resume(struct platform_device *pdev)
1428 struct driver_data *drv_data = platform_get_drvdata(pdev);
1431 /* Enable the SPI interface */
1432 bfin_spi_enable(drv_data);
1434 /* Start the queue running */
1435 status = bfin_spi_start_queue(drv_data);
1437 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1444 #define bfin_spi_suspend NULL
1445 #define bfin_spi_resume NULL
1446 #endif /* CONFIG_PM */
1448 MODULE_ALIAS("platform:bfin-spi");
1449 static struct platform_driver bfin_spi_driver = {
1452 .owner = THIS_MODULE,
1454 .suspend = bfin_spi_suspend,
1455 .resume = bfin_spi_resume,
1456 .remove = __devexit_p(bfin_spi_remove),
1459 static int __init bfin_spi_init(void)
1461 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1463 module_init(bfin_spi_init);
1465 static void __exit bfin_spi_exit(void)
1467 platform_driver_unregister(&bfin_spi_driver);
1469 module_exit(bfin_spi_exit);