drivers/ssb/driver_chipcommon.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom ChipCommon core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <linux/ssb/ssb.h>
  12 #include <linux/ssb/ssb_regs.h>
  13 #include <linux/export.h>
  14 #include <linux/pci.h>
  15
  16 #include "ssb_private.h"
  17
  18
  19 /* Clock sources */
  20 enum ssb_clksrc {
  21         /* PCI clock */
  22         SSB_CHIPCO_CLKSRC_PCI,
  23         /* Crystal slow clock oscillator */
  24         SSB_CHIPCO_CLKSRC_XTALOS,
  25         /* Low power oscillator */
  26         SSB_CHIPCO_CLKSRC_LOPWROS,
  27 };
  28
  29
  30 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
  31                                         u32 mask, u32 value)
  32 {
  33         value &= mask;
  34         value |= chipco_read32(cc, offset) & ~mask;
  35         chipco_write32(cc, offset, value);
  36
  37         return value;
  38 }
  39
  40 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
  41                               enum ssb_clkmode mode)
  42 {
  43         struct ssb_device *ccdev = cc->dev;
  44         struct ssb_bus *bus;
  45         u32 tmp;
  46
  47         if (!ccdev)
  48                 return;
  49         bus = ccdev->bus;
  50
  51         /* We support SLOW only on 6..9 */
  52         if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
  53                 mode = SSB_CLKMODE_DYNAMIC;
  54
  55         if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
  56                 return; /* PMU controls clockmode, separated function needed */
  57         SSB_WARN_ON(ccdev->id.revision >= 20);
  58
  59         /* chipcommon cores prior to rev6 don't support dynamic clock control */
  60         if (ccdev->id.revision < 6)
  61                 return;
  62
  63         /* ChipCommon cores rev10+ need testing */
  64         if (ccdev->id.revision >= 10)
  65                 return;
  66
  67         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
  68                 return;
  69
  70         switch (mode) {
  71         case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
  72                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  73                 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  74                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  75                 break;
  76         case SSB_CLKMODE_FAST:
  77                 if (ccdev->id.revision < 10) {
  78                         ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
  79                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  80                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  81                         tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
  82                         chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  83                 } else {
  84                         chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
  85                                 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
  86                                  SSB_CHIPCO_SYSCLKCTL_FORCEHT));
  87                         /* udelay(150); TODO: not available in early init */
  88                 }
  89                 break;
  90         case SSB_CLKMODE_DYNAMIC:
  91                 if (ccdev->id.revision < 10) {
  92                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  93                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  94                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
  95                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  96                         if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
  97                             SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
  98                                 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  99                         chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
 100
 101                         /* For dynamic control, we have to release our xtal_pu
 102                          * "force on" */
 103                         if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
 104                                 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
 105                 } else {
 106                         chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
 107                                 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
 108                                  ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
 109                 }
 110                 break;
 111         default:
 112                 SSB_WARN_ON(1);
 113         }
 114 }
 115
 116 /* Get the Slow Clock Source */
 117 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
 118 {
 119         struct ssb_bus *bus = cc->dev->bus;
 120         u32 uninitialized_var(tmp);
 121
 122         if (cc->dev->id.revision < 6) {
 123                 if (bus->bustype == SSB_BUSTYPE_SSB ||
 124                     bus->bustype == SSB_BUSTYPE_PCMCIA)
 125                         return SSB_CHIPCO_CLKSRC_XTALOS;
 126                 if (bus->bustype == SSB_BUSTYPE_PCI) {
 127                         pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
 128                         if (tmp & 0x10)
 129                                 return SSB_CHIPCO_CLKSRC_PCI;
 130                         return SSB_CHIPCO_CLKSRC_XTALOS;
 131                 }
 132         }
 133         if (cc->dev->id.revision < 10) {
 134                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 135                 tmp &= 0x7;
 136                 if (tmp == 0)
 137                         return SSB_CHIPCO_CLKSRC_LOPWROS;
 138                 if (tmp == 1)
 139                         return SSB_CHIPCO_CLKSRC_XTALOS;
 140                 if (tmp == 2)
 141                         return SSB_CHIPCO_CLKSRC_PCI;
 142         }
 143
 144         return SSB_CHIPCO_CLKSRC_XTALOS;
 145 }
 146
 147 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
 148 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
 149 {
 150         int uninitialized_var(limit);
 151         enum ssb_clksrc clocksrc;
 152         int divisor = 1;
 153         u32 tmp;
 154
 155         clocksrc = chipco_pctl_get_slowclksrc(cc);
 156         if (cc->dev->id.revision < 6) {
 157                 switch (clocksrc) {
 158                 case SSB_CHIPCO_CLKSRC_PCI:
 159                         divisor = 64;
 160                         break;
 161                 case SSB_CHIPCO_CLKSRC_XTALOS:
 162                         divisor = 32;
 163                         break;
 164                 default:
 165                         SSB_WARN_ON(1);
 166                 }
 167         } else if (cc->dev->id.revision < 10) {
 168                 switch (clocksrc) {
 169                 case SSB_CHIPCO_CLKSRC_LOPWROS:
 170                         break;
 171                 case SSB_CHIPCO_CLKSRC_XTALOS:
 172                 case SSB_CHIPCO_CLKSRC_PCI:
 173                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 174                         divisor = (tmp >> 16) + 1;
 175                         divisor *= 4;
 176                         break;
 177                 }
 178         } else {
 179                 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
 180                 divisor = (tmp >> 16) + 1;
 181                 divisor *= 4;
 182         }
 183
 184         switch (clocksrc) {
 185         case SSB_CHIPCO_CLKSRC_LOPWROS:
 186                 if (get_max)
 187                         limit = 43000;
 188                 else
 189                         limit = 25000;
 190                 break;
 191         case SSB_CHIPCO_CLKSRC_XTALOS:
 192                 if (get_max)
 193                         limit = 20200000;
 194                 else
 195                         limit = 19800000;
 196                 break;
 197         case SSB_CHIPCO_CLKSRC_PCI:
 198                 if (get_max)
 199                         limit = 34000000;
 200                 else
 201                         limit = 25000000;
 202                 break;
 203         }
 204         limit /= divisor;
 205
 206         return limit;
 207 }
 208
 209 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
 210 {
 211         struct ssb_bus *bus = cc->dev->bus;
 212
 213         if (bus->chip_id == 0x4321) {
 214                 if (bus->chip_rev == 0)
 215                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
 216                 else if (bus->chip_rev == 1)
 217                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
 218         }
 219
 220         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 221                 return;
 222
 223         if (cc->dev->id.revision >= 10) {
 224                 /* Set Idle Power clock rate to 1Mhz */
 225                 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
 226                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
 227                                 0x0000FFFF) | 0x00040000);
 228         } else {
 229                 int maxfreq;
 230
 231                 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
 232                 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
 233                                (maxfreq * 150 + 999999) / 1000000);
 234                 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
 235                                (maxfreq * 15 + 999999) / 1000000);
 236         }
 237 }
 238
 239 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
 240 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
 241 {
 242         struct ssb_bus *bus = cc->dev->bus;
 243
 244         switch (bus->chip_id) {
 245         case 0x4312:
 246         case 0x4322:
 247         case 0x4328:
 248                 return 7000;
 249         case 0x4325:
 250                 /* TODO: */
 251         default:
 252                 return 15000;
 253         }
 254 }
 255
 256 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
 257 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
 258 {
 259         struct ssb_bus *bus = cc->dev->bus;
 260         int minfreq;
 261         unsigned int tmp;
 262         u32 pll_on_delay;
 263
 264         if (bus->bustype != SSB_BUSTYPE_PCI)
 265                 return;
 266
 267         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 268                 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
 269                 return;
 270         }
 271
 272         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 273                 return;
 274
 275         minfreq = chipco_pctl_clockfreqlimit(cc, 0);
 276         pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
 277         tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
 278         SSB_WARN_ON(tmp & ~0xFFFF);
 279
 280         cc->fast_pwrup_delay = tmp;
 281 }
 282
 283 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 284 {
 285         if (!cc->dev)
 286                 return; /* We don't have a ChipCommon */
 287
 288         spin_lock_init(&cc->gpio_lock);
 289
 290         if (cc->dev->id.revision >= 11)
 291                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
 292         ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
 293
 294         if (cc->dev->id.revision >= 20) {
 295                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
 296                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
 297         }
 298
 299         ssb_pmu_init(cc);
 300         chipco_powercontrol_init(cc);
 301         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 302         calc_fast_powerup_delay(cc);
 303 }
 304
 305 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 306 {
 307         if (!cc->dev)
 308                 return;
 309         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
 310 }
 311
 312 void ssb_chipco_resume(struct ssb_chipcommon *cc)
 313 {
 314         if (!cc->dev)
 315                 return;
 316         chipco_powercontrol_init(cc);
 317         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 318 }
 319
 320 /* Get the processor clock */
 321 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
 322                              u32 *plltype, u32 *n, u32 *m)
 323 {
 324         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 325         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 326         switch (*plltype) {
 327         case SSB_PLLTYPE_2:
 328         case SSB_PLLTYPE_4:
 329         case SSB_PLLTYPE_6:
 330         case SSB_PLLTYPE_7:
 331                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 332                 break;
 333         case SSB_PLLTYPE_3:
 334                 /* 5350 uses m2 to control mips */
 335                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 336                 break;
 337         default:
 338                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 339                 break;
 340         }
 341 }
 342
 343 /* Get the bus clock */
 344 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
 345                                  u32 *plltype, u32 *n, u32 *m)
 346 {
 347         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 348         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 349         switch (*plltype) {
 350         case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
 351                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 352                 break;
 353         case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
 354                 if (cc->dev->bus->chip_id != 0x5365) {
 355                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 356                         break;
 357                 }
 358                 /* Fallthough */
 359         default:
 360                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 361         }
 362 }
 363
 364 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
 365                             unsigned long ns)
 366 {
 367         struct ssb_device *dev = cc->dev;
 368         struct ssb_bus *bus = dev->bus;
 369         u32 tmp;
 370
 371         /* set register for external IO to control LED. */
 372         chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
 373         tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;            /* Waitcount-3 = 10ns */
 374         tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;   /* Waitcount-1 = 40ns */
 375         tmp |= DIV_ROUND_UP(240, ns);                           /* Waitcount-0 = 240ns */
 376         chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
 377
 378         /* Set timing for the flash */
 379         tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT;   /* Waitcount-3 = 10nS */
 380         tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT;  /* Waitcount-1 = 10nS */
 381         tmp |= DIV_ROUND_UP(120, ns);                           /* Waitcount-0 = 120nS */
 382         if ((bus->chip_id == 0x5365) ||
 383             (dev->id.revision < 9))
 384                 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
 385         if ((bus->chip_id == 0x5365) ||
 386             (dev->id.revision < 9) ||
 387             ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
 388                 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
 389
 390         if (bus->chip_id == 0x5350) {
 391                 /* Enable EXTIF */
 392                 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;      /* Waitcount-3 = 10ns */
 393                 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
 394                 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
 395                 tmp |= DIV_ROUND_UP(120, ns);                     /* Waitcount-0 = 120ns */
 396                 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
 397         }
 398 }
 399
 400 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 401 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 402 {
 403         /* instant NMI */
 404         chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 405 }
 406
 407 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 408 {
 409         chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
 410 }
 411
 412 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
 413 {
 414         return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
 415 }
 416
 417 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
 418 {
 419         return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
 420 }
 421
 422 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
 423 {
 424         unsigned long flags;
 425         u32 res = 0;
 426
 427         spin_lock_irqsave(&cc->gpio_lock, flags);
 428         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 429         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 430
 431         return res;
 432 }
 433
 434 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
 435 {
 436         unsigned long flags;
 437         u32 res = 0;
 438
 439         spin_lock_irqsave(&cc->gpio_lock, flags);
 440         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 441         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 442
 443         return res;
 444 }
 445
 446 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
 447 {
 448         unsigned long flags;
 449         u32 res = 0;
 450
 451         spin_lock_irqsave(&cc->gpio_lock, flags);
 452         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 453         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 454
 455         return res;
 456 }
 457 EXPORT_SYMBOL(ssb_chipco_gpio_control);
 458
 459 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 460 {
 461         unsigned long flags;
 462         u32 res = 0;
 463
 464         spin_lock_irqsave(&cc->gpio_lock, flags);
 465         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 466         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 467
 468         return res;
 469 }
 470
 471 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 472 {
 473         unsigned long flags;
 474         u32 res = 0;
 475
 476         spin_lock_irqsave(&cc->gpio_lock, flags);
 477         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 478         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 479
 480         return res;
 481 }
 482
 483 u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
 484 {
 485         unsigned long flags;
 486         u32 res = 0;
 487
 488         if (cc->dev->id.revision < 20)
 489                 return 0xffffffff;
 490
 491         spin_lock_irqsave(&cc->gpio_lock, flags);
 492         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
 493         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 494
 495         return res;
 496 }
 497
 498 u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
 499 {
 500         unsigned long flags;
 501         u32 res = 0;
 502
 503         if (cc->dev->id.revision < 20)
 504                 return 0xffffffff;
 505
 506         spin_lock_irqsave(&cc->gpio_lock, flags);
 507         res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
 508         spin_unlock_irqrestore(&cc->gpio_lock, flags);
 509
 510         return res;
 511 }
 512
 513 #ifdef CONFIG_SSB_SERIAL
 514 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
 515                            struct ssb_serial_port *ports)
 516 {
 517         struct ssb_bus *bus = cc->dev->bus;
 518         int nr_ports = 0;
 519         u32 plltype;
 520         unsigned int irq;
 521         u32 baud_base, div;
 522         u32 i, n;
 523         unsigned int ccrev = cc->dev->id.revision;
 524
 525         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 526         irq = ssb_mips_irq(cc->dev);
 527
 528         if (plltype == SSB_PLLTYPE_1) {
 529                 /* PLL clock */
 530                 baud_base = ssb_calc_clock_rate(plltype,
 531                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
 532                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
 533                 div = 1;
 534         } else {
 535                 if (ccrev == 20) {
 536                         /* BCM5354 uses constant 25MHz clock */
 537                         baud_base = 25000000;
 538                         div = 48;
 539                         /* Set the override bit so we don't divide it */
 540                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 541                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 542                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 543                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 544                         /* Fixed ALP clock */
 545                         baud_base = 20000000;
 546                         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 547                                 /* FIXME: baud_base is different for devices with a PMU */
 548                                 SSB_WARN_ON(1);
 549                         }
 550                         div = 1;
 551                         if (ccrev >= 21) {
 552                                 /* Turn off UART clock before switching clocksource. */
 553                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
 554                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
 555                                                & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
 556                         }
 557                         /* Set the override bit so we don't divide it */
 558                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 559                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 560                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 561                         if (ccrev >= 21) {
 562                                 /* Re-enable the UART clock. */
 563                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
 564                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
 565                                                | SSB_CHIPCO_CORECTL_UARTCLKEN);
 566                         }
 567                 } else if (ccrev >= 3) {
 568                         /* Internal backplane clock */
 569                         baud_base = ssb_clockspeed(bus);
 570                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
 571                               & SSB_CHIPCO_CLKDIV_UART;
 572                 } else {
 573                         /* Fixed internal backplane clock */
 574                         baud_base = 88000000;
 575                         div = 48;
 576                 }
 577
 578                 /* Clock source depends on strapping if UartClkOverride is unset */
 579                 if ((ccrev > 0) &&
 580                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
 581                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
 582                             SSB_CHIPCO_CAP_UARTCLK_INT) {
 583                                 /* Internal divided backplane clock */
 584                                 baud_base /= div;
 585                         } else {
 586                                 /* Assume external clock of 1.8432 MHz */
 587                                 baud_base = 1843200;
 588                         }
 589                 }
 590         }
 591
 592         /* Determine the registers of the UARTs */
 593         n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
 594         for (i = 0; i < n; i++) {
 595                 void __iomem *cc_mmio;
 596                 void __iomem *uart_regs;
 597
 598                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
 599                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
 600                 /* Offset changed at after rev 0 */
 601                 if (ccrev == 0)
 602                         uart_regs += (i * 8);
 603                 else
 604                         uart_regs += (i * 256);
 605
 606                 nr_ports++;
 607                 ports[i].regs = uart_regs;
 608                 ports[i].irq = irq;
 609                 ports[i].baud_base = baud_base;
 610                 ports[i].reg_shift = 0;
 611         }
 612
 613         return nr_ports;
 614 }
 615 #endif /* CONFIG_SSB_SERIAL */