drivers/ssb/driver_chipcommon.c

   1 /*
   2  * Sonics Silicon Backplane
   3  * Broadcom ChipCommon core driver
   4  *
   5  * Copyright 2005, Broadcom Corporation
   6  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
   7  * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
   8  *
   9  * Licensed under the GNU/GPL. See COPYING for details.
  10  */
  11
  12 #include <linux/ssb/ssb.h>
  13 #include <linux/ssb/ssb_regs.h>
  14 #include <linux/export.h>
  15 #include <linux/pci.h>
  16 #include <linux/bcm47xx_wdt.h>
  17
  18 #include "ssb_private.h"
  19
  20
  21 /* Clock sources */
  22 enum ssb_clksrc {
  23         /* PCI clock */
  24         SSB_CHIPCO_CLKSRC_PCI,
  25         /* Crystal slow clock oscillator */
  26         SSB_CHIPCO_CLKSRC_XTALOS,
  27         /* Low power oscillator */
  28         SSB_CHIPCO_CLKSRC_LOPWROS,
  29 };
  30
  31
  32 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
  33                                         u32 mask, u32 value)
  34 {
  35         value &= mask;
  36         value |= chipco_read32(cc, offset) & ~mask;
  37         chipco_write32(cc, offset, value);
  38
  39         return value;
  40 }
  41
  42 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
  43                               enum ssb_clkmode mode)
  44 {
  45         struct ssb_device *ccdev = cc->dev;
  46         struct ssb_bus *bus;
  47         u32 tmp;
  48
  49         if (!ccdev)
  50                 return;
  51         bus = ccdev->bus;
  52
  53         /* We support SLOW only on 6..9 */
  54         if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
  55                 mode = SSB_CLKMODE_DYNAMIC;
  56
  57         if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
  58                 return; /* PMU controls clockmode, separated function needed */
  59         SSB_WARN_ON(ccdev->id.revision >= 20);
  60
  61         /* chipcommon cores prior to rev6 don't support dynamic clock control */
  62         if (ccdev->id.revision < 6)
  63                 return;
  64
  65         /* ChipCommon cores rev10+ need testing */
  66         if (ccdev->id.revision >= 10)
  67                 return;
  68
  69         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
  70                 return;
  71
  72         switch (mode) {
  73         case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
  74                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  75                 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  76                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  77                 break;
  78         case SSB_CLKMODE_FAST:
  79                 if (ccdev->id.revision < 10) {
  80                         ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
  81                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  82                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  83                         tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
  84                         chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
  85                 } else {
  86                         chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
  87                                 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
  88                                  SSB_CHIPCO_SYSCLKCTL_FORCEHT));
  89                         /* udelay(150); TODO: not available in early init */
  90                 }
  91                 break;
  92         case SSB_CLKMODE_DYNAMIC:
  93                 if (ccdev->id.revision < 10) {
  94                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
  95                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
  96                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
  97                         tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
  98                         if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
  99                             SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
 100                                 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
 101                         chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
 102
 103                         /* For dynamic control, we have to release our xtal_pu
 104                          * "force on" */
 105                         if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
 106                                 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
 107                 } else {
 108                         chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
 109                                 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
 110                                  ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
 111                 }
 112                 break;
 113         default:
 114                 SSB_WARN_ON(1);
 115         }
 116 }
 117
 118 /* Get the Slow Clock Source */
 119 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
 120 {
 121         struct ssb_bus *bus = cc->dev->bus;
 122         u32 uninitialized_var(tmp);
 123
 124         if (cc->dev->id.revision < 6) {
 125                 if (bus->bustype == SSB_BUSTYPE_SSB ||
 126                     bus->bustype == SSB_BUSTYPE_PCMCIA)
 127                         return SSB_CHIPCO_CLKSRC_XTALOS;
 128                 if (bus->bustype == SSB_BUSTYPE_PCI) {
 129                         pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
 130                         if (tmp & 0x10)
 131                                 return SSB_CHIPCO_CLKSRC_PCI;
 132                         return SSB_CHIPCO_CLKSRC_XTALOS;
 133                 }
 134         }
 135         if (cc->dev->id.revision < 10) {
 136                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 137                 tmp &= 0x7;
 138                 if (tmp == 0)
 139                         return SSB_CHIPCO_CLKSRC_LOPWROS;
 140                 if (tmp == 1)
 141                         return SSB_CHIPCO_CLKSRC_XTALOS;
 142                 if (tmp == 2)
 143                         return SSB_CHIPCO_CLKSRC_PCI;
 144         }
 145
 146         return SSB_CHIPCO_CLKSRC_XTALOS;
 147 }
 148
 149 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
 150 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
 151 {
 152         int uninitialized_var(limit);
 153         enum ssb_clksrc clocksrc;
 154         int divisor = 1;
 155         u32 tmp;
 156
 157         clocksrc = chipco_pctl_get_slowclksrc(cc);
 158         if (cc->dev->id.revision < 6) {
 159                 switch (clocksrc) {
 160                 case SSB_CHIPCO_CLKSRC_PCI:
 161                         divisor = 64;
 162                         break;
 163                 case SSB_CHIPCO_CLKSRC_XTALOS:
 164                         divisor = 32;
 165                         break;
 166                 default:
 167                         SSB_WARN_ON(1);
 168                 }
 169         } else if (cc->dev->id.revision < 10) {
 170                 switch (clocksrc) {
 171                 case SSB_CHIPCO_CLKSRC_LOPWROS:
 172                         break;
 173                 case SSB_CHIPCO_CLKSRC_XTALOS:
 174                 case SSB_CHIPCO_CLKSRC_PCI:
 175                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
 176                         divisor = (tmp >> 16) + 1;
 177                         divisor *= 4;
 178                         break;
 179                 }
 180         } else {
 181                 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
 182                 divisor = (tmp >> 16) + 1;
 183                 divisor *= 4;
 184         }
 185
 186         switch (clocksrc) {
 187         case SSB_CHIPCO_CLKSRC_LOPWROS:
 188                 if (get_max)
 189                         limit = 43000;
 190                 else
 191                         limit = 25000;
 192                 break;
 193         case SSB_CHIPCO_CLKSRC_XTALOS:
 194                 if (get_max)
 195                         limit = 20200000;
 196                 else
 197                         limit = 19800000;
 198                 break;
 199         case SSB_CHIPCO_CLKSRC_PCI:
 200                 if (get_max)
 201                         limit = 34000000;
 202                 else
 203                         limit = 25000000;
 204                 break;
 205         }
 206         limit /= divisor;
 207
 208         return limit;
 209 }
 210
 211 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
 212 {
 213         struct ssb_bus *bus = cc->dev->bus;
 214
 215         if (bus->chip_id == 0x4321) {
 216                 if (bus->chip_rev == 0)
 217                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
 218                 else if (bus->chip_rev == 1)
 219                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
 220         }
 221
 222         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 223                 return;
 224
 225         if (cc->dev->id.revision >= 10) {
 226                 /* Set Idle Power clock rate to 1Mhz */
 227                 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
 228                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
 229                                 0x0000FFFF) | 0x00040000);
 230         } else {
 231                 int maxfreq;
 232
 233                 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
 234                 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
 235                                (maxfreq * 150 + 999999) / 1000000);
 236                 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
 237                                (maxfreq * 15 + 999999) / 1000000);
 238         }
 239 }
 240
 241 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
 242 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
 243 {
 244         struct ssb_bus *bus = cc->dev->bus;
 245
 246         switch (bus->chip_id) {
 247         case 0x4312:
 248         case 0x4322:
 249         case 0x4328:
 250                 return 7000;
 251         case 0x4325:
 252                 /* TODO: */
 253         default:
 254                 return 15000;
 255         }
 256 }
 257
 258 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
 259 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
 260 {
 261         struct ssb_bus *bus = cc->dev->bus;
 262         int minfreq;
 263         unsigned int tmp;
 264         u32 pll_on_delay;
 265
 266         if (bus->bustype != SSB_BUSTYPE_PCI)
 267                 return;
 268
 269         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 270                 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
 271                 return;
 272         }
 273
 274         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
 275                 return;
 276
 277         minfreq = chipco_pctl_clockfreqlimit(cc, 0);
 278         pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
 279         tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
 280         SSB_WARN_ON(tmp & ~0xFFFF);
 281
 282         cc->fast_pwrup_delay = tmp;
 283 }
 284
 285 static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
 286 {
 287         if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
 288                 return ssb_pmu_get_alp_clock(cc);
 289
 290         return 20000000;
 291 }
 292
 293 static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
 294 {
 295         u32 nb;
 296
 297         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 298                 if (cc->dev->id.revision < 26)
 299                         nb = 16;
 300                 else
 301                         nb = (cc->dev->id.revision >= 37) ? 32 : 24;
 302         } else {
 303                 nb = 28;
 304         }
 305         if (nb == 32)
 306                 return 0xffffffff;
 307         else
 308                 return (1 << nb) - 1;
 309 }
 310
 311 u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
 312 {
 313         struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 314
 315         if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 316                 return 0;
 317
 318         return ssb_chipco_watchdog_timer_set(cc, ticks);
 319 }
 320
 321 u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
 322 {
 323         struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
 324         u32 ticks;
 325
 326         if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
 327                 return 0;
 328
 329         ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
 330         return ticks / cc->ticks_per_ms;
 331 }
 332
 333 static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
 334 {
 335         struct ssb_bus *bus = cc->dev->bus;
 336
 337         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 338                         /* based on 32KHz ILP clock */
 339                         return 32;
 340         } else {
 341                 if (cc->dev->id.revision < 18)
 342                         return ssb_clockspeed(bus) / 1000;
 343                 else
 344                         return ssb_chipco_alp_clock(cc) / 1000;
 345         }
 346 }
 347
 348 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
 349 {
 350         if (!cc->dev)
 351                 return; /* We don't have a ChipCommon */
 352         if (cc->dev->id.revision >= 11)
 353                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
 354         ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
 355
 356         if (cc->dev->id.revision >= 20) {
 357                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
 358                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
 359         }
 360
 361         ssb_pmu_init(cc);
 362         chipco_powercontrol_init(cc);
 363         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 364         calc_fast_powerup_delay(cc);
 365
 366         if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
 367                 cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
 368                 cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
 369         }
 370 }
 371
 372 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
 373 {
 374         if (!cc->dev)
 375                 return;
 376         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
 377 }
 378
 379 void ssb_chipco_resume(struct ssb_chipcommon *cc)
 380 {
 381         if (!cc->dev)
 382                 return;
 383         chipco_powercontrol_init(cc);
 384         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
 385 }
 386
 387 /* Get the processor clock */
 388 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
 389                              u32 *plltype, u32 *n, u32 *m)
 390 {
 391         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 392         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 393         switch (*plltype) {
 394         case SSB_PLLTYPE_2:
 395         case SSB_PLLTYPE_4:
 396         case SSB_PLLTYPE_6:
 397         case SSB_PLLTYPE_7:
 398                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 399                 break;
 400         case SSB_PLLTYPE_3:
 401                 /* 5350 uses m2 to control mips */
 402                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 403                 break;
 404         default:
 405                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 406                 break;
 407         }
 408 }
 409
 410 /* Get the bus clock */
 411 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
 412                                  u32 *plltype, u32 *n, u32 *m)
 413 {
 414         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
 415         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 416         switch (*plltype) {
 417         case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
 418                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
 419                 break;
 420         case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
 421                 if (cc->dev->bus->chip_id != 0x5365) {
 422                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
 423                         break;
 424                 }
 425                 /* Fallthough */
 426         default:
 427                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
 428         }
 429 }
 430
 431 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
 432                             unsigned long ns)
 433 {
 434         struct ssb_device *dev = cc->dev;
 435         struct ssb_bus *bus = dev->bus;
 436         u32 tmp;
 437
 438         /* set register for external IO to control LED. */
 439         chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
 440         tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;            /* Waitcount-3 = 10ns */
 441         tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;   /* Waitcount-1 = 40ns */
 442         tmp |= DIV_ROUND_UP(240, ns);                           /* Waitcount-0 = 240ns */
 443         chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
 444
 445         /* Set timing for the flash */
 446         tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT;   /* Waitcount-3 = 10nS */
 447         tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT;  /* Waitcount-1 = 10nS */
 448         tmp |= DIV_ROUND_UP(120, ns);                           /* Waitcount-0 = 120nS */
 449         if ((bus->chip_id == 0x5365) ||
 450             (dev->id.revision < 9))
 451                 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
 452         if ((bus->chip_id == 0x5365) ||
 453             (dev->id.revision < 9) ||
 454             ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
 455                 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
 456
 457         if (bus->chip_id == 0x5350) {
 458                 /* Enable EXTIF */
 459                 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;      /* Waitcount-3 = 10ns */
 460                 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
 461                 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
 462                 tmp |= DIV_ROUND_UP(120, ns);                     /* Waitcount-0 = 120ns */
 463                 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
 464         }
 465 }
 466
 467 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
 468 u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
 469 {
 470         u32 maxt;
 471         enum ssb_clkmode clkmode;
 472
 473         maxt = ssb_chipco_watchdog_get_max_timer(cc);
 474         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
 475                 if (ticks == 1)
 476                         ticks = 2;
 477                 else if (ticks > maxt)
 478                         ticks = maxt;
 479                 chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
 480         } else {
 481                 clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
 482                 ssb_chipco_set_clockmode(cc, clkmode);
 483                 if (ticks > maxt)
 484                         ticks = maxt;
 485                 /* instant NMI */
 486                 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
 487         }
 488         return ticks;
 489 }
 490
 491 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 492 {
 493         chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
 494 }
 495
 496 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
 497 {
 498         return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
 499 }
 500
 501 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
 502 {
 503         return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
 504 }
 505
 506 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
 507 {
 508         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
 509 }
 510
 511 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
 512 {
 513         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
 514 }
 515
 516 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
 517 {
 518         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
 519 }
 520 EXPORT_SYMBOL(ssb_chipco_gpio_control);
 521
 522 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
 523 {
 524         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
 525 }
 526
 527 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
 528 {
 529         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
 530 }
 531
 532 #ifdef CONFIG_SSB_SERIAL
 533 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
 534                            struct ssb_serial_port *ports)
 535 {
 536         struct ssb_bus *bus = cc->dev->bus;
 537         int nr_ports = 0;
 538         u32 plltype;
 539         unsigned int irq;
 540         u32 baud_base, div;
 541         u32 i, n;
 542         unsigned int ccrev = cc->dev->id.revision;
 543
 544         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
 545         irq = ssb_mips_irq(cc->dev);
 546
 547         if (plltype == SSB_PLLTYPE_1) {
 548                 /* PLL clock */
 549                 baud_base = ssb_calc_clock_rate(plltype,
 550                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
 551                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
 552                 div = 1;
 553         } else {
 554                 if (ccrev == 20) {
 555                         /* BCM5354 uses constant 25MHz clock */
 556                         baud_base = 25000000;
 557                         div = 48;
 558                         /* Set the override bit so we don't divide it */
 559                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 560                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 561                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 562                 } else if ((ccrev >= 11) && (ccrev != 15)) {
 563                         baud_base = ssb_chipco_alp_clock(cc);
 564                         div = 1;
 565                         if (ccrev >= 21) {
 566                                 /* Turn off UART clock before switching clocksource. */
 567                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
 568                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
 569                                                & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
 570                         }
 571                         /* Set the override bit so we don't divide it */
 572                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
 573                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
 574                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
 575                         if (ccrev >= 21) {
 576                                 /* Re-enable the UART clock. */
 577                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
 578                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
 579                                                | SSB_CHIPCO_CORECTL_UARTCLKEN);
 580                         }
 581                 } else if (ccrev >= 3) {
 582                         /* Internal backplane clock */
 583                         baud_base = ssb_clockspeed(bus);
 584                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
 585                               & SSB_CHIPCO_CLKDIV_UART;
 586                 } else {
 587                         /* Fixed internal backplane clock */
 588                         baud_base = 88000000;
 589                         div = 48;
 590                 }
 591
 592                 /* Clock source depends on strapping if UartClkOverride is unset */
 593                 if ((ccrev > 0) &&
 594                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
 595                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
 596                             SSB_CHIPCO_CAP_UARTCLK_INT) {
 597                                 /* Internal divided backplane clock */
 598                                 baud_base /= div;
 599                         } else {
 600                                 /* Assume external clock of 1.8432 MHz */
 601                                 baud_base = 1843200;
 602                         }
 603                 }
 604         }
 605
 606         /* Determine the registers of the UARTs */
 607         n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
 608         for (i = 0; i < n; i++) {
 609                 void __iomem *cc_mmio;
 610                 void __iomem *uart_regs;
 611
 612                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
 613                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
 614                 /* Offset changed at after rev 0 */
 615                 if (ccrev == 0)
 616                         uart_regs += (i * 8);
 617                 else
 618                         uart_regs += (i * 256);
 619
 620                 nr_ports++;
 621                 ports[i].regs = uart_regs;
 622                 ports[i].irq = irq;
 623                 ports[i].baud_base = baud_base;
 624                 ports[i].reg_shift = 0;
 625         }
 626
 627         return nr_ports;
 628 }
 629 #endif /* CONFIG_SSB_SERIAL */