2 * Sonics Silicon Backplane
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "ssb_private.h"
13 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pci.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/slab.h>
25 #include <pcmcia/cistpl.h>
26 #include <pcmcia/ds.h>
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
33 /* Temporary list of yet-to-be-attached buses */
34 static LIST_HEAD(attach_queue);
35 /* List if running buses */
36 static LIST_HEAD(buses);
37 /* Software ID counter */
38 static unsigned int next_busnumber;
39 /* buses_mutes locks the two buslists and the next_busnumber.
40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41 static DEFINE_MUTEX(buses_mutex);
43 /* There are differences in the codeflow, if the bus is
44 * initialized from early boot, as various needed services
45 * are not available early. This is a mechanism to delay
46 * these initializations to after early boot has finished.
47 * It's also used to avoid mutex locking, as that's not
48 * available and needed early. */
49 static bool ssb_is_early_boot = 1;
51 static void ssb_buses_lock(void);
52 static void ssb_buses_unlock(void);
55 #ifdef CONFIG_SSB_PCIHOST
56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
61 list_for_each_entry(bus, &buses, list) {
62 if (bus->bustype == SSB_BUSTYPE_PCI &&
63 bus->host_pci == pdev)
72 #endif /* CONFIG_SSB_PCIHOST */
74 #ifdef CONFIG_SSB_PCMCIAHOST
75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
80 list_for_each_entry(bus, &buses, list) {
81 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
82 bus->host_pcmcia == pdev)
91 #endif /* CONFIG_SSB_PCMCIAHOST */
93 #ifdef CONFIG_SSB_SDIOHOST
94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
99 list_for_each_entry(bus, &buses, list) {
100 if (bus->bustype == SSB_BUSTYPE_SDIO &&
101 bus->host_sdio == func)
110 #endif /* CONFIG_SSB_SDIOHOST */
112 int ssb_for_each_bus_call(unsigned long data,
113 int (*func)(struct ssb_bus *bus, unsigned long data))
119 list_for_each_entry(bus, &buses, list) {
120 res = func(bus, data);
131 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
134 get_device(dev->dev);
138 static void ssb_device_put(struct ssb_device *dev)
141 put_device(dev->dev);
144 static int ssb_device_resume(struct device *dev)
146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
147 struct ssb_driver *ssb_drv;
151 ssb_drv = drv_to_ssb_drv(dev->driver);
152 if (ssb_drv && ssb_drv->resume)
153 err = ssb_drv->resume(ssb_dev);
161 static int ssb_device_suspend(struct device *dev, pm_message_t state)
163 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
164 struct ssb_driver *ssb_drv;
168 ssb_drv = drv_to_ssb_drv(dev->driver);
169 if (ssb_drv && ssb_drv->suspend)
170 err = ssb_drv->suspend(ssb_dev, state);
178 int ssb_bus_resume(struct ssb_bus *bus)
182 /* Reset HW state information in memory, so that HW is
183 * completely reinitialized. */
184 bus->mapped_device = NULL;
185 #ifdef CONFIG_SSB_DRIVER_PCICORE
186 bus->pcicore.setup_done = 0;
189 err = ssb_bus_powerup(bus, 0);
192 err = ssb_pcmcia_hardware_setup(bus);
194 ssb_bus_may_powerdown(bus);
197 ssb_chipco_resume(&bus->chipco);
198 ssb_bus_may_powerdown(bus);
202 EXPORT_SYMBOL(ssb_bus_resume);
204 int ssb_bus_suspend(struct ssb_bus *bus)
206 ssb_chipco_suspend(&bus->chipco);
207 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
211 EXPORT_SYMBOL(ssb_bus_suspend);
213 #ifdef CONFIG_SSB_SPROM
214 /** ssb_devices_freeze - Freeze all devices on the bus.
216 * After freezing no device driver will be handling a device
217 * on this bus anymore. ssb_devices_thaw() must be called after
218 * a successful freeze to reactivate the devices.
221 * @ctx: Context structure. Pass this to ssb_devices_thaw().
223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
225 struct ssb_device *sdev;
226 struct ssb_driver *sdrv;
229 memset(ctx, 0, sizeof(*ctx));
231 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
233 for (i = 0; i < bus->nr_devices; i++) {
234 sdev = ssb_device_get(&bus->devices[i]);
236 if (!sdev->dev || !sdev->dev->driver ||
237 !device_is_registered(sdev->dev)) {
238 ssb_device_put(sdev);
241 sdrv = drv_to_ssb_drv(sdev->dev->driver);
242 if (SSB_WARN_ON(!sdrv->remove))
245 ctx->device_frozen[i] = 1;
251 /** ssb_devices_thaw - Unfreeze all devices on the bus.
253 * This will re-attach the device drivers and re-init the devices.
255 * @ctx: The context structure from ssb_devices_freeze()
257 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
259 struct ssb_bus *bus = ctx->bus;
260 struct ssb_device *sdev;
261 struct ssb_driver *sdrv;
265 for (i = 0; i < bus->nr_devices; i++) {
266 if (!ctx->device_frozen[i])
268 sdev = &bus->devices[i];
270 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
272 sdrv = drv_to_ssb_drv(sdev->dev->driver);
273 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
276 err = sdrv->probe(sdev, &sdev->id);
278 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
279 dev_name(sdev->dev));
282 ssb_device_put(sdev);
287 #endif /* CONFIG_SSB_SPROM */
289 static void ssb_device_shutdown(struct device *dev)
291 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
292 struct ssb_driver *ssb_drv;
296 ssb_drv = drv_to_ssb_drv(dev->driver);
297 if (ssb_drv && ssb_drv->shutdown)
298 ssb_drv->shutdown(ssb_dev);
301 static int ssb_device_remove(struct device *dev)
303 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
304 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
306 if (ssb_drv && ssb_drv->remove)
307 ssb_drv->remove(ssb_dev);
308 ssb_device_put(ssb_dev);
313 static int ssb_device_probe(struct device *dev)
315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
316 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
319 ssb_device_get(ssb_dev);
320 if (ssb_drv && ssb_drv->probe)
321 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
323 ssb_device_put(ssb_dev);
328 static int ssb_match_devid(const struct ssb_device_id *tabid,
329 const struct ssb_device_id *devid)
331 if ((tabid->vendor != devid->vendor) &&
332 tabid->vendor != SSB_ANY_VENDOR)
334 if ((tabid->coreid != devid->coreid) &&
335 tabid->coreid != SSB_ANY_ID)
337 if ((tabid->revision != devid->revision) &&
338 tabid->revision != SSB_ANY_REV)
343 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
345 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
346 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
347 const struct ssb_device_id *id;
349 for (id = ssb_drv->id_table;
350 id->vendor || id->coreid || id->revision;
352 if (ssb_match_devid(id, &ssb_dev->id))
353 return 1; /* found */
359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
361 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
366 return add_uevent_var(env,
367 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
368 ssb_dev->id.vendor, ssb_dev->id.coreid,
369 ssb_dev->id.revision);
372 #define ssb_config_attr(attrib, field, format_string) \
374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
379 ssb_config_attr(core_num, core_index, "%u\n")
380 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
381 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
382 ssb_config_attr(revision, id.revision, "%u\n")
383 ssb_config_attr(irq, irq, "%u\n")
385 name_show(struct device *dev, struct device_attribute *attr, char *buf)
387 return sprintf(buf, "%s\n",
388 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
391 static struct device_attribute ssb_device_attrs[] = {
401 static struct bus_type ssb_bustype = {
403 .match = ssb_bus_match,
404 .probe = ssb_device_probe,
405 .remove = ssb_device_remove,
406 .shutdown = ssb_device_shutdown,
407 .suspend = ssb_device_suspend,
408 .resume = ssb_device_resume,
409 .uevent = ssb_device_uevent,
410 .dev_attrs = ssb_device_attrs,
413 static void ssb_buses_lock(void)
415 /* See the comment at the ssb_is_early_boot definition */
416 if (!ssb_is_early_boot)
417 mutex_lock(&buses_mutex);
420 static void ssb_buses_unlock(void)
422 /* See the comment at the ssb_is_early_boot definition */
423 if (!ssb_is_early_boot)
424 mutex_unlock(&buses_mutex);
427 static void ssb_devices_unregister(struct ssb_bus *bus)
429 struct ssb_device *sdev;
432 for (i = bus->nr_devices - 1; i >= 0; i--) {
433 sdev = &(bus->devices[i]);
435 device_unregister(sdev->dev);
438 #ifdef CONFIG_SSB_EMBEDDED
439 if (bus->bustype == SSB_BUSTYPE_SSB)
440 platform_device_unregister(bus->watchdog);
444 void ssb_bus_unregister(struct ssb_bus *bus)
447 ssb_devices_unregister(bus);
448 list_del(&bus->list);
451 ssb_pcmcia_exit(bus);
455 EXPORT_SYMBOL(ssb_bus_unregister);
457 static void ssb_release_dev(struct device *dev)
459 struct __ssb_dev_wrapper *devwrap;
461 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
465 static int ssb_devices_register(struct ssb_bus *bus)
467 struct ssb_device *sdev;
469 struct __ssb_dev_wrapper *devwrap;
473 for (i = 0; i < bus->nr_devices; i++) {
474 sdev = &(bus->devices[i]);
476 /* We don't register SSB-system devices to the kernel,
477 * as the drivers for them are built into SSB. */
478 switch (sdev->id.coreid) {
479 case SSB_DEV_CHIPCOMMON:
484 case SSB_DEV_MIPS_3302:
489 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
491 ssb_printk(KERN_ERR PFX
492 "Could not allocate device\n");
497 devwrap->sdev = sdev;
499 dev->release = ssb_release_dev;
500 dev->bus = &ssb_bustype;
501 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
503 switch (bus->bustype) {
504 case SSB_BUSTYPE_PCI:
505 #ifdef CONFIG_SSB_PCIHOST
506 sdev->irq = bus->host_pci->irq;
507 dev->parent = &bus->host_pci->dev;
508 sdev->dma_dev = dev->parent;
511 case SSB_BUSTYPE_PCMCIA:
512 #ifdef CONFIG_SSB_PCMCIAHOST
513 sdev->irq = bus->host_pcmcia->irq;
514 dev->parent = &bus->host_pcmcia->dev;
517 case SSB_BUSTYPE_SDIO:
518 #ifdef CONFIG_SSB_SDIOHOST
519 dev->parent = &bus->host_sdio->dev;
522 case SSB_BUSTYPE_SSB:
523 dev->dma_mask = &dev->coherent_dma_mask;
529 err = device_register(dev);
531 ssb_printk(KERN_ERR PFX
532 "Could not register %s\n",
534 /* Set dev to NULL to not unregister
535 * dev on error unwinding. */
545 /* Unwind the already registered devices. */
546 ssb_devices_unregister(bus);
550 /* Needs ssb_buses_lock() */
551 static int __devinit ssb_attach_queued_buses(void)
553 struct ssb_bus *bus, *n;
555 int drop_them_all = 0;
557 list_for_each_entry_safe(bus, n, &attach_queue, list) {
559 list_del(&bus->list);
562 /* Can't init the PCIcore in ssb_bus_register(), as that
563 * is too early in boot for embedded systems
564 * (no udelay() available). So do it here in attach stage.
566 err = ssb_bus_powerup(bus, 0);
569 ssb_pcicore_init(&bus->pcicore);
570 if (bus->bustype == SSB_BUSTYPE_SSB)
571 ssb_watchdog_register(bus);
572 ssb_bus_may_powerdown(bus);
574 err = ssb_devices_register(bus);
578 list_del(&bus->list);
581 list_move_tail(&bus->list, &buses);
587 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
589 struct ssb_bus *bus = dev->bus;
591 offset += dev->core_index * SSB_CORE_SIZE;
592 return readb(bus->mmio + offset);
595 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
597 struct ssb_bus *bus = dev->bus;
599 offset += dev->core_index * SSB_CORE_SIZE;
600 return readw(bus->mmio + offset);
603 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
605 struct ssb_bus *bus = dev->bus;
607 offset += dev->core_index * SSB_CORE_SIZE;
608 return readl(bus->mmio + offset);
611 #ifdef CONFIG_SSB_BLOCKIO
612 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
613 size_t count, u16 offset, u8 reg_width)
615 struct ssb_bus *bus = dev->bus;
618 offset += dev->core_index * SSB_CORE_SIZE;
619 addr = bus->mmio + offset;
626 *buf = __raw_readb(addr);
633 __le16 *buf = buffer;
635 SSB_WARN_ON(count & 1);
637 *buf = (__force __le16)__raw_readw(addr);
644 __le32 *buf = buffer;
646 SSB_WARN_ON(count & 3);
648 *buf = (__force __le32)__raw_readl(addr);
658 #endif /* CONFIG_SSB_BLOCKIO */
660 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
662 struct ssb_bus *bus = dev->bus;
664 offset += dev->core_index * SSB_CORE_SIZE;
665 writeb(value, bus->mmio + offset);
668 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
670 struct ssb_bus *bus = dev->bus;
672 offset += dev->core_index * SSB_CORE_SIZE;
673 writew(value, bus->mmio + offset);
676 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
678 struct ssb_bus *bus = dev->bus;
680 offset += dev->core_index * SSB_CORE_SIZE;
681 writel(value, bus->mmio + offset);
684 #ifdef CONFIG_SSB_BLOCKIO
685 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
686 size_t count, u16 offset, u8 reg_width)
688 struct ssb_bus *bus = dev->bus;
691 offset += dev->core_index * SSB_CORE_SIZE;
692 addr = bus->mmio + offset;
696 const u8 *buf = buffer;
699 __raw_writeb(*buf, addr);
706 const __le16 *buf = buffer;
708 SSB_WARN_ON(count & 1);
710 __raw_writew((__force u16)(*buf), addr);
717 const __le32 *buf = buffer;
719 SSB_WARN_ON(count & 3);
721 __raw_writel((__force u32)(*buf), addr);
731 #endif /* CONFIG_SSB_BLOCKIO */
733 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
734 static const struct ssb_bus_ops ssb_ssb_ops = {
735 .read8 = ssb_ssb_read8,
736 .read16 = ssb_ssb_read16,
737 .read32 = ssb_ssb_read32,
738 .write8 = ssb_ssb_write8,
739 .write16 = ssb_ssb_write16,
740 .write32 = ssb_ssb_write32,
741 #ifdef CONFIG_SSB_BLOCKIO
742 .block_read = ssb_ssb_block_read,
743 .block_write = ssb_ssb_block_write,
747 static int ssb_fetch_invariants(struct ssb_bus *bus,
748 ssb_invariants_func_t get_invariants)
750 struct ssb_init_invariants iv;
753 memset(&iv, 0, sizeof(iv));
754 err = get_invariants(bus, &iv);
757 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
758 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
759 bus->has_cardbus_slot = iv.has_cardbus_slot;
764 static int __devinit ssb_bus_register(struct ssb_bus *bus,
765 ssb_invariants_func_t get_invariants,
766 unsigned long baseaddr)
770 spin_lock_init(&bus->bar_lock);
771 INIT_LIST_HEAD(&bus->list);
772 #ifdef CONFIG_SSB_EMBEDDED
773 spin_lock_init(&bus->gpio_lock);
776 /* Powerup the bus */
777 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
781 /* Init SDIO-host device (if any), before the scan */
782 err = ssb_sdio_init(bus);
784 goto err_disable_xtal;
787 bus->busnumber = next_busnumber;
788 /* Scan for devices (cores) */
789 err = ssb_bus_scan(bus, baseaddr);
793 /* Init PCI-host device (if any) */
794 err = ssb_pci_init(bus);
797 /* Init PCMCIA-host device (if any) */
798 err = ssb_pcmcia_init(bus);
802 /* Initialize basic system devices (if available) */
803 err = ssb_bus_powerup(bus, 0);
805 goto err_pcmcia_exit;
806 ssb_chipcommon_init(&bus->chipco);
807 ssb_mipscore_init(&bus->mipscore);
808 err = ssb_fetch_invariants(bus, get_invariants);
810 ssb_bus_may_powerdown(bus);
811 goto err_pcmcia_exit;
813 ssb_bus_may_powerdown(bus);
815 /* Queue it for attach.
816 * See the comment at the ssb_is_early_boot definition. */
817 list_add_tail(&bus->list, &attach_queue);
818 if (!ssb_is_early_boot) {
819 /* This is not early boot, so we must attach the bus now */
820 err = ssb_attach_queued_buses();
831 list_del(&bus->list);
833 ssb_pcmcia_exit(bus);
842 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
846 #ifdef CONFIG_SSB_PCIHOST
847 int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
848 struct pci_dev *host_pci)
852 bus->bustype = SSB_BUSTYPE_PCI;
853 bus->host_pci = host_pci;
854 bus->ops = &ssb_pci_ops;
856 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
858 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
859 "PCI device %s\n", dev_name(&host_pci->dev));
861 ssb_printk(KERN_ERR PFX "Failed to register PCI version"
862 " of SSB with error %d\n", err);
867 EXPORT_SYMBOL(ssb_bus_pcibus_register);
868 #endif /* CONFIG_SSB_PCIHOST */
870 #ifdef CONFIG_SSB_PCMCIAHOST
871 int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
872 struct pcmcia_device *pcmcia_dev,
873 unsigned long baseaddr)
877 bus->bustype = SSB_BUSTYPE_PCMCIA;
878 bus->host_pcmcia = pcmcia_dev;
879 bus->ops = &ssb_pcmcia_ops;
881 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
883 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
884 "PCMCIA device %s\n", pcmcia_dev->devname);
889 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
890 #endif /* CONFIG_SSB_PCMCIAHOST */
892 #ifdef CONFIG_SSB_SDIOHOST
893 int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
894 struct sdio_func *func,
899 bus->bustype = SSB_BUSTYPE_SDIO;
900 bus->host_sdio = func;
901 bus->ops = &ssb_sdio_ops;
902 bus->quirks = quirks;
904 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
906 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
907 "SDIO device %s\n", sdio_func_id(func));
912 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
913 #endif /* CONFIG_SSB_PCMCIAHOST */
915 int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
916 unsigned long baseaddr,
917 ssb_invariants_func_t get_invariants)
921 bus->bustype = SSB_BUSTYPE_SSB;
922 bus->ops = &ssb_ssb_ops;
924 err = ssb_bus_register(bus, get_invariants, baseaddr);
926 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
927 "address 0x%08lX\n", baseaddr);
933 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
935 drv->drv.name = drv->name;
936 drv->drv.bus = &ssb_bustype;
937 drv->drv.owner = owner;
939 return driver_register(&drv->drv);
941 EXPORT_SYMBOL(__ssb_driver_register);
943 void ssb_driver_unregister(struct ssb_driver *drv)
945 driver_unregister(&drv->drv);
947 EXPORT_SYMBOL(ssb_driver_unregister);
949 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
951 struct ssb_bus *bus = dev->bus;
952 struct ssb_device *ent;
955 for (i = 0; i < bus->nr_devices; i++) {
956 ent = &(bus->devices[i]);
957 if (ent->id.vendor != dev->id.vendor)
959 if (ent->id.coreid != dev->id.coreid)
962 ent->devtypedata = data;
965 EXPORT_SYMBOL(ssb_set_devtypedata);
967 static u32 clkfactor_f6_resolve(u32 v)
969 /* map the magic values */
971 case SSB_CHIPCO_CLK_F6_2:
973 case SSB_CHIPCO_CLK_F6_3:
975 case SSB_CHIPCO_CLK_F6_4:
977 case SSB_CHIPCO_CLK_F6_5:
979 case SSB_CHIPCO_CLK_F6_6:
981 case SSB_CHIPCO_CLK_F6_7:
987 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
988 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
990 u32 n1, n2, clock, m1, m2, m3, mc;
992 n1 = (n & SSB_CHIPCO_CLK_N1);
993 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
996 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
997 if (m & SSB_CHIPCO_CLK_T6_MMASK)
998 return SSB_CHIPCO_CLK_T6_M1;
999 return SSB_CHIPCO_CLK_T6_M0;
1000 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1001 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1002 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1003 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1004 n1 = clkfactor_f6_resolve(n1);
1005 n2 += SSB_CHIPCO_CLK_F5_BIAS;
1007 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
1008 n1 += SSB_CHIPCO_CLK_T2_BIAS;
1009 n2 += SSB_CHIPCO_CLK_T2_BIAS;
1010 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
1011 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
1013 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
1020 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1021 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1022 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
1025 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1030 m1 = (m & SSB_CHIPCO_CLK_M1);
1031 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1032 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1033 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1036 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1037 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1038 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1039 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1040 m1 = clkfactor_f6_resolve(m1);
1041 if ((plltype == SSB_PLLTYPE_1) ||
1042 (plltype == SSB_PLLTYPE_3))
1043 m2 += SSB_CHIPCO_CLK_F5_BIAS;
1045 m2 = clkfactor_f6_resolve(m2);
1046 m3 = clkfactor_f6_resolve(m3);
1049 case SSB_CHIPCO_CLK_MC_BYPASS:
1051 case SSB_CHIPCO_CLK_MC_M1:
1052 return (clock / m1);
1053 case SSB_CHIPCO_CLK_MC_M1M2:
1054 return (clock / (m1 * m2));
1055 case SSB_CHIPCO_CLK_MC_M1M2M3:
1056 return (clock / (m1 * m2 * m3));
1057 case SSB_CHIPCO_CLK_MC_M1M3:
1058 return (clock / (m1 * m3));
1062 m1 += SSB_CHIPCO_CLK_T2_BIAS;
1063 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1064 m3 += SSB_CHIPCO_CLK_T2_BIAS;
1065 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1066 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1067 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1069 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1071 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1073 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1082 /* Get the current speed the backplane is running at */
1083 u32 ssb_clockspeed(struct ssb_bus *bus)
1087 u32 clkctl_n, clkctl_m;
1089 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1090 return ssb_pmu_get_controlclock(&bus->chipco);
1092 if (ssb_extif_available(&bus->extif))
1093 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1094 &clkctl_n, &clkctl_m);
1095 else if (bus->chipco.dev)
1096 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1097 &clkctl_n, &clkctl_m);
1101 if (bus->chip_id == 0x5365) {
1104 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1105 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1111 EXPORT_SYMBOL(ssb_clockspeed);
1113 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1115 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1117 /* The REJECT bit seems to be different for Backplane rev 2.3 */
1119 case SSB_IDLOW_SSBREV_22:
1120 case SSB_IDLOW_SSBREV_24:
1121 case SSB_IDLOW_SSBREV_26:
1122 return SSB_TMSLOW_REJECT;
1123 case SSB_IDLOW_SSBREV_23:
1124 return SSB_TMSLOW_REJECT_23;
1125 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1126 case SSB_IDLOW_SSBREV_27: /* same here */
1127 return SSB_TMSLOW_REJECT; /* this is a guess */
1129 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1131 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1134 int ssb_device_is_enabled(struct ssb_device *dev)
1139 reject = ssb_tmslow_reject_bitmask(dev);
1140 val = ssb_read32(dev, SSB_TMSLOW);
1141 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1143 return (val == SSB_TMSLOW_CLOCK);
1145 EXPORT_SYMBOL(ssb_device_is_enabled);
1147 static void ssb_flush_tmslow(struct ssb_device *dev)
1149 /* Make _really_ sure the device has finished the TMSLOW
1150 * register write transaction, as we risk running into
1151 * a machine check exception otherwise.
1152 * Do this by reading the register back to commit the
1153 * PCI write and delay an additional usec for the device
1154 * to react to the change. */
1155 ssb_read32(dev, SSB_TMSLOW);
1159 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1163 ssb_device_disable(dev, core_specific_flags);
1164 ssb_write32(dev, SSB_TMSLOW,
1165 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1166 SSB_TMSLOW_FGC | core_specific_flags);
1167 ssb_flush_tmslow(dev);
1169 /* Clear SERR if set. This is a hw bug workaround. */
1170 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1171 ssb_write32(dev, SSB_TMSHIGH, 0);
1173 val = ssb_read32(dev, SSB_IMSTATE);
1174 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1175 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1176 ssb_write32(dev, SSB_IMSTATE, val);
1179 ssb_write32(dev, SSB_TMSLOW,
1180 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1181 core_specific_flags);
1182 ssb_flush_tmslow(dev);
1184 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1185 core_specific_flags);
1186 ssb_flush_tmslow(dev);
1188 EXPORT_SYMBOL(ssb_device_enable);
1190 /* Wait for bitmask in a register to get set or cleared.
1191 * timeout is in units of ten-microseconds */
1192 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1193 int timeout, int set)
1198 for (i = 0; i < timeout; i++) {
1199 val = ssb_read32(dev, reg);
1201 if ((val & bitmask) == bitmask)
1204 if (!(val & bitmask))
1209 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1210 "register %04X to %s.\n",
1211 bitmask, reg, (set ? "set" : "clear"));
1216 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1220 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1223 reject = ssb_tmslow_reject_bitmask(dev);
1225 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1226 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1227 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1228 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1230 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1231 val = ssb_read32(dev, SSB_IMSTATE);
1232 val |= SSB_IMSTATE_REJECT;
1233 ssb_write32(dev, SSB_IMSTATE, val);
1234 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1238 ssb_write32(dev, SSB_TMSLOW,
1239 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1240 reject | SSB_TMSLOW_RESET |
1241 core_specific_flags);
1242 ssb_flush_tmslow(dev);
1244 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1245 val = ssb_read32(dev, SSB_IMSTATE);
1246 val &= ~SSB_IMSTATE_REJECT;
1247 ssb_write32(dev, SSB_IMSTATE, val);
1251 ssb_write32(dev, SSB_TMSLOW,
1252 reject | SSB_TMSLOW_RESET |
1253 core_specific_flags);
1254 ssb_flush_tmslow(dev);
1256 EXPORT_SYMBOL(ssb_device_disable);
1258 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1259 static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1261 u16 chip_id = dev->bus->chip_id;
1263 if (dev->id.coreid == SSB_DEV_80211) {
1264 return (chip_id == 0x4322 || chip_id == 43221 ||
1265 chip_id == 43231 || chip_id == 43222);
1271 u32 ssb_dma_translation(struct ssb_device *dev)
1273 switch (dev->bus->bustype) {
1274 case SSB_BUSTYPE_SSB:
1276 case SSB_BUSTYPE_PCI:
1277 if (pci_is_pcie(dev->bus->host_pci) &&
1278 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1279 return SSB_PCIE_DMA_H32;
1281 if (ssb_dma_translation_special_bit(dev))
1282 return SSB_PCIE_DMA_H32;
1287 __ssb_dma_not_implemented(dev);
1291 EXPORT_SYMBOL(ssb_dma_translation);
1293 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1295 struct ssb_chipcommon *cc;
1298 /* On buses where more than one core may be working
1299 * at a time, we must not powerdown stuff if there are
1300 * still cores that may want to run. */
1301 if (bus->bustype == SSB_BUSTYPE_SSB)
1308 if (cc->dev->id.revision < 5)
1311 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1312 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1316 #ifdef CONFIG_SSB_DEBUG
1317 bus->powered_up = 0;
1321 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1324 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1326 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1329 enum ssb_clkmode mode;
1331 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1335 #ifdef CONFIG_SSB_DEBUG
1336 bus->powered_up = 1;
1339 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1340 ssb_chipco_set_clockmode(&bus->chipco, mode);
1344 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1347 EXPORT_SYMBOL(ssb_bus_powerup);
1349 static void ssb_broadcast_value(struct ssb_device *dev,
1350 u32 address, u32 data)
1352 #ifdef CONFIG_SSB_DRIVER_PCICORE
1353 /* This is used for both, PCI and ChipCommon core, so be careful. */
1354 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1355 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1358 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1359 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1360 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1361 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1364 void ssb_commit_settings(struct ssb_bus *bus)
1366 struct ssb_device *dev;
1368 #ifdef CONFIG_SSB_DRIVER_PCICORE
1369 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1371 dev = bus->chipco.dev;
1375 /* This forces an update of the cached registers. */
1376 ssb_broadcast_value(dev, 0xFD8, 0);
1378 EXPORT_SYMBOL(ssb_commit_settings);
1380 u32 ssb_admatch_base(u32 adm)
1384 switch (adm & SSB_ADM_TYPE) {
1386 base = (adm & SSB_ADM_BASE0);
1389 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1390 base = (adm & SSB_ADM_BASE1);
1393 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1394 base = (adm & SSB_ADM_BASE2);
1402 EXPORT_SYMBOL(ssb_admatch_base);
1404 u32 ssb_admatch_size(u32 adm)
1408 switch (adm & SSB_ADM_TYPE) {
1410 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1413 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1414 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1417 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1418 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1423 size = (1 << (size + 1));
1427 EXPORT_SYMBOL(ssb_admatch_size);
1429 static int __init ssb_modinit(void)
1433 /* See the comment at the ssb_is_early_boot definition */
1434 ssb_is_early_boot = 0;
1435 err = bus_register(&ssb_bustype);
1439 /* Maybe we already registered some buses at early boot.
1440 * Check for this and attach them
1443 err = ssb_attach_queued_buses();
1446 bus_unregister(&ssb_bustype);
1450 err = b43_pci_ssb_bridge_init();
1452 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1453 "initialization failed\n");
1454 /* don't fail SSB init because of this */
1457 err = ssb_gige_init();
1459 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1460 "driver initialization failed\n");
1461 /* don't fail SSB init because of this */
1467 /* ssb must be initialized after PCI but before the ssb drivers.
1468 * That means we must use some initcall between subsys_initcall
1469 * and device_initcall. */
1470 fs_initcall(ssb_modinit);
1472 static void __exit ssb_modexit(void)
1475 b43_pci_ssb_bridge_exit();
1476 bus_unregister(&ssb_bustype);
1478 module_exit(ssb_modexit)