1 //------------------------------------------------------------------------------
2 // <copyright file="common_drv.c" company="Atheros">
3 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 //------------------------------------------------------------------------------
20 //==============================================================================
21 // Author(s): ="Atheros"
22 //==============================================================================
28 #include "AR6002/hw2.0/hw/mbox_host_reg.h"
29 #include "AR6002/hw2.0/hw/apb_map.h"
30 #include "AR6002/hw2.0/hw/si_reg.h"
31 #include "AR6002/hw2.0/hw/gpio_reg.h"
32 #include "AR6002/hw2.0/hw/rtc_reg.h"
33 #include "AR6002/hw2.0/hw/vmc_reg.h"
34 #include "AR6002/hw2.0/hw/mbox_reg.h"
37 #include "targaddrs.h"
43 #include "common_drv.h"
44 #define ATH_MODULE_NAME misc
46 #include "ar6000_diag.h"
48 static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL;
49 static A_MUTEX_T g_ModuleListLock;
50 static bool g_ModuleDebugInit = false;
52 #ifdef ATH_DEBUG_MODULE
54 ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc,
56 "Common and misc APIs",
57 ATH_DEBUG_MASK_DEFAULTS,
63 #define HOST_INTEREST_ITEM_ADDRESS(target, item) \
64 ((((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
65 (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
68 #define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080
69 #define AR6002_LOCAL_COUNT_ADDRESS 0x00018080
70 #define AR6003_LOCAL_COUNT_ADDRESS 0x00018080
71 #define CPU_DBG_SEL_ADDRESS 0x00000483
72 #define CPU_DBG_ADDRESS 0x00000484
74 static u8 custDataAR6002[AR6002_CUST_DATA_SIZE];
75 static u8 custDataAR6003[AR6003_CUST_DATA_SIZE];
77 /* Compile the 4BYTE version of the window register setup routine,
78 * This mitigates host interconnect issues with non-4byte aligned bus requests, some
79 * interconnects use bus adapters that impose strict limitations.
80 * Since diag window access is not intended for performance critical operations, the 4byte mode should
81 * be satisfactory even though it generates 4X the bus activity. */
83 #ifdef USE_4BYTE_REGISTER_ACCESS
85 /* set the window address register (using 4-byte register access ). */
86 int ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
92 /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
93 * last to initiate the access cycle */
95 for (i = 1; i <= 3; i++) {
96 /* fill the buffer with the address byte value we want to hit 4 times*/
97 addrValue[0] = ((u8 *)&Address)[i];
98 addrValue[1] = addrValue[0];
99 addrValue[2] = addrValue[0];
100 addrValue[3] = addrValue[0];
102 /* hit each byte of the register address with a 4-byte write operation to the same address,
103 * this is a harmless operation */
104 status = HIFReadWrite(hifDevice,
108 HIF_WR_SYNC_BYTE_FIX,
110 if (status != A_OK) {
115 if (status != A_OK) {
116 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
117 Address, RegisterAddr));
121 /* write the address register again, this time write the whole 4-byte value.
122 * The effect here is that the LSB write causes the cycle to start, the extra
123 * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
124 status = HIFReadWrite(hifDevice,
126 (A_UCHAR *)(&Address),
128 HIF_WR_SYNC_BYTE_INC,
131 if (status != A_OK) {
132 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
133 Address, RegisterAddr));
146 /* set the window address register */
147 int ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
151 /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
152 * last to initiate the access cycle */
153 status = HIFReadWrite(hifDevice,
154 RegisterAddr+1, /* write upper 3 bytes */
155 ((A_UCHAR *)(&Address))+1,
157 HIF_WR_SYNC_BYTE_INC,
160 if (status != A_OK) {
161 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
162 RegisterAddr, Address));
166 /* write the LSB of the register, this initiates the operation */
167 status = HIFReadWrite(hifDevice,
169 (A_UCHAR *)(&Address),
171 HIF_WR_SYNC_BYTE_INC,
174 if (status != A_OK) {
175 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
176 RegisterAddr, Address));
186 * Read from the AR6000 through its diagnostic window.
187 * No cooperation from the Target is required for this.
190 ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
194 /* set window register to start read cycle */
195 status = ar6000_SetAddressWindowRegister(hifDevice,
196 WINDOW_READ_ADDR_ADDRESS,
199 if (status != A_OK) {
204 status = HIFReadWrite(hifDevice,
208 HIF_RD_SYNC_BYTE_INC,
210 if (status != A_OK) {
211 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
220 * Write to the AR6000 through its diagnostic window.
221 * No cooperation from the Target is required for this.
224 ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
229 status = HIFReadWrite(hifDevice,
233 HIF_WR_SYNC_BYTE_INC,
235 if (status != A_OK) {
236 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
240 /* set window register, which starts the write cycle */
241 return ar6000_SetAddressWindowRegister(hifDevice,
242 WINDOW_WRITE_ADDR_ADDRESS,
247 ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
248 A_UCHAR *data, A_UINT32 length)
253 for (count = 0; count < length; count += 4, address += 4) {
254 if ((status = ar6000_ReadRegDiag(hifDevice, &address,
255 (A_UINT32 *)&data[count])) != A_OK)
265 ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
266 A_UCHAR *data, A_UINT32 length)
271 for (count = 0; count < length; count += 4, address += 4) {
272 if ((status = ar6000_WriteRegDiag(hifDevice, &address,
273 (A_UINT32 *)&data[count])) != A_OK)
283 ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval)
287 A_UCHAR register_selection[4];
289 register_selection[0] = register_selection[1] = register_selection[2] = register_selection[3] = (regsel & 0xff);
290 status = HIFReadWrite(hifDevice,
294 HIF_WR_SYNC_BYTE_FIX,
297 if (status != A_OK) {
298 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write CPU_DBG_SEL (%d)\n", regsel));
302 status = HIFReadWrite(hifDevice,
306 HIF_RD_SYNC_BYTE_INC,
308 if (status != A_OK) {
309 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from CPU_DBG_ADDRESS\n"));
313 *regval = vals[0]<<0 | vals[1]<<8 | vals[2]<<16 | vals[3]<<24;
319 ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs)
324 for (i=0; i<AR6003_FETCH_TARG_REGS_COUNT; i++) {
326 (void)ar6k_ReadTargetRegister(hifDevice, i, &val);
333 _do_write_diag(HIF_DEVICE *hifDevice, A_UINT32 addr, A_UINT32 value)
337 status = ar6000_WriteRegDiag(hifDevice, &addr, &value);
340 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
349 * Delay up to wait_msecs millisecs to allow Target to enter BMI phase,
350 * which is a good sign that it's alive and well. This is used after
351 * explicitly forcing the Target to reset.
353 * The wait_msecs time should be sufficiently long to cover any reasonable
354 * boot-time delay. For instance, AR6001 firmware allow one second for a
355 * low frequency crystal to settle before it calibrates the refclk frequency.
357 * TBD: Might want to add special handling for AR6K_OPTION_BMI_DISABLE.
361 _delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 TargetType)
369 /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */
370 if (TargetType == TARGET_TYPE_AR6002) {
371 address = AR6002_LOCAL_COUNT_ADDRESS;
372 } else if (TargetType == TARGET_TYPE_AR6003) {
373 address = AR6003_LOCAL_COUNT_ADDRESS;
378 for (i=0; actual_wait < wait_msecs; i++) {
385 if (ar6000_ReadRegDiag(hifDevice, &address, &data) != A_OK) {
390 /* No need to wait longer -- we have a BMI credit */
394 return A_ERROR; /* timed out */
398 #define AR6001_RESET_CONTROL_ADDRESS 0x0C000000
399 #define AR6002_RESET_CONTROL_ADDRESS 0x00004000
400 #define AR6003_RESET_CONTROL_ADDRESS 0x00004000
402 int ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType, bool waitForCompletion, bool coldReset)
410 // address = RESET_CONTROL_ADDRESS;
413 data = RESET_CONTROL_COLD_RST_MASK;
416 data = RESET_CONTROL_MBOX_RST_MASK;
419 /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
420 if (TargetType == TARGET_TYPE_AR6002) {
421 address = AR6002_RESET_CONTROL_ADDRESS;
422 } else if (TargetType == TARGET_TYPE_AR6003) {
423 address = AR6003_RESET_CONTROL_ADDRESS;
429 status = ar6000_WriteRegDiag(hifDevice, &address, &data);
435 if (!waitForCompletion) {
440 /* Up to 2 second delay to allow things to settle down */
441 (void)_delay_until_target_alive(hifDevice, 2000, TargetType);
444 * Read back the RESET CAUSE register to ensure that the cold reset
448 // address = RESET_CAUSE_ADDRESS;
449 /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
450 if (TargetType == TARGET_TYPE_AR6002) {
451 address = 0x000040C0;
452 } else if (TargetType == TARGET_TYPE_AR6003) {
453 address = 0x000040C0;
459 status = ar6000_ReadRegDiag(hifDevice, &address, &data);
465 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
466 data &= RESET_CAUSE_LAST_MASK;
468 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
476 AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
482 /* This should be called in BMI phase after firmware is downloaded */
484 ar6000_copy_cust_data_from_target(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
486 A_UINT32 eepHeaderAddr;
487 u8 AR6003CustDataShadow[AR6003_CUST_DATA_SIZE+4];
490 if (BMIReadMemory(hifDevice,
491 HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_board_data),
492 (A_UCHAR *)&eepHeaderAddr,
495 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadMemory for reading board data address failed \n"));
499 if (TargetType == TARGET_TYPE_AR6003) {
500 eepHeaderAddr += 36; /* AR6003 customer data section offset is 37 */
502 for (i=0; i<AR6003_CUST_DATA_SIZE+4; i+=4){
503 if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (A_UINT32 *)&AR6003CustDataShadow[i])!= A_OK) {
504 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
510 memcpy(custDataAR6003, AR6003CustDataShadow+1, AR6003_CUST_DATA_SIZE);
513 if (TargetType == TARGET_TYPE_AR6002) {
514 eepHeaderAddr += 64; /* AR6002 customer data sectioin offset is 64 */
516 for (i=0; i<AR6002_CUST_DATA_SIZE; i+=4){
517 if (BMIReadSOCRegister(hifDevice, eepHeaderAddr, (A_UINT32 *)&custDataAR6002[i])!= A_OK) {
518 AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMIReadSOCRegister () failed \n"));
528 /* This is the function to call when need to use the cust data */
529 u8 *ar6000_get_cust_data_buffer(A_UINT32 TargetType)
531 if (TargetType == TARGET_TYPE_AR6003)
532 return custDataAR6003;
534 if (TargetType == TARGET_TYPE_AR6002)
535 return custDataAR6002;
540 #define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR600x_regdump.h */
541 #define REG_DUMP_COUNT_AR6002 60
542 #define REG_DUMP_COUNT_AR6003 60
543 #define REGISTER_DUMP_LEN_MAX 60
544 #if REG_DUMP_COUNT_AR6001 > REGISTER_DUMP_LEN_MAX
545 #error "REG_DUMP_COUNT_AR6001 too large"
547 #if REG_DUMP_COUNT_AR6002 > REGISTER_DUMP_LEN_MAX
548 #error "REG_DUMP_COUNT_AR6002 too large"
550 #if REG_DUMP_COUNT_AR6003 > REGISTER_DUMP_LEN_MAX
551 #error "REG_DUMP_COUNT_AR6003 too large"
555 void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
558 A_UINT32 regDumpArea = 0;
560 A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
561 A_UINT32 regDumpCount = 0;
566 /* the reg dump pointer is copied to the host interest area */
567 address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
568 address = TARG_VTOP(TargetType, address);
570 if (TargetType == TARGET_TYPE_AR6002) {
571 regDumpCount = REG_DUMP_COUNT_AR6002;
572 } else if (TargetType == TARGET_TYPE_AR6003) {
573 regDumpCount = REG_DUMP_COUNT_AR6003;
578 /* read RAM location through diagnostic window */
579 status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea);
582 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
586 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
588 if (regDumpArea == 0) {
593 regDumpArea = TARG_VTOP(TargetType, regDumpArea);
595 /* fetch register dump data */
596 status = ar6000_ReadDataDiag(hifDevice,
598 (A_UCHAR *)®DumpValues[0],
599 regDumpCount * (sizeof(A_UINT32)));
602 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
605 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
607 for (i = 0; i < regDumpCount; i++) {
608 //ATHR_DISPLAY_MSG (_T(" %d : 0x%8.8X \n"), i, regDumpValues[i]);
609 AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i]));
613 * For Every logPrintf() Open the File so that in case of Crashes
614 * We will have until the Last Message Flushed on to the File
615 * So use logPrintf Sparingly..!!
617 tgtassertPrintf (ATH_DEBUG_TRC," %d: 0x%8.8X \n",i, regDumpValues[i]);
625 /* set HTC/Mbox operational parameters, this can only be called when the target is in the
627 int ar6000_set_htc_params(HIF_DEVICE *hifDevice,
629 A_UINT32 MboxIsrYieldValue,
630 u8 HtcControlBuffers)
633 A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
636 /* get the block sizes */
637 status = HIFConfigureDevice(hifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
638 blocksizes, sizeof(blocksizes));
641 AR_DEBUG_PRINTF(ATH_LOG_ERR,("Failed to get block size info from HIF layer...\n"));
644 /* note: we actually get the block size for mailbox 1, for SDIO the block
645 * size on mailbox 0 is artificially set to 1 */
646 /* must be a power of 2 */
647 A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
649 if (HtcControlBuffers != 0) {
650 /* set override for number of control buffers to use */
651 blocksizes[1] |= ((A_UINT32)HtcControlBuffers) << 16;
654 /* set the host interest area for the block size */
655 status = BMIWriteMemory(hifDevice,
656 HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz),
657 (A_UCHAR *)&blocksizes[1],
661 AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for IO block size failed \n"));
665 AR_DEBUG_PRINTF(ATH_LOG_INF,("Block Size Set: %d (target address:0x%X)\n",
666 blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_io_block_sz)));
668 if (MboxIsrYieldValue != 0) {
669 /* set the host interest area for the mbox ISR yield limit */
670 status = BMIWriteMemory(hifDevice,
671 HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_mbox_isr_yield_limit),
672 (A_UCHAR *)&MboxIsrYieldValue,
676 AR_DEBUG_PRINTF(ATH_LOG_ERR,("BMIWriteMemory for yield limit failed \n"));
687 static int prepare_ar6002(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
696 static int prepare_ar6003(HIF_DEVICE *hifDevice, A_UINT32 TargetVersion)
705 /* this function assumes the caller has already initialized the BMI APIs */
706 int ar6000_prepare_target(HIF_DEVICE *hifDevice,
708 A_UINT32 TargetVersion)
710 if (TargetType == TARGET_TYPE_AR6002) {
711 /* do any preparations for AR6002 devices */
712 return prepare_ar6002(hifDevice,TargetVersion);
713 } else if (TargetType == TARGET_TYPE_AR6003) {
714 return prepare_ar6003(hifDevice,TargetVersion);
720 #if defined(CONFIG_AR6002_REV1_FORCE_HOST)
722 * Call this function just before the call to BMIInit
723 * in order to force* AR6002 rev 1.x firmware to detect a Host.
724 * THIS IS FOR USE ONLY WITH AR6002 REV 1.x.
725 * TBDXXX: Remove this function when REV 1.x is desupported.
728 ar6002_REV1_reset_force_host (HIF_DEVICE *hifDevice)
735 struct forceROM_s *ForceROM;
741 /* Force AR6002 REV1.x to recognize Host presence.
743 * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0
744 * so that this workaround functions with AR6002.war1.sh. We
745 * could fold that entire workaround into this one, but it's not
746 * worth the effort at this point. This workaround cannot be
747 * merged into the other workaround because this must be done
751 static struct forceROM_s ForceROM_NEW[] = {
752 {0x52df80, 0x20f31c07},
753 {0x52df84, 0x92374420},
754 {0x52df88, 0x1d120c03},
755 {0x52df8c, 0xff8216f0},
756 {0x52df90, 0xf01d120c},
757 {0x52df94, 0x81004136},
758 {0x52df98, 0xbc9100bd},
759 {0x52df9c, 0x00bba100},
761 {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */
762 {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380},
763 {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000},
764 {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001},
766 {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */
768 {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
771 address = 0x004ed4b0; /* REV1 target software ID is stored here */
772 status = ar6000_ReadRegDiag(hifDevice, &address, &data);
773 if (status || (data != AR6002_VERSION_REV1)) {
774 return A_ERROR; /* Not AR6002 REV1 */
777 ForceROM = ForceROM_NEW;
778 szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
780 ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n"));
781 for (i = 0; i < szForceROM; i++)
783 if (ar6000_WriteRegDiag(hifDevice,
785 &ForceROM[i].data) != A_OK)
787 ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n"));
797 #endif /* CONFIG_AR6002_REV1_FORCE_HOST */
799 void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
802 char byteOffsetStr[10];
804 A_UINT16 offset, count, byteOffset;
806 A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length, pDescription);
811 for(i = 0; i < length; i++) {
812 A_SPRINTF(stream + offset, "%2.2X ", buffer[i]);
819 A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
820 A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
821 A_MEMZERO(stream, 60);
827 A_SPRINTF(byteOffsetStr,"%4.4X",byteOffset);
828 A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
831 A_PRINTF("<------------------------------------------------->\n");
834 void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
837 ATH_DEBUG_MASK_DESCRIPTION *pDesc;
843 pDesc = pInfo->pMaskDescriptions;
845 A_PRINTF("========================================================\n\n");
846 A_PRINTF("Module Debug Info => Name : %s \n", pInfo->ModuleName);
847 A_PRINTF(" => Descr. : %s \n", pInfo->ModuleDescription);
848 A_PRINTF("\n Current mask => 0x%8.8X \n", pInfo->CurrentMask);
849 A_PRINTF("\n Avail. Debug Masks :\n\n");
851 for (i = 0; i < pInfo->MaxDescriptions; i++,pDesc++) {
852 A_PRINTF(" => 0x%8.8X -- %s \n", pDesc->Mask, pDesc->Description);
856 A_PRINTF(" => * none defined * \n");
859 A_PRINTF("\n Standard Debug Masks :\n\n");
860 /* print standard masks */
861 A_PRINTF(" => 0x%8.8X -- Errors \n", ATH_DEBUG_ERR);
862 A_PRINTF(" => 0x%8.8X -- Warnings \n", ATH_DEBUG_WARN);
863 A_PRINTF(" => 0x%8.8X -- Informational \n", ATH_DEBUG_INFO);
864 A_PRINTF(" => 0x%8.8X -- Tracing \n", ATH_DEBUG_TRC);
865 A_PRINTF("\n========================================================\n");
870 static ATH_DEBUG_MODULE_DBG_INFO *FindModule(char *module_name)
872 ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
874 if (!g_ModuleDebugInit) {
878 while (pInfo != NULL) {
879 /* TODO: need to use something other than strlen */
880 if (A_MEMCMP(pInfo->ModuleName,module_name,strlen(module_name)) == 0) {
883 pInfo = pInfo->pNext;
890 void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo)
892 if (!g_ModuleDebugInit) {
896 A_MUTEX_LOCK(&g_ModuleListLock);
898 if (!(pInfo->Flags & ATH_DEBUG_INFO_FLAGS_REGISTERED)) {
899 if (g_pModuleInfoHead == NULL) {
900 g_pModuleInfoHead = pInfo;
902 pInfo->pNext = g_pModuleInfoHead;
903 g_pModuleInfoHead = pInfo;
905 pInfo->Flags |= ATH_DEBUG_INFO_FLAGS_REGISTERED;
908 A_MUTEX_UNLOCK(&g_ModuleListLock);
911 void a_dump_module_debug_info_by_name(char *module_name)
913 ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
915 if (!g_ModuleDebugInit) {
919 if (A_MEMCMP(module_name,"all",3) == 0) {
921 while (pInfo != NULL) {
922 a_dump_module_debug_info(pInfo);
923 pInfo = pInfo->pNext;
928 pInfo = FindModule(module_name);
931 a_dump_module_debug_info(pInfo);
936 int a_get_module_mask(char *module_name, A_UINT32 *pMask)
938 ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
944 *pMask = pInfo->CurrentMask;
948 int a_set_module_mask(char *module_name, A_UINT32 Mask)
950 ATH_DEBUG_MODULE_DBG_INFO *pInfo = FindModule(module_name);
956 pInfo->CurrentMask = Mask;
957 A_PRINTF("Module %s, new mask: 0x%8.8X \n",module_name,pInfo->CurrentMask);
962 void a_module_debug_support_init(void)
964 if (g_ModuleDebugInit) {
967 A_MUTEX_INIT(&g_ModuleListLock);
968 g_pModuleInfoHead = NULL;
969 g_ModuleDebugInit = true;
970 A_REGISTER_MODULE_DEBUG_INFO(misc);
973 void a_module_debug_support_cleanup(void)
975 ATH_DEBUG_MODULE_DBG_INFO *pInfo = g_pModuleInfoHead;
976 ATH_DEBUG_MODULE_DBG_INFO *pCur;
978 if (!g_ModuleDebugInit) {
982 g_ModuleDebugInit = false;
984 A_MUTEX_LOCK(&g_ModuleListLock);
986 while (pInfo != NULL) {
988 pInfo = pInfo->pNext;
990 /* clear registered flag */
991 pCur->Flags &= ~ATH_DEBUG_INFO_FLAGS_REGISTERED;
994 A_MUTEX_UNLOCK(&g_ModuleListLock);
996 A_MUTEX_DELETE(&g_ModuleListLock);
997 g_pModuleInfoHead = NULL;
1000 /* can only be called during bmi init stage */
1001 int ar6000_set_hci_bridge_flags(HIF_DEVICE *hifDevice,
1002 A_UINT32 TargetType,
1009 if (TargetType != TARGET_TYPE_AR6003) {
1010 AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("Target Type:%d, does not support HCI bridging! \n",
1015 /* set hci bridge flags */
1016 status = BMIWriteMemory(hifDevice,
1017 HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_bridge_flags),