drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include <proto/802.11.h>
  25 #include <osl.h>
  26 #include <bcmdefs.h>
  27 #include <bcmdevs.h>
  28 #include <bcmwifi.h>
  29 #include <siutils.h>
  30 #include <bcmsrom.h>
  31 #include <bcmotp.h>
  32 #include <bcmutils.h>
  33 #include <wlioctl.h>
  34 #include <sbconfig.h>
  35 #include <sbchipc.h>
  36 #include <pcicfg.h>
  37 #include <sbhnddma.h>
  38 #include <hnddma.h>
  39 #include <hndpmu.h>
  40
  41 #include "wlc_types.h"
  42 #include "d11.h"
  43 #include "wlc_cfg.h"
  44 #include "wlc_rate.h"
  45 #include "wlc_scb.h"
  46 #include "wlc_pub.h"
  47 #include "wlc_key.h"
  48 #include "wlc_phy_shim.h"
  49 #include "phy/wlc_phy_hal.h"
  50 #include "wlc_channel.h"
  51 #include "wlc_bsscfg.h"
  52 #include "wlc_mac80211.h"
  53 #include "wl_export.h"
  54 #include "wl_ucode.h"
  55 #include "d11ucode_ext.h"
  56 #include "wlc_antsel.h"
  57 #include "pcie_core.h"
  58 #include "wlc_alloc.h"
  59 #include "wl_dbg.h"
  60 #include "wlc_bmac.h"
  61
  62 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  63
  64 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  65 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  66 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  67 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  68
  69 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  70
  71 #ifndef BMAC_DUP_TO_REMOVE
  72 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  73
  74 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  75
  76 #endif                          /* BMAC_DUP_TO_REMOVE */
  77
  78 #define DMAREG(wlc_hw, direction, fifonum) \
  79         ((direction == DMA_TX) ? \
  80                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  81                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  82
  83 /*
  84  * The following table lists the buffer memory allocated to xmt fifos in HW.
  85  * the size is in units of 256bytes(one block), total size is HW dependent
  86  * ucode has default fifo partition, sw can overwrite if necessary
  87  *
  88  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  89  * the twiki is updated before making changes.
  90  */
  91
  92 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  93
  94 static u16 xmtfifo_sz[][NFIFO] = {
  95         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  96         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  97         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  98         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  99         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 100 };
 101
 102 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 103 static void wlc_coreinit(struct wlc_info *wlc);
 104
 105 /* used by wlc_wakeucode_init() */
 106 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits);
 107 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 108                             const uint nbytes);
 109 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 110 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 111
 112 /* used by wlc_dpc() */
 113 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 114                                 u32 s2);
 115 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 116 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 117
 118 /* used by wlc_down() */
 119 static void wlc_flushqueues(struct wlc_info *wlc);
 120
 121 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 122 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 123 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 124 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
 125                                        uint tx_fifo);
 126 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 127 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
 128
 129 /* Low Level Prototypes */
 130 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
 131 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
 132 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
 133 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 134                                    u32 sel);
 135 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 136                                   u16 v, u32 sel);
 137 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
 138 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 139 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 140 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 141 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 142 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 143 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
 144 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 145 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 146 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 147 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
 148 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 149 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 150 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 151 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 152 static void wlc_gpio_init(struct wlc_info *wlc);
 153 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 154                                       int len);
 155 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 156                                       int len);
 157 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 158 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 159 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 160                              chanspec_t chanspec);
 161 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 162                                         bool shortslot);
 163 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 164 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 165                                              u8 rate);
 166
 167 /* === Low Level functions === */
 168
 169 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 170 {
 171         wlc_hw->shortslot = shortslot;
 172
 173         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 174                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 175                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 176                 wlc_enable_mac(wlc_hw->wlc);
 177         }
 178 }
 179
 180 /*
 181  * Update the slot timing for standard 11b/g (20us slots)
 182  * or shortslot 11g (9us slots)
 183  * The PSM needs to be suspended for this call.
 184  */
 185 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 186                                         bool shortslot)
 187 {
 188         struct osl_info *osh;
 189         d11regs_t *regs;
 190
 191         osh = wlc_hw->osh;
 192         regs = wlc_hw->regs;
 193
 194         if (shortslot) {
 195                 /* 11g short slot: 11a timing */
 196                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 197                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 198         } else {
 199                 /* 11g long slot: 11b timing */
 200                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 201                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 202         }
 203 }
 204
 205 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 206 {
 207         /* init microcode host flags */
 208         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 209
 210         /* do band-specific ucode IHR, SHM, and SCR inits */
 211         if (D11REV_IS(wlc_hw->corerev, 23)) {
 212                 if (WLCISNPHY(wlc_hw->band)) {
 213                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 214                 } else {
 215                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 216                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 217                 }
 218         } else {
 219                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 220                         if (WLCISLCNPHY(wlc_hw->band)) {
 221                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 222                         } else
 223                                 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 224                                          __func__, wlc_hw->unit,
 225                                          wlc_hw->corerev);
 226                 } else {
 227                         WL_ERROR("%s: wl%d: unsupported corerev %d\n",
 228                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 229                 }
 230         }
 231 }
 232
 233 /* switch to new band but leave it inactive */
 234 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 235 {
 236         struct wlc_hw_info *wlc_hw = wlc->hw;
 237         u32 macintmask;
 238
 239         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 240
 241         ASSERT(bandunit != wlc_hw->band->bandunit);
 242         ASSERT(si_iscoreup(wlc_hw->sih));
 243         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 244                0);
 245
 246         /* disable interrupts */
 247         macintmask = wl_intrsoff(wlc->wl);
 248
 249         /* radio off */
 250         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 251
 252         ASSERT(wlc_hw->clk);
 253
 254         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 255
 256         wlc_setxband(wlc_hw, bandunit);
 257
 258         return macintmask;
 259 }
 260
 261 /* Process received frames */
 262 /*
 263  * Return true if more frames need to be processed. false otherwise.
 264  * Param 'bound' indicates max. # frames to process before break out.
 265  */
 266 static bool BCMFASTPATH
 267 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 268 {
 269         struct sk_buff *p;
 270         struct sk_buff *head = NULL;
 271         struct sk_buff *tail = NULL;
 272         uint n = 0;
 273         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 274         u32 tsf_h, tsf_l;
 275         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 276
 277         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 278         /* gather received frames */
 279         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 280
 281                 if (!tail)
 282                         head = tail = p;
 283                 else {
 284                         tail->prev = p;
 285                         tail = p;
 286                 }
 287
 288                 /* !give others some time to run! */
 289                 if (++n >= bound_limit)
 290                         break;
 291         }
 292
 293         /* get the TSF REG reading */
 294         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 295
 296         /* post more rbufs */
 297         dma_rxfill(wlc_hw->di[fifo]);
 298
 299         /* process each frame */
 300         while ((p = head) != NULL) {
 301                 head = head->prev;
 302                 p->prev = NULL;
 303
 304                 /* record the tsf_l in wlc_rxd11hdr */
 305                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 306                 wlc_rxhdr->tsf_l = cpu_to_le32(tsf_l);
 307
 308                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 309                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 310
 311                 wlc_recv(wlc_hw->wlc, p);
 312         }
 313
 314         return n >= bound_limit;
 315 }
 316
 317 /* second-level interrupt processing
 318  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 319  *   Param 'bounded' indicates if applicable loops should be bounded.
 320  */
 321 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 322 {
 323         u32 macintstatus;
 324         struct wlc_hw_info *wlc_hw = wlc->hw;
 325         d11regs_t *regs = wlc_hw->regs;
 326         bool fatal = false;
 327
 328         if (DEVICEREMOVED(wlc)) {
 329                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
 330                 wl_down(wlc->wl);
 331                 return false;
 332         }
 333
 334         /* grab and clear the saved software intstatus bits */
 335         macintstatus = wlc->macintstatus;
 336         wlc->macintstatus = 0;
 337
 338         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 339                  wlc_hw->unit, macintstatus);
 340
 341         if (macintstatus & MI_PRQ) {
 342                 /* Process probe request FIFO */
 343                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 344         }
 345
 346         /* BCN template is available */
 347         /* ZZZ: Use AP_ACTIVE ? */
 348         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 349             && (macintstatus & MI_BCNTPL)) {
 350                 wlc_update_beacon(wlc);
 351         }
 352
 353         /* PMQ entry addition */
 354         if (macintstatus & MI_PMQ) {
 355         }
 356
 357         /* tx status */
 358         if (macintstatus & MI_TFS) {
 359                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 360                         wlc->macintstatus |= MI_TFS;
 361                 if (fatal) {
 362                         WL_ERROR("MI_TFS: fatal\n");
 363                         goto fatal;
 364                 }
 365         }
 366
 367         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 368                 wlc_tbtt(wlc, regs);
 369
 370         /* ATIM window end */
 371         if (macintstatus & MI_ATIMWINEND) {
 372                 WL_TRACE("wlc_isr: end of ATIM window\n");
 373
 374                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 375                 wlc->qvalid = 0;
 376         }
 377
 378         /* phy tx error */
 379         if (macintstatus & MI_PHYTXERR) {
 380                 wlc->pub->_cnt->txphyerr++;
 381         }
 382
 383         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 384         if (macintstatus & MI_DMAINT) {
 385                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 386                         wlc->macintstatus |= MI_DMAINT;
 387                 }
 388         }
 389
 390         /* TX FIFO suspend/flush completion */
 391         if (macintstatus & MI_TXSTOP) {
 392                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 393                         /*      WL_ERROR("dpc: fifo_suspend_comlete\n"); */
 394                 }
 395         }
 396
 397         /* noise sample collected */
 398         if (macintstatus & MI_BG_NOISE) {
 399                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 400         }
 401
 402         if (macintstatus & MI_GP0) {
 403                 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
 404                          wlc_hw->unit, wlc_hw->now);
 405
 406                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 407                                         __func__, wlc_hw->sih->chip,
 408                                         wlc_hw->sih->chiprev);
 409
 410                 wlc->pub->_cnt->psmwds++;
 411
 412                 /* big hammer */
 413                 wl_init(wlc->wl);
 414         }
 415
 416         /* gptimer timeout */
 417         if (macintstatus & MI_TO) {
 418                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 419         }
 420
 421         if (macintstatus & MI_RFDISABLE) {
 422                 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
 423
 424                 wlc->pub->_cnt->rfdisable++;
 425                 wl_rfkill_set_hw_state(wlc->wl);
 426         }
 427
 428         /* send any enq'd tx packets. Just makes sure to jump start tx */
 429         if (!pktq_empty(&wlc->active_queue->q))
 430                 wlc_send_q(wlc, wlc->active_queue);
 431
 432         ASSERT(wlc_ps_check(wlc));
 433
 434         /* make sure the bound indication and the implementation are in sync */
 435         ASSERT(bounded == true || wlc->macintstatus == 0);
 436
 437         /* it isn't done and needs to be resched if macintstatus is non-zero */
 438         return wlc->macintstatus != 0;
 439
 440  fatal:
 441         wl_init(wlc->wl);
 442         return wlc->macintstatus != 0;
 443 }
 444
 445 /* common low-level watchdog code */
 446 void wlc_bmac_watchdog(void *arg)
 447 {
 448         struct wlc_info *wlc = (struct wlc_info *) arg;
 449         struct wlc_hw_info *wlc_hw = wlc->hw;
 450
 451         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 452
 453         if (!wlc_hw->up)
 454                 return;
 455
 456         /* increment second count */
 457         wlc_hw->now++;
 458
 459         /* Check for FIFO error interrupts */
 460         wlc_bmac_fifoerrors(wlc_hw);
 461
 462         /* make sure RX dma has buffers */
 463         dma_rxfill(wlc->hw->di[RX_FIFO]);
 464
 465         wlc_phy_watchdog(wlc_hw->band->pi);
 466 }
 467
 468 void
 469 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 470                       bool mute, struct txpwr_limits *txpwr)
 471 {
 472         uint bandunit;
 473
 474         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 475                  wlc_hw->unit, chanspec);
 476
 477         wlc_hw->chanspec = chanspec;
 478
 479         /* Switch bands if necessary */
 480         if (NBANDS_HW(wlc_hw) > 1) {
 481                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 482                 if (wlc_hw->band->bandunit != bandunit) {
 483                         /* wlc_bmac_setband disables other bandunit,
 484                          *  use light band switch if not up yet
 485                          */
 486                         if (wlc_hw->up) {
 487                                 wlc_phy_chanspec_radio_set(wlc_hw->
 488                                                            bandstate[bandunit]->
 489                                                            pi, chanspec);
 490                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 491                         } else {
 492                                 wlc_setxband(wlc_hw, bandunit);
 493                         }
 494                 }
 495         }
 496
 497         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 498
 499         if (!wlc_hw->up) {
 500                 if (wlc_hw->clk)
 501                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 502                                                   chanspec);
 503                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 504         } else {
 505                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 506                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 507
 508                 /* Update muting of the channel */
 509                 wlc_bmac_mute(wlc_hw, mute, 0);
 510         }
 511 }
 512
 513 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 514 {
 515         state->machwcap = wlc_hw->machwcap;
 516
 517         return 0;
 518 }
 519
 520 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 521 {
 522         uint i;
 523         char name[8];
 524         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 525         u16 pio_mhf2 = 0;
 526         struct wlc_hw_info *wlc_hw = wlc->hw;
 527         uint unit = wlc_hw->unit;
 528         wlc_tunables_t *tune = wlc->pub->tunables;
 529
 530         /* name and offsets for dma_attach */
 531         snprintf(name, sizeof(name), "wl%d", unit);
 532
 533         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 534                 uint addrwidth;
 535                 int dma_attach_err = 0;
 536                 struct osl_info *osh = wlc_hw->osh;
 537
 538                 /* Find out the DMA addressing capability and let OS know
 539                  * All the channels within one DMA core have 'common-minimum' same
 540                  * capability
 541                  */
 542                 addrwidth =
 543                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 544
 545                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 546                         WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
 547                                  unit);
 548                         return false;
 549                 }
 550
 551                 /*
 552                  * FIFO 0
 553                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 554                  * RX: RX_FIFO (RX data packets)
 555                  */
 556                 ASSERT(TX_AC_BK_FIFO == 0);
 557                 ASSERT(RX_FIFO == 0);
 558                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 559                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 560                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 561                                            (wme ? tune->ntxd : 0), tune->nrxd,
 562                                            tune->rxbufsz, -1, tune->nrxbufpost,
 563                                            WL_HWRXOFF, &wl_msg_level);
 564                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 565
 566                 /*
 567                  * FIFO 1
 568                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 569                  *   (legacy) TX_DATA_FIFO (TX data packets)
 570                  * RX: UNUSED
 571                  */
 572                 ASSERT(TX_AC_BE_FIFO == 1);
 573                 ASSERT(TX_DATA_FIFO == 1);
 574                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 575                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 576                                            tune->ntxd, 0, 0, -1, 0, 0,
 577                                            &wl_msg_level);
 578                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 579
 580                 /*
 581                  * FIFO 2
 582                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 583                  * RX: UNUSED
 584                  */
 585                 ASSERT(TX_AC_VI_FIFO == 2);
 586                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 587                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 588                                            tune->ntxd, 0, 0, -1, 0, 0,
 589                                            &wl_msg_level);
 590                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 591                 /*
 592                  * FIFO 3
 593                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 594                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 595                  */
 596                 ASSERT(TX_AC_VO_FIFO == 3);
 597                 ASSERT(TX_CTL_FIFO == 3);
 598                 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 599                                            DMAREG(wlc_hw, DMA_TX, 3),
 600                                            NULL, tune->ntxd, 0, 0, -1,
 601                                            0, 0, &wl_msg_level);
 602                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 603 /* Cleaner to leave this as if with AP defined */
 604
 605                 if (dma_attach_err) {
 606                         WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
 607                         return false;
 608                 }
 609
 610                 /* get pointer to dma engine tx flow control variable */
 611                 for (i = 0; i < NFIFO; i++)
 612                         if (wlc_hw->di[i])
 613                                 wlc_hw->txavail[i] =
 614                                     (uint *) dma_getvar(wlc_hw->di[i],
 615                                                         "&txavail");
 616         }
 617
 618         /* initial ucode host flags */
 619         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 620
 621         return true;
 622 }
 623
 624 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 625 {
 626         uint j;
 627
 628         for (j = 0; j < NFIFO; j++) {
 629                 if (wlc_hw->di[j]) {
 630                         dma_detach(wlc_hw->di[j]);
 631                         wlc_hw->di[j] = NULL;
 632                 }
 633         }
 634 }
 635
 636 /* low level attach
 637  *    run backplane attach, init nvram
 638  *    run phy attach
 639  *    initialize software state for each core and band
 640  *    put the whole chip in reset(driver down state), no clock
 641  */
 642 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 643                     bool piomode, struct osl_info *osh, void *regsva,
 644                     uint bustype, void *btparam)
 645 {
 646         struct wlc_hw_info *wlc_hw;
 647         d11regs_t *regs;
 648         char *macaddr = NULL;
 649         char *vars;
 650         uint err = 0;
 651         uint j;
 652         bool wme = false;
 653         shared_phy_params_t sha_params;
 654
 655         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 656                  unit, vendor, device);
 657
 658         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 659
 660         wme = true;
 661
 662         wlc_hw = wlc->hw;
 663         wlc_hw->wlc = wlc;
 664         wlc_hw->unit = unit;
 665         wlc_hw->osh = osh;
 666         wlc_hw->band = wlc_hw->bandstate[0];
 667         wlc_hw->_piomode = piomode;
 668
 669         /* populate struct wlc_hw_info with default values  */
 670         wlc_bmac_info_init(wlc_hw);
 671
 672         /*
 673          * Do the hardware portion of the attach.
 674          * Also initialize software state that depends on the particular hardware
 675          * we are running.
 676          */
 677         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 678                                 &wlc_hw->vars, &wlc_hw->vars_size);
 679         if (wlc_hw->sih == NULL) {
 680                 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
 681                 err = 11;
 682                 goto fail;
 683         }
 684         vars = wlc_hw->vars;
 685
 686         /*
 687          * Get vendid/devid nvram overwrites, which could be different
 688          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 689          * SDIO_BUS, and SROMless devices on PCI_BUS.
 690          */
 691 #ifdef BCMBUSTYPE
 692         bustype = BCMBUSTYPE;
 693 #endif
 694         if (bustype != SI_BUS) {
 695                 char *var;
 696
 697                 var = getvar(vars, "vendid");
 698                 if (var) {
 699                         vendor = (u16) simple_strtoul(var, NULL, 0);
 700                         WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
 701                 }
 702                 var = getvar(vars, "devid");
 703                 if (var) {
 704                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 705                         if (devid != 0xffff) {
 706                                 device = devid;
 707                                 WL_ERROR("Overriding device id = 0x%x\n",
 708                                          device);
 709                         }
 710                 }
 711
 712                 /* verify again the device is supported */
 713                 if (!wlc_chipmatch(vendor, device)) {
 714                         WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
 715                                  unit, vendor, device);
 716                         err = 12;
 717                         goto fail;
 718                 }
 719         }
 720
 721         wlc_hw->vendorid = vendor;
 722         wlc_hw->deviceid = device;
 723
 724         /* set bar0 window to point at D11 core */
 725         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 726         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 727
 728         regs = wlc_hw->regs;
 729
 730         wlc->regs = wlc_hw->regs;
 731
 732         /* validate chip, chiprev and corerev */
 733         if (!wlc_isgoodchip(wlc_hw)) {
 734                 err = 13;
 735                 goto fail;
 736         }
 737
 738         /* initialize power control registers */
 739         si_clkctl_init(wlc_hw->sih);
 740
 741         /* request fastclock and force fastclock for the rest of attach
 742          * bring the d11 core out of reset.
 743          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 744          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 745          */
 746         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 747         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 748
 749         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 750                 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
 751                          unit);
 752                 err = 14;
 753                 goto fail;
 754         }
 755
 756         /* get the board rev, used just below */
 757         j = getintvar(vars, "boardrev");
 758         /* promote srom boardrev of 0xFF to 1 */
 759         if (j == BOARDREV_PROMOTABLE)
 760                 j = BOARDREV_PROMOTED;
 761         wlc_hw->boardrev = (u16) j;
 762         if (!wlc_validboardtype(wlc_hw)) {
 763                 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
 764                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 765                 err = 15;
 766                 goto fail;
 767         }
 768         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 769         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 770         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 771
 772         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 773                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 774
 775         if ((wlc_hw->sih->bustype == PCI_BUS)
 776             && (si_pci_war16165(wlc_hw->sih)))
 777                 wlc->war16165 = true;
 778
 779         /* check device id(srom, nvram etc.) to set bands */
 780         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 781                 /* Dualband boards */
 782                 wlc_hw->_nbands = 2;
 783         } else
 784                 wlc_hw->_nbands = 1;
 785
 786         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 787                 wlc_hw->_nbands = 1;
 788
 789         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 790          * init of these values
 791          */
 792         wlc->vendorid = wlc_hw->vendorid;
 793         wlc->deviceid = wlc_hw->deviceid;
 794         wlc->pub->sih = wlc_hw->sih;
 795         wlc->pub->corerev = wlc_hw->corerev;
 796         wlc->pub->sromrev = wlc_hw->sromrev;
 797         wlc->pub->boardrev = wlc_hw->boardrev;
 798         wlc->pub->boardflags = wlc_hw->boardflags;
 799         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 800         wlc->pub->_nbands = wlc_hw->_nbands;
 801
 802         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 803
 804         if (wlc_hw->physhim == NULL) {
 805                 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 806                          unit);
 807                 err = 25;
 808                 goto fail;
 809         }
 810
 811         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 812         sha_params.osh = osh;
 813         sha_params.sih = wlc_hw->sih;
 814         sha_params.physhim = wlc_hw->physhim;
 815         sha_params.unit = unit;
 816         sha_params.corerev = wlc_hw->corerev;
 817         sha_params.vars = vars;
 818         sha_params.vid = wlc_hw->vendorid;
 819         sha_params.did = wlc_hw->deviceid;
 820         sha_params.chip = wlc_hw->sih->chip;
 821         sha_params.chiprev = wlc_hw->sih->chiprev;
 822         sha_params.chippkg = wlc_hw->sih->chippkg;
 823         sha_params.sromrev = wlc_hw->sromrev;
 824         sha_params.boardtype = wlc_hw->sih->boardtype;
 825         sha_params.boardrev = wlc_hw->boardrev;
 826         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 827         sha_params.boardflags = wlc_hw->boardflags;
 828         sha_params.boardflags2 = wlc_hw->boardflags2;
 829         sha_params.bustype = wlc_hw->sih->bustype;
 830         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 831
 832         /* alloc and save pointer to shared phy state area */
 833         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 834         if (!wlc_hw->phy_sh) {
 835                 err = 16;
 836                 goto fail;
 837         }
 838
 839         /* initialize software state for each core and band */
 840         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 841                 /*
 842                  * band0 is always 2.4Ghz
 843                  * band1, if present, is 5Ghz
 844                  */
 845
 846                 /* So if this is a single band 11a card, use band 1 */
 847                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 848                         j = BAND_5G_INDEX;
 849
 850                 wlc_setxband(wlc_hw, j);
 851
 852                 wlc_hw->band->bandunit = j;
 853                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 854                 wlc->band->bandunit = j;
 855                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 856                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 857
 858                 wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 859                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 860
 861                 /* init tx fifo size */
 862                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 863                        ARRAY_SIZE(xmtfifo_sz));
 864                 wlc_hw->xmtfifo_sz =
 865                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 866
 867                 /* Get a phy for this band */
 868                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 869                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
 870                 if (wlc_hw->band->pi == NULL) {
 871                         WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
 872                                  unit);
 873                         err = 17;
 874                         goto fail;
 875                 }
 876
 877                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 878
 879                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 880                                        &wlc_hw->band->phyrev,
 881                                        &wlc_hw->band->radioid,
 882                                        &wlc_hw->band->radiorev);
 883                 wlc_hw->band->abgphy_encore =
 884                     wlc_phy_get_encore(wlc_hw->band->pi);
 885                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 886                 wlc_hw->band->core_flags =
 887                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 888
 889                 /* verify good phy_type & supported phy revision */
 890                 if (WLCISNPHY(wlc_hw->band)) {
 891                         if (NCONF_HAS(wlc_hw->band->phyrev))
 892                                 goto good_phy;
 893                         else
 894                                 goto bad_phy;
 895                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 896                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 897                                 goto good_phy;
 898                         else
 899                                 goto bad_phy;
 900                 } else {
 901  bad_phy:
 902                         WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
 903                                  unit,
 904                                  wlc_hw->band->phytype, wlc_hw->band->phyrev);
 905                         err = 18;
 906                         goto fail;
 907                 }
 908
 909  good_phy:
 910                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 911                  * high level attach. However we can not make that change until all low level access
 912                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 913                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 914                  * low only init when all fns updated.
 915                  */
 916                 wlc->band->pi = wlc_hw->band->pi;
 917                 wlc->band->phytype = wlc_hw->band->phytype;
 918                 wlc->band->phyrev = wlc_hw->band->phyrev;
 919                 wlc->band->radioid = wlc_hw->band->radioid;
 920                 wlc->band->radiorev = wlc_hw->band->radiorev;
 921
 922                 /* default contention windows size limits */
 923                 wlc_hw->band->CWmin = APHY_CWMIN;
 924                 wlc_hw->band->CWmax = PHY_CWMAX;
 925
 926                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 927                         err = 19;
 928                         goto fail;
 929                 }
 930         }
 931
 932         /* disable core to match driver "down" state */
 933         wlc_coredisable(wlc_hw);
 934
 935         /* Match driver "down" state */
 936         if (wlc_hw->sih->bustype == PCI_BUS)
 937                 si_pci_down(wlc_hw->sih);
 938
 939         /* register sb interrupt callback functions */
 940         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 941                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 942
 943         /* turn off pll and xtal to match driver "down" state */
 944         wlc_bmac_xtal(wlc_hw, OFF);
 945
 946         /* *********************************************************************
 947          * The hardware is in the DOWN state at this point. D11 core
 948          * or cores are in reset with clocks off, and the board PLLs
 949          * are off if possible.
 950          *
 951          * Beyond this point, wlc->sbclk == false and chip registers
 952          * should not be touched.
 953          *********************************************************************
 954          */
 955
 956         /* init etheraddr state variables */
 957         macaddr = wlc_get_macaddr(wlc_hw);
 958         if (macaddr == NULL) {
 959                 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
 960                 err = 21;
 961                 goto fail;
 962         }
 963         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 964         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 965             is_zero_ether_addr(wlc_hw->etheraddr)) {
 966                 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
 967                          unit, macaddr);
 968                 err = 22;
 969                 goto fail;
 970         }
 971
 972         WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 973                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
 974                  wlc_hw->sih->boardtype, macaddr);
 975
 976         return err;
 977
 978  fail:
 979         WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
 980         return err;
 981 }
 982
 983 /*
 984  * Initialize wlc_info default values ...
 985  * may get overrides later in this function
 986  *  BMAC_NOTES, move low out and resolve the dangling ones
 987  */
 988 static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
 989 {
 990         struct wlc_info *wlc = wlc_hw->wlc;
 991
 992         /* set default sw macintmask value */
 993         wlc->defmacintmask = DEF_MACINTMASK;
 994
 995         /* various 802.11g modes */
 996         wlc_hw->shortslot = false;
 997
 998         wlc_hw->SFBL = RETRY_SHORT_FB;
 999         wlc_hw->LFBL = RETRY_LONG_FB;
1000
1001         /* default mac retry limits */
1002         wlc_hw->SRL = RETRY_SHORT_DEF;
1003         wlc_hw->LRL = RETRY_LONG_DEF;
1004         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1005 }
1006
1007 /*
1008  * low level detach
1009  */
1010 int wlc_bmac_detach(struct wlc_info *wlc)
1011 {
1012         uint i;
1013         struct wlc_hwband *band;
1014         struct wlc_hw_info *wlc_hw = wlc->hw;
1015         int callbacks;
1016
1017         callbacks = 0;
1018
1019         if (wlc_hw->sih) {
1020                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1021                  * interrupt object may has been freed. this must be done before sb core switch
1022                  */
1023                 si_deregister_intr_callback(wlc_hw->sih);
1024
1025                 if (wlc_hw->sih->bustype == PCI_BUS)
1026                         si_pci_sleep(wlc_hw->sih);
1027         }
1028
1029         wlc_bmac_detach_dmapio(wlc_hw);
1030
1031         band = wlc_hw->band;
1032         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1033                 if (band->pi) {
1034                         /* Detach this band's phy */
1035                         wlc_phy_detach(band->pi);
1036                         band->pi = NULL;
1037                 }
1038                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1039         }
1040
1041         /* Free shared phy state */
1042         wlc_phy_shared_detach(wlc_hw->phy_sh);
1043
1044         wlc_phy_shim_detach(wlc_hw->physhim);
1045
1046         /* free vars */
1047         if (wlc_hw->vars) {
1048                 kfree(wlc_hw->vars);
1049                 wlc_hw->vars = NULL;
1050         }
1051
1052         if (wlc_hw->sih) {
1053                 si_detach(wlc_hw->sih);
1054                 wlc_hw->sih = NULL;
1055         }
1056
1057         return callbacks;
1058
1059 }
1060
1061 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1062 {
1063         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1064
1065         wlc_hw->wlc->pub->_cnt->reset++;
1066
1067         /* reset the core */
1068         if (!DEVICEREMOVED(wlc_hw->wlc))
1069                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1070
1071         /* purge the dma rings */
1072         wlc_flushqueues(wlc_hw->wlc);
1073
1074         wlc_reset_bmac_done(wlc_hw->wlc);
1075 }
1076
1077 void
1078 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1079                           bool mute) {
1080         u32 macintmask;
1081         bool fastclk;
1082         struct wlc_info *wlc = wlc_hw->wlc;
1083
1084         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1085
1086         /* request FAST clock if not on */
1087         fastclk = wlc_hw->forcefastclk;
1088         if (!fastclk)
1089                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1090
1091         /* disable interrupts */
1092         macintmask = wl_intrsoff(wlc->wl);
1093
1094         /* set up the specified band and chanspec */
1095         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1096         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1097
1098         /* do one-time phy inits and calibration */
1099         wlc_phy_cal_init(wlc_hw->band->pi);
1100
1101         /* core-specific initialization */
1102         wlc_coreinit(wlc);
1103
1104         /* suspend the tx fifos and mute the phy for preism cac time */
1105         if (mute)
1106                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1107
1108         /* band-specific inits */
1109         wlc_bmac_bsinit(wlc, chanspec);
1110
1111         /* restore macintmask */
1112         wl_intrsrestore(wlc->wl, macintmask);
1113
1114         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1115          * and wlc_enable_mac() will clear this override bit.
1116          */
1117         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1118
1119         /*
1120          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1121          */
1122         wlc_hw->mac_suspend_depth = 1;
1123
1124         /* restore the clk */
1125         if (!fastclk)
1126                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1127 }
1128
1129 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1130 {
1131         uint coremask;
1132
1133         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1134
1135         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1136
1137         /*
1138          * Enable pll and xtal, initialize the power control registers,
1139          * and force fastclock for the remainder of wlc_up().
1140          */
1141         wlc_bmac_xtal(wlc_hw, ON);
1142         si_clkctl_init(wlc_hw->sih);
1143         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1144
1145         /*
1146          * Configure pci/pcmcia here instead of in wlc_attach()
1147          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1148          */
1149         coremask = (1 << wlc_hw->wlc->core->coreidx);
1150
1151         if (wlc_hw->sih->bustype == PCI_BUS)
1152                 si_pci_setup(wlc_hw->sih, coremask);
1153
1154         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1155
1156         /*
1157          * Need to read the hwradio status here to cover the case where the system
1158          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1159          */
1160         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1161                 /* put SB PCI in down state again */
1162                 if (wlc_hw->sih->bustype == PCI_BUS)
1163                         si_pci_down(wlc_hw->sih);
1164                 wlc_bmac_xtal(wlc_hw, OFF);
1165                 return BCME_RADIOOFF;
1166         }
1167
1168         if (wlc_hw->sih->bustype == PCI_BUS)
1169                 si_pci_up(wlc_hw->sih);
1170
1171         /* reset the d11 core */
1172         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1173
1174         return 0;
1175 }
1176
1177 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1178 {
1179         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1180
1181         wlc_hw->up = true;
1182         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1183
1184         /* FULLY enable dynamic power control and d11 core interrupt */
1185         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1186         ASSERT(wlc_hw->wlc->macintmask == 0);
1187         wl_intrson(wlc_hw->wlc->wl);
1188         return 0;
1189 }
1190
1191 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1192 {
1193         bool dev_gone;
1194         uint callbacks = 0;
1195
1196         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1197
1198         if (!wlc_hw->up)
1199                 return callbacks;
1200
1201         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1202
1203         /* disable interrupts */
1204         if (dev_gone)
1205                 wlc_hw->wlc->macintmask = 0;
1206         else {
1207                 /* now disable interrupts */
1208                 wl_intrsoff(wlc_hw->wlc->wl);
1209
1210                 /* ensure we're running on the pll clock again */
1211                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1212         }
1213         /* down phy at the last of this stage */
1214         callbacks += wlc_phy_down(wlc_hw->band->pi);
1215
1216         return callbacks;
1217 }
1218
1219 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1220 {
1221         uint callbacks = 0;
1222         bool dev_gone;
1223
1224         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1225
1226         if (!wlc_hw->up)
1227                 return callbacks;
1228
1229         wlc_hw->up = false;
1230         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1231
1232         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1233
1234         if (dev_gone) {
1235                 wlc_hw->sbclk = false;
1236                 wlc_hw->clk = false;
1237                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1238
1239                 /* reclaim any posted packets */
1240                 wlc_flushqueues(wlc_hw->wlc);
1241         } else {
1242
1243                 /* Reset and disable the core */
1244                 if (si_iscoreup(wlc_hw->sih)) {
1245                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1246                             MCTL_EN_MAC)
1247                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1248                         callbacks += wl_reset(wlc_hw->wlc->wl);
1249                         wlc_coredisable(wlc_hw);
1250                 }
1251
1252                 /* turn off primary xtal and pll */
1253                 if (!wlc_hw->noreset) {
1254                         if (wlc_hw->sih->bustype == PCI_BUS)
1255                                 si_pci_down(wlc_hw->sih);
1256                         wlc_bmac_xtal(wlc_hw, OFF);
1257                 }
1258         }
1259
1260         return callbacks;
1261 }
1262
1263 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1264 {
1265         /* delay before first read of ucode state */
1266         udelay(40);
1267
1268         /* wait until ucode is no longer asleep */
1269         SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1270                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1271
1272         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1273 }
1274
1275 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1276 {
1277         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1278 }
1279
1280 static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1281 {
1282         return wlc_hw->band->bandtype;
1283 }
1284
1285 /* control chip clock to save power, enable dynamic clock or force fast clock */
1286 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1287 {
1288         if (PMUCTL_ENAB(wlc_hw->sih)) {
1289                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1290                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1291                  *      which means the FCA bit may not be set.
1292                  *      should wakeup mac if driver wants it to run on HT.
1293                  */
1294
1295                 if (wlc_hw->clk) {
1296                         if (mode == CLK_FAST) {
1297                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1298                                        CCS_FORCEHT);
1299
1300                                 udelay(64);
1301
1302                                 SPINWAIT(((R_REG
1303                                            (wlc_hw->osh,
1304                                             &wlc_hw->regs->
1305                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1306                                          PMU_MAX_TRANSITION_DLY);
1307                                 ASSERT(R_REG
1308                                        (wlc_hw->osh,
1309                                         &wlc_hw->regs->
1310                                         clk_ctl_st) & CCS_HTAVAIL);
1311                         } else {
1312                                 if ((wlc_hw->sih->pmurev == 0) &&
1313                                     (R_REG
1314                                      (wlc_hw->osh,
1315                                       &wlc_hw->regs->
1316                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1317                                         SPINWAIT(((R_REG
1318                                                    (wlc_hw->osh,
1319                                                     &wlc_hw->regs->
1320                                                     clk_ctl_st) & CCS_HTAVAIL)
1321                                                   == 0),
1322                                                  PMU_MAX_TRANSITION_DLY);
1323                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1324                                         ~CCS_FORCEHT);
1325                         }
1326                 }
1327                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1328         } else {
1329
1330                 /* old chips w/o PMU, force HT through cc,
1331                  * then use FCA to verify mac is running fast clock
1332                  */
1333
1334                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1335
1336                 /* check fast clock is available (if core is not in reset) */
1337                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1338                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1339
1340                 /* keep the ucode wake bit on if forcefastclk is on
1341                  * since we do not want ucode to put us back to slow clock
1342                  * when it dozes for PM mode.
1343                  * Code below matches the wake override bit with current forcefastclk state
1344                  * Only setting bit in wake_override instead of waking ucode immediately
1345                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1346                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1347                  * (protected by an up check) was executed just below.
1348                  */
1349                 if (wlc_hw->forcefastclk)
1350                         mboolset(wlc_hw->wake_override,
1351                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1352                 else
1353                         mboolclr(wlc_hw->wake_override,
1354                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1355         }
1356 }
1357
1358 /* set initial host flags value */
1359 static void
1360 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1361 {
1362         struct wlc_hw_info *wlc_hw = wlc->hw;
1363
1364         memset(mhfs, 0, MHFMAX * sizeof(u16));
1365
1366         mhfs[MHF2] |= mhf2_init;
1367
1368         /* prohibit use of slowclock on multifunction boards */
1369         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1370                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1371
1372         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1373                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1374                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1375         }
1376 }
1377
1378 /* set or clear ucode host flag bits
1379  * it has an optimization for no-change write
1380  * it only writes through shared memory when the core has clock;
1381  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1382  *
1383  *
1384  * bands values are: WLC_BAND_AUTO <--- Current band only
1385  *                   WLC_BAND_5G   <--- 5G band only
1386  *                   WLC_BAND_2G   <--- 2G band only
1387  *                   WLC_BAND_ALL  <--- All bands
1388  */
1389 void
1390 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1391              int bands)
1392 {
1393         u16 save;
1394         u16 addr[MHFMAX] = {
1395                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1396                 M_HOST_FLAGS5
1397         };
1398         struct wlc_hwband *band;
1399
1400         ASSERT((val & ~mask) == 0);
1401         ASSERT(idx < MHFMAX);
1402         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1403
1404         switch (bands) {
1405                 /* Current band only or all bands,
1406                  * then set the band to current band
1407                  */
1408         case WLC_BAND_AUTO:
1409         case WLC_BAND_ALL:
1410                 band = wlc_hw->band;
1411                 break;
1412         case WLC_BAND_5G:
1413                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1414                 break;
1415         case WLC_BAND_2G:
1416                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1417                 break;
1418         default:
1419                 ASSERT(0);
1420                 band = NULL;
1421         }
1422
1423         if (band) {
1424                 save = band->mhfs[idx];
1425                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1426
1427                 /* optimization: only write through if changed, and
1428                  * changed band is the current band
1429                  */
1430                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1431                     && (band == wlc_hw->band))
1432                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1433                                            (u16) band->mhfs[idx]);
1434         }
1435
1436         if (bands == WLC_BAND_ALL) {
1437                 wlc_hw->bandstate[0]->mhfs[idx] =
1438                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1439                 wlc_hw->bandstate[1]->mhfs[idx] =
1440                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1441         }
1442 }
1443
1444 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1445 {
1446         struct wlc_hwband *band;
1447         ASSERT(idx < MHFMAX);
1448
1449         switch (bands) {
1450         case WLC_BAND_AUTO:
1451                 band = wlc_hw->band;
1452                 break;
1453         case WLC_BAND_5G:
1454                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1455                 break;
1456         case WLC_BAND_2G:
1457                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1458                 break;
1459         default:
1460                 ASSERT(0);
1461                 band = NULL;
1462         }
1463
1464         if (!band)
1465                 return 0;
1466
1467         return band->mhfs[idx];
1468 }
1469
1470 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1471 {
1472         u8 idx;
1473         u16 addr[] = {
1474                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1475                 M_HOST_FLAGS5
1476         };
1477
1478         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1479
1480         for (idx = 0; idx < MHFMAX; idx++) {
1481                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1482         }
1483 }
1484
1485 /* set the maccontrol register to desired reset state and
1486  * initialize the sw cache of the register
1487  */
1488 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1489 {
1490         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1491         wlc_hw->maccontrol = 0;
1492         wlc_hw->suspended_fifos = 0;
1493         wlc_hw->wake_override = 0;
1494         wlc_hw->mute_override = 0;
1495         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1496 }
1497
1498 /* set or clear maccontrol bits */
1499 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1500 {
1501         u32 maccontrol;
1502         u32 new_maccontrol;
1503
1504         ASSERT((val & ~mask) == 0);
1505
1506         maccontrol = wlc_hw->maccontrol;
1507         new_maccontrol = (maccontrol & ~mask) | val;
1508
1509         /* if the new maccontrol value is the same as the old, nothing to do */
1510         if (new_maccontrol == maccontrol)
1511                 return;
1512
1513         /* something changed, cache the new value */
1514         wlc_hw->maccontrol = new_maccontrol;
1515
1516         /* write the new values with overrides applied */
1517         wlc_mctrl_write(wlc_hw);
1518 }
1519
1520 /* write the software state of maccontrol and overrides to the maccontrol register */
1521 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1522 {
1523         u32 maccontrol = wlc_hw->maccontrol;
1524
1525         /* OR in the wake bit if overridden */
1526         if (wlc_hw->wake_override)
1527                 maccontrol |= MCTL_WAKE;
1528
1529         /* set AP and INFRA bits for mute if needed */
1530         if (wlc_hw->mute_override) {
1531                 maccontrol &= ~(MCTL_AP);
1532                 maccontrol |= MCTL_INFRA;
1533         }
1534
1535         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1536 }
1537
1538 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1539 {
1540         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1541
1542         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1543                 mboolset(wlc_hw->wake_override, override_bit);
1544                 return;
1545         }
1546
1547         mboolset(wlc_hw->wake_override, override_bit);
1548
1549         wlc_mctrl_write(wlc_hw);
1550         wlc_bmac_wait_for_wake(wlc_hw);
1551
1552         return;
1553 }
1554
1555 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1556 {
1557         ASSERT(wlc_hw->wake_override & override_bit);
1558
1559         mboolclr(wlc_hw->wake_override, override_bit);
1560
1561         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1562                 return;
1563
1564         wlc_mctrl_write(wlc_hw);
1565
1566         return;
1567 }
1568
1569 /* When driver needs ucode to stop beaconing, it has to make sure that
1570  * MCTL_AP is clear and MCTL_INFRA is set
1571  * Mode           MCTL_AP        MCTL_INFRA
1572  * AP                1              1
1573  * STA               0              1 <--- This will ensure no beacons
1574  * IBSS              0              0
1575  */
1576 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1577 {
1578         wlc_hw->mute_override = 1;
1579
1580         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1581          * override, then there is no change to write
1582          */
1583         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1584                 return;
1585
1586         wlc_mctrl_write(wlc_hw);
1587
1588         return;
1589 }
1590
1591 /* Clear the override on AP and INFRA bits */
1592 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1593 {
1594         if (wlc_hw->mute_override == 0)
1595                 return;
1596
1597         wlc_hw->mute_override = 0;
1598
1599         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1600          * override, then there is no change to write
1601          */
1602         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1603                 return;
1604
1605         wlc_mctrl_write(wlc_hw);
1606 }
1607
1608 /*
1609  * Write a MAC address to the rcmta structure
1610  */
1611 void
1612 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1613                    const u8 *addr)
1614 {
1615         d11regs_t *regs = wlc_hw->regs;
1616         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1617         u32 mac_hm;
1618         u16 mac_l;
1619         struct osl_info *osh;
1620
1621         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1622
1623         mac_hm =
1624             (addr[3] << 24) | (addr[2] << 16) |
1625             (addr[1] << 8) | addr[0];
1626         mac_l = (addr[5] << 8) | addr[4];
1627
1628         osh = wlc_hw->osh;
1629
1630         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1631         (void)R_REG(osh, &regs->objaddr);
1632         W_REG(osh, &regs->objdata, mac_hm);
1633         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1634         (void)R_REG(osh, &regs->objaddr);
1635         W_REG(osh, objdata16, mac_l);
1636 }
1637
1638 /*
1639  * Write a MAC address to the given match reg offset in the RXE match engine.
1640  */
1641 void
1642 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1643                        const u8 *addr)
1644 {
1645         d11regs_t *regs;
1646         u16 mac_l;
1647         u16 mac_m;
1648         u16 mac_h;
1649         struct osl_info *osh;
1650
1651         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1652
1653         ASSERT(match_reg_offset < RCM_SIZE);
1654
1655         regs = wlc_hw->regs;
1656         mac_l = addr[0] | (addr[1] << 8);
1657         mac_m = addr[2] | (addr[3] << 8);
1658         mac_h = addr[4] | (addr[5] << 8);
1659
1660         osh = wlc_hw->osh;
1661
1662         /* enter the MAC addr into the RXE match registers */
1663         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1664         W_REG(osh, &regs->rcm_mat_data, mac_l);
1665         W_REG(osh, &regs->rcm_mat_data, mac_m);
1666         W_REG(osh, &regs->rcm_mat_data, mac_h);
1667
1668 }
1669
1670 void
1671 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1672                             void *buf)
1673 {
1674         d11regs_t *regs;
1675         u32 word;
1676         bool be_bit;
1677 #ifdef IL_BIGENDIAN
1678         volatile u16 *dptr = NULL;
1679 #endif                          /* IL_BIGENDIAN */
1680         struct osl_info *osh;
1681
1682         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1683
1684         regs = wlc_hw->regs;
1685         osh = wlc_hw->osh;
1686
1687         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1688         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1689         ASSERT((offset & ~0xffff) == 0);
1690
1691         W_REG(osh, &regs->tplatewrptr, offset);
1692
1693         /* if MCTL_BIGEND bit set in mac control register,
1694          * the chip swaps data in fifo, as well as data in
1695          * template ram
1696          */
1697         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1698
1699         while (len > 0) {
1700                 memcpy(&word, buf, sizeof(u32));
1701
1702                 if (be_bit)
1703                         word = cpu_to_be32(word);
1704                 else
1705                         word = cpu_to_le32(word);
1706
1707                 W_REG(osh, &regs->tplatewrdata, word);
1708
1709                 buf = (u8 *) buf + sizeof(u32);
1710                 len -= sizeof(u32);
1711         }
1712 }
1713
1714 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1715 {
1716         struct osl_info *osh;
1717
1718         osh = wlc_hw->osh;
1719         wlc_hw->band->CWmin = newmin;
1720
1721         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1722         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1723         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1724 }
1725
1726 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1727 {
1728         struct osl_info *osh;
1729
1730         osh = wlc_hw->osh;
1731         wlc_hw->band->CWmax = newmax;
1732
1733         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1734         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1735         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1736 }
1737
1738 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1739 {
1740         bool fastclk;
1741
1742         /* request FAST clock if not on */
1743         fastclk = wlc_hw->forcefastclk;
1744         if (!fastclk)
1745                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1746
1747         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1748
1749         ASSERT(wlc_hw->clk);
1750
1751         wlc_bmac_phy_reset(wlc_hw);
1752         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1753
1754         /* restore the clk */
1755         if (!fastclk)
1756                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1757 }
1758
1759 static void
1760 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1761 {
1762         d11regs_t *regs = wlc_hw->regs;
1763
1764         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1765                                     bcn);
1766         /* write beacon length to SCR */
1767         ASSERT(len < 65536);
1768         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1769         /* mark beacon0 valid */
1770         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1771 }
1772
1773 static void
1774 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1775 {
1776         d11regs_t *regs = wlc_hw->regs;
1777
1778         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1779                                     bcn);
1780         /* write beacon length to SCR */
1781         ASSERT(len < 65536);
1782         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1783         /* mark beacon1 valid */
1784         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1785 }
1786
1787 /* mac is assumed to be suspended at this point */
1788 void
1789 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1790                                bool both)
1791 {
1792         d11regs_t *regs = wlc_hw->regs;
1793
1794         if (both) {
1795                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1796                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1797         } else {
1798                 /* bcn 0 */
1799                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1800                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1801                 /* bcn 1 */
1802                 else if (!
1803                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1804                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1805                 else            /* one template should always have been available */
1806                         ASSERT(0);
1807         }
1808 }
1809
1810 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1811 {
1812         u16 v;
1813         struct wlc_info *wlc = wlc_hw->wlc;
1814         /* update SYNTHPU_DLY */
1815
1816         if (WLCISLCNPHY(wlc->band)) {
1817                 v = SYNTHPU_DLY_LPPHY_US;
1818         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1819                 v = SYNTHPU_DLY_NPHY_US;
1820         } else {
1821                 v = SYNTHPU_DLY_BPHY_US;
1822         }
1823
1824         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1825 }
1826
1827 /* band-specific init */
1828 static void
1829 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1830 {
1831         struct wlc_hw_info *wlc_hw = wlc->hw;
1832
1833         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1834                  wlc_hw->unit, wlc_hw->band->bandunit);
1835
1836         /* sanity check */
1837         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1838             PHY_TYPE_LCNXN)
1839                 ASSERT((uint)
1840                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1841                        == wlc_hw->band->phytype);
1842
1843         wlc_ucode_bsinit(wlc_hw);
1844
1845         wlc_phy_init(wlc_hw->band->pi, chanspec);
1846
1847         wlc_ucode_txant_set(wlc_hw);
1848
1849         /* cwmin is band-specific, update hardware with value for current band */
1850         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1851         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1852
1853         wlc_bmac_update_slot_timing(wlc_hw,
1854                                     BAND_5G(wlc_hw->band->
1855                                             bandtype) ? true : wlc_hw->
1856                                     shortslot);
1857
1858         /* write phytype and phyvers */
1859         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1860         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1861
1862         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1863         wlc_upd_ofdm_pctl1_table(wlc_hw);
1864
1865         wlc_bmac_upd_synthpu(wlc_hw);
1866 }
1867
1868 static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1869 {
1870         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1871
1872         wlc_hw->phyclk = clk;
1873
1874         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1875
1876                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1877                                (SICF_PRST | SICF_FGC));
1878                 udelay(1);
1879                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1880                 udelay(1);
1881
1882         } else {                /* take phy out of reset */
1883
1884                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1885                 udelay(1);
1886                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1887                 udelay(1);
1888
1889         }
1890 }
1891
1892 /* Perform a soft reset of the PHY PLL */
1893 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1894 {
1895         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1896
1897         si_corereg(wlc_hw->sih, SI_CC_IDX,
1898                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1899         udelay(1);
1900         si_corereg(wlc_hw->sih, SI_CC_IDX,
1901                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1902         udelay(1);
1903         si_corereg(wlc_hw->sih, SI_CC_IDX,
1904                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1905         udelay(1);
1906         si_corereg(wlc_hw->sih, SI_CC_IDX,
1907                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1908         udelay(1);
1909 }
1910
1911 /* light way to turn on phy clock without reset for NPHY only
1912  *  refer to wlc_bmac_core_phy_clk for full version
1913  */
1914 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1915 {
1916         /* support(necessary for NPHY and HYPHY) only */
1917         if (!WLCISNPHY(wlc_hw->band))
1918                 return;
1919
1920         if (ON == clk)
1921                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1922         else
1923                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1924
1925 }
1926
1927 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1928 {
1929         if (ON == clk)
1930                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1931         else
1932                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1933 }
1934
1935 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1936 {
1937         wlc_phy_t *pih = wlc_hw->band->pi;
1938         u32 phy_bw_clkbits;
1939         bool phy_in_reset = false;
1940
1941         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
1942
1943         if (pih == NULL)
1944                 return;
1945
1946         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1947
1948         /* Specfic reset sequence required for NPHY rev 3 and 4 */
1949         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1950             NREV_LE(wlc_hw->band->phyrev, 4)) {
1951                 /* Set the PHY bandwidth */
1952                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1953
1954                 udelay(1);
1955
1956                 /* Perform a soft reset of the PHY PLL */
1957                 wlc_bmac_core_phypll_reset(wlc_hw);
1958
1959                 /* reset the PHY */
1960                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1961                                (SICF_PRST | SICF_PCLKE));
1962                 phy_in_reset = true;
1963         } else {
1964
1965                 si_core_cflags(wlc_hw->sih,
1966                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1967                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1968         }
1969
1970         udelay(2);
1971         wlc_bmac_core_phy_clk(wlc_hw, ON);
1972
1973         if (pih)
1974                 wlc_phy_anacore(pih, ON);
1975 }
1976
1977 /* switch to and initialize new band */
1978 static void
1979 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
1980                                 chanspec_t chanspec) {
1981         struct wlc_info *wlc = wlc_hw->wlc;
1982         u32 macintmask;
1983
1984         ASSERT(NBANDS_HW(wlc_hw) > 1);
1985         ASSERT(bandunit != wlc_hw->band->bandunit);
1986
1987         /* Enable the d11 core before accessing it */
1988         if (!si_iscoreup(wlc_hw->sih)) {
1989                 si_core_reset(wlc_hw->sih, 0, 0);
1990                 ASSERT(si_iscoreup(wlc_hw->sih));
1991                 wlc_mctrl_reset(wlc_hw);
1992         }
1993
1994         macintmask = wlc_setband_inact(wlc, bandunit);
1995
1996         if (!wlc_hw->up)
1997                 return;
1998
1999         wlc_bmac_core_phy_clk(wlc_hw, ON);
2000
2001         /* band-specific initializations */
2002         wlc_bmac_bsinit(wlc, chanspec);
2003
2004         /*
2005          * If there are any pending software interrupt bits,
2006          * then replace these with a harmless nonzero value
2007          * so wlc_dpc() will re-enable interrupts when done.
2008          */
2009         if (wlc->macintstatus)
2010                 wlc->macintstatus = MI_DMAINT;
2011
2012         /* restore macintmask */
2013         wl_intrsrestore(wlc->wl, macintmask);
2014
2015         /* ucode should still be suspended.. */
2016         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2017                0);
2018 }
2019
2020 /* low-level band switch utility routine */
2021 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
2022 {
2023         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
2024
2025         wlc_hw->band = wlc_hw->bandstate[bandunit];
2026
2027         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2028         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2029
2030         /* set gmode core flag */
2031         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2032                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2033                                ((bandunit == 0) ? SICF_GMODE : 0));
2034         }
2035 }
2036
2037 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2038 {
2039
2040         /* reject unsupported corerev */
2041         if (!VALID_COREREV(wlc_hw->corerev)) {
2042                 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2043                 return false;
2044         }
2045
2046         return true;
2047 }
2048
2049 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2050 {
2051         bool goodboard = true;
2052         uint boardrev = wlc_hw->boardrev;
2053
2054         if (boardrev == 0)
2055                 goodboard = false;
2056         else if (boardrev > 0xff) {
2057                 uint brt = (boardrev & 0xf000) >> 12;
2058                 uint b0 = (boardrev & 0xf00) >> 8;
2059                 uint b1 = (boardrev & 0xf0) >> 4;
2060                 uint b2 = boardrev & 0xf;
2061
2062                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2063                     || (b2 > 9))
2064                         goodboard = false;
2065         }
2066
2067         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2068                 return goodboard;
2069
2070         return goodboard;
2071 }
2072
2073 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2074 {
2075         const char *varname = "macaddr";
2076         char *macaddr;
2077
2078         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2079         macaddr = getvar(wlc_hw->vars, varname);
2080         if (macaddr != NULL)
2081                 return macaddr;
2082
2083         if (NBANDS_HW(wlc_hw) > 1)
2084                 varname = "et1macaddr";
2085         else
2086                 varname = "il0macaddr";
2087
2088         macaddr = getvar(wlc_hw->vars, varname);
2089         if (macaddr == NULL) {
2090                 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2091                          wlc_hw->unit, varname);
2092         }
2093
2094         return macaddr;
2095 }
2096
2097 /*
2098  * Return true if radio is disabled, otherwise false.
2099  * hw radio disable signal is an external pin, users activate it asynchronously
2100  * this function could be called when driver is down and w/o clock
2101  * it operates on different registers depending on corerev and boardflag.
2102  */
2103 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2104 {
2105         bool v, clk, xtal;
2106         u32 resetbits = 0, flags = 0;
2107
2108         xtal = wlc_hw->sbclk;
2109         if (!xtal)
2110                 wlc_bmac_xtal(wlc_hw, ON);
2111
2112         /* may need to take core out of reset first */
2113         clk = wlc_hw->clk;
2114         if (!clk) {
2115                 /*
2116                  * mac no longer enables phyclk automatically when driver
2117                  * accesses phyreg throughput mac. This can be skipped since
2118                  * only mac reg is accessed below
2119                  */
2120                 flags |= SICF_PCLKE;
2121
2122                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2123                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2124                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2125                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2126                         wlc_hw->regs =
2127                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2128                                                      0);
2129                 si_core_reset(wlc_hw->sih, flags, resetbits);
2130                 wlc_mctrl_reset(wlc_hw);
2131         }
2132
2133         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2134
2135         /* put core back into reset */
2136         if (!clk)
2137                 si_core_disable(wlc_hw->sih, 0);
2138
2139         if (!xtal)
2140                 wlc_bmac_xtal(wlc_hw, OFF);
2141
2142         return v;
2143 }
2144
2145 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2146 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2147 {
2148         if (wlc_hw->wlc->pub->hw_up)
2149                 return;
2150
2151         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2152
2153         /*
2154          * Enable pll and xtal, initialize the power control registers,
2155          * and force fastclock for the remainder of wlc_up().
2156          */
2157         wlc_bmac_xtal(wlc_hw, ON);
2158         si_clkctl_init(wlc_hw->sih);
2159         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2160
2161         if (wlc_hw->sih->bustype == PCI_BUS) {
2162                 si_pci_fixcfg(wlc_hw->sih);
2163
2164                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2165                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2166                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2167                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2168                         wlc_hw->regs =
2169                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2170                                                      0);
2171         }
2172
2173         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2174         wlc_phy_por_inform(wlc_hw->band->pi);
2175
2176         wlc_hw->ucode_loaded = false;
2177         wlc_hw->wlc->pub->hw_up = true;
2178
2179         if ((wlc_hw->boardflags & BFL_FEM)
2180             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2181                 if (!
2182                     (wlc_hw->boardrev >= 0x1250
2183                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2184                         si_epa_4313war(wlc_hw->sih);
2185         }
2186 }
2187
2188 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2189 {
2190         struct hnddma_pub *di = wlc_hw->di[fifo];
2191         return dma_rxreset(di);
2192 }
2193
2194 /* d11 core reset
2195  *   ensure fask clock during reset
2196  *   reset dma
2197  *   reset d11(out of reset)
2198  *   reset phy(out of reset)
2199  *   clear software macintstatus for fresh new start
2200  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2201  */
2202 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2203 {
2204         d11regs_t *regs;
2205         uint i;
2206         bool fastclk;
2207         u32 resetbits = 0;
2208
2209         if (flags == WLC_USE_COREFLAGS)
2210                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2211
2212         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2213
2214         regs = wlc_hw->regs;
2215
2216         /* request FAST clock if not on  */
2217         fastclk = wlc_hw->forcefastclk;
2218         if (!fastclk)
2219                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2220
2221         /* reset the dma engines except first time thru */
2222         if (si_iscoreup(wlc_hw->sih)) {
2223                 for (i = 0; i < NFIFO; i++)
2224                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2225                                 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2226                                          wlc_hw->unit, __func__, i);
2227                         }
2228
2229                 if ((wlc_hw->di[RX_FIFO])
2230                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2231                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2232                                  wlc_hw->unit, __func__, RX_FIFO);
2233                 }
2234         }
2235         /* if noreset, just stop the psm and return */
2236         if (wlc_hw->noreset) {
2237                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2238                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2239                 return;
2240         }
2241
2242         /*
2243          * mac no longer enables phyclk automatically when driver accesses
2244          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2245          * band->pi is invalid. need to enable PHY CLK
2246          */
2247         flags |= SICF_PCLKE;
2248
2249         /* reset the core
2250          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2251          *  is cleared by the core_reset. have to re-request it.
2252          *  This adds some delay and we can optimize it by also requesting fastclk through
2253          *  chipcommon during this period if necessary. But that has to work coordinate
2254          *  with other driver like mips/arm since they may touch chipcommon as well.
2255          */
2256         wlc_hw->clk = false;
2257         si_core_reset(wlc_hw->sih, flags, resetbits);
2258         wlc_hw->clk = true;
2259         if (wlc_hw->band && wlc_hw->band->pi)
2260                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2261
2262         wlc_mctrl_reset(wlc_hw);
2263
2264         if (PMUCTL_ENAB(wlc_hw->sih))
2265                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2266
2267         wlc_bmac_phy_reset(wlc_hw);
2268
2269         /* turn on PHY_PLL */
2270         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2271
2272         /* clear sw intstatus */
2273         wlc_hw->wlc->macintstatus = 0;
2274
2275         /* restore the clk setting */
2276         if (!fastclk)
2277                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2278 }
2279
2280 /* txfifo sizes needs to be modified(increased) since the newer cores
2281  * have more memory.
2282  */
2283 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2284 {
2285         d11regs_t *regs = wlc_hw->regs;
2286         u16 fifo_nu;
2287         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2288         u16 txfifo_def, txfifo_def1;
2289         u16 txfifo_cmd;
2290         struct osl_info *osh;
2291
2292         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2293         txfifo_startblk = TXFIFO_START_BLK;
2294
2295         osh = wlc_hw->osh;
2296
2297         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2298         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2299
2300                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2301                 txfifo_def = (txfifo_startblk & 0xff) |
2302                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2303                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2304                     ((((txfifo_endblk -
2305                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2306                 txfifo_cmd =
2307                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2308
2309                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2310                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2311                 W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2312
2313                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2314
2315                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2316         }
2317         /*
2318          * need to propagate to shm location to be in sync since ucode/hw won't
2319          * do this
2320          */
2321         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2322                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2323         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2324                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2325         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2326                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2327                             xmtfifo_sz[TX_AC_BK_FIFO]));
2328         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2329                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2330                             xmtfifo_sz[TX_BCMC_FIFO]));
2331 }
2332
2333 /* d11 core init
2334  *   reset PSM
2335  *   download ucode/PCM
2336  *   let ucode run to suspended
2337  *   download ucode inits
2338  *   config other core registers
2339  *   init dma
2340  */
2341 static void wlc_coreinit(struct wlc_info *wlc)
2342 {
2343         struct wlc_hw_info *wlc_hw = wlc->hw;
2344         d11regs_t *regs;
2345         u32 sflags;
2346         uint bcnint_us;
2347         uint i = 0;
2348         bool fifosz_fixup = false;
2349         struct osl_info *osh;
2350         int err = 0;
2351         u16 buf[NFIFO];
2352
2353         regs = wlc_hw->regs;
2354         osh = wlc_hw->osh;
2355
2356         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2357
2358         /* reset PSM */
2359         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2360
2361         wlc_ucode_download(wlc_hw);
2362         /*
2363          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2364          */
2365         fifosz_fixup = true;
2366
2367         /* let the PSM run to the suspended state, set mode to BSS STA */
2368         W_REG(osh, &regs->macintstatus, -1);
2369         wlc_bmac_mctrl(wlc_hw, ~0,
2370                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2371
2372         /* wait for ucode to self-suspend after auto-init */
2373         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2374                  1000 * 1000);
2375         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2376                 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2377                          wlc_hw->unit);
2378
2379         wlc_gpio_init(wlc);
2380
2381         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2382
2383         if (D11REV_IS(wlc_hw->corerev, 23)) {
2384                 if (WLCISNPHY(wlc_hw->band))
2385                         wlc_write_inits(wlc_hw, d11n0initvals16);
2386                 else
2387                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2388                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2389         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2390                 if (WLCISLCNPHY(wlc_hw->band)) {
2391                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2392                 } else {
2393                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2394                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2395                 }
2396         } else {
2397                 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2398                          __func__, wlc_hw->unit, wlc_hw->corerev);
2399         }
2400
2401         /* For old ucode, txfifo sizes needs to be modified(increased) */
2402         if (fifosz_fixup == true) {
2403                 wlc_corerev_fifofixup(wlc_hw);
2404         }
2405
2406         /* check txfifo allocations match between ucode and driver */
2407         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2408         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2409                 i = TX_AC_BE_FIFO;
2410                 err = -1;
2411         }
2412         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2413         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2414                 i = TX_AC_VI_FIFO;
2415                 err = -1;
2416         }
2417         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2418         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2419         buf[TX_AC_BK_FIFO] &= 0xff;
2420         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2421                 i = TX_AC_BK_FIFO;
2422                 err = -1;
2423         }
2424         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2425                 i = TX_AC_VO_FIFO;
2426                 err = -1;
2427         }
2428         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2429         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2430         buf[TX_BCMC_FIFO] &= 0xff;
2431         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2432                 i = TX_BCMC_FIFO;
2433                 err = -1;
2434         }
2435         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2436                 i = TX_ATIM_FIFO;
2437                 err = -1;
2438         }
2439         if (err != 0) {
2440                 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2441                          buf[i], wlc_hw->xmtfifo_sz[i], i);
2442                 ASSERT(0);
2443         }
2444
2445         /* make sure we can still talk to the mac */
2446         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2447
2448         /* band-specific inits done by wlc_bsinit() */
2449
2450         /* Set up frame burst size and antenna swap threshold init values */
2451         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2452         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2453
2454         /* enable one rx interrupt per received frame */
2455         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2456
2457         /* set the station mode (BSS STA) */
2458         wlc_bmac_mctrl(wlc_hw,
2459                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2460                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2461
2462         /* set up Beacon interval */
2463         bcnint_us = 0x8000 << 10;
2464         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2465         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2466         W_REG(osh, &regs->macintstatus, MI_GP1);
2467
2468         /* write interrupt mask */
2469         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2470
2471         /* allow the MAC to control the PHY clock (dynamic on/off) */
2472         wlc_bmac_macphyclk_set(wlc_hw, ON);
2473
2474         /* program dynamic clock control fast powerup delay register */
2475         wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2476         W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2477
2478         /* tell the ucode the corerev */
2479         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2480
2481         /* tell the ucode MAC capabilities */
2482         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2483                            (u16) (wlc_hw->machwcap & 0xffff));
2484         wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2485                            (u16) ((wlc_hw->
2486                                       machwcap >> 16) & 0xffff));
2487
2488         /* write retry limits to SCR, this done after PSM init */
2489         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2490         (void)R_REG(osh, &regs->objaddr);
2491         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2492         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2493         (void)R_REG(osh, &regs->objaddr);
2494         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2495
2496         /* write rate fallback retry limits */
2497         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2498         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2499
2500         AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2501         W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2502
2503         /* dma initializations */
2504         wlc->txpend16165war = 0;
2505
2506         /* init the tx dma engines */
2507         for (i = 0; i < NFIFO; i++) {
2508                 if (wlc_hw->di[i])
2509                         dma_txinit(wlc_hw->di[i]);
2510         }
2511
2512         /* init the rx dma engine(s) and post receive buffers */
2513         dma_rxinit(wlc_hw->di[RX_FIFO]);
2514         dma_rxfill(wlc_hw->di[RX_FIFO]);
2515 }
2516
2517 /* This function is used for changing the tsf frac register
2518  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2519  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2520  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2521  * HTPHY Formula is 2^26/freq(MHz) e.g.
2522  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2523  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2524  * For spuron: 123MHz -> 2^26/123    = 545600.5
2525  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2526  * For spur off: 120MHz -> 2^26/120    = 559240.5
2527  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2528  */
2529
2530 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2531 {
2532         d11regs_t *regs;
2533         struct osl_info *osh;
2534         regs = wlc_hw->regs;
2535         osh = wlc_hw->osh;
2536
2537         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2538             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2539                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2540                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2541                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2542                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2543                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2544                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2545                 } else {        /* 120Mhz */
2546                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2547                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2548                 }
2549         } else if (WLCISLCNPHY(wlc_hw->band)) {
2550                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2551                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2552                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2553                 } else {        /* 80Mhz */
2554                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2555                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2556                 }
2557         }
2558 }
2559
2560 /* Initialize GPIOs that are controlled by D11 core */
2561 static void wlc_gpio_init(struct wlc_info *wlc)
2562 {
2563         struct wlc_hw_info *wlc_hw = wlc->hw;
2564         d11regs_t *regs;
2565         u32 gc, gm;
2566         struct osl_info *osh;
2567
2568         regs = wlc_hw->regs;
2569         osh = wlc_hw->osh;
2570
2571         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2572         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2573
2574         /*
2575          * Common GPIO setup:
2576          *      G0 = LED 0 = WLAN Activity
2577          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2578          *      G2 = LED 2 = WLAN 5 GHz Radio State
2579          *      G4 = radio disable input (HI enabled, LO disabled)
2580          */
2581
2582         gc = gm = 0;
2583
2584         /* Allocate GPIOs for mimo antenna diversity feature */
2585         if (WLANTSEL_ENAB(wlc)) {
2586                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2587                         /* Enable antenna diversity, use 2x3 mode */
2588                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2589                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2590                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2591                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2592
2593                         /* init superswitch control */
2594                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2595
2596                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2597                         ASSERT((gm & BOARD_GPIO_12) == 0);
2598                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2599                         /* The board itself is powered by these GPIOs (when not sending pattern)
2600                          * So set them high
2601                          */
2602                         OR_REG(osh, &regs->psm_gpio_oe,
2603                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2604                         OR_REG(osh, &regs->psm_gpio_out,
2605                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2606
2607                         /* Enable antenna diversity, use 2x4 mode */
2608                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2609                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2610                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2611                                      WLC_BAND_ALL);
2612
2613                         /* Configure the desired clock to be 4Mhz */
2614                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2615                                            ANTSEL_CLKDIV_4MHZ);
2616                 }
2617         }
2618         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2619         if (wlc_hw->boardflags & BFL_PACTRL)
2620                 gm |= gc |= BOARD_GPIO_PACTRL;
2621
2622         /* apply to gpiocontrol register */
2623         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2624 }
2625
2626 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2627 {
2628         struct wlc_info *wlc;
2629         wlc = wlc_hw->wlc;
2630
2631         if (wlc_hw->ucode_loaded)
2632                 return;
2633
2634         if (D11REV_IS(wlc_hw->corerev, 23)) {
2635                 if (WLCISNPHY(wlc_hw->band)) {
2636                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2637                                         bcm43xx_16_mimosz);
2638                         wlc_hw->ucode_loaded = true;
2639                 } else
2640                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2641                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2642         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2643                 if (WLCISLCNPHY(wlc_hw->band)) {
2644                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2645                                         bcm43xx_24_lcnsz);
2646                         wlc_hw->ucode_loaded = true;
2647                 } else {
2648                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2649                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2650                 }
2651         }
2652 }
2653
2654 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2655                               const uint nbytes) {
2656         struct osl_info *osh;
2657         d11regs_t *regs = wlc_hw->regs;
2658         uint i;
2659         uint count;
2660
2661         osh = wlc_hw->osh;
2662
2663         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2664
2665         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2666
2667         count = (nbytes / sizeof(u32));
2668
2669         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2670         (void)R_REG(osh, &regs->objaddr);
2671         for (i = 0; i < count; i++)
2672                 W_REG(osh, &regs->objdata, ucode[i]);
2673 }
2674
2675 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits)
2676 {
2677         int i;
2678         struct osl_info *osh;
2679         volatile u8 *base;
2680
2681         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2682
2683         osh = wlc_hw->osh;
2684         base = (volatile u8 *)wlc_hw->regs;
2685
2686         for (i = 0; inits[i].addr != 0xffff; i++) {
2687                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2688
2689                 if (inits[i].size == 2)
2690                         W_REG(osh, (u16 *)(base + inits[i].addr),
2691                               inits[i].value);
2692                 else if (inits[i].size == 4)
2693                         W_REG(osh, (u32 *)(base + inits[i].addr),
2694                               inits[i].value);
2695         }
2696 }
2697
2698 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2699 {
2700         u16 phyctl;
2701         u16 phytxant = wlc_hw->bmac_phytxant;
2702         u16 mask = PHY_TXC_ANT_MASK;
2703
2704         /* set the Probe Response frame phy control word */
2705         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2706         phyctl = (phyctl & ~mask) | phytxant;
2707         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2708
2709         /* set the Response (ACK/CTS) frame phy control word */
2710         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2711         phyctl = (phyctl & ~mask) | phytxant;
2712         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2713 }
2714
2715 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2716 {
2717         /* update sw state */
2718         wlc_hw->bmac_phytxant = phytxant;
2719
2720         /* push to ucode if up */
2721         if (!wlc_hw->up)
2722                 return;
2723         wlc_ucode_txant_set(wlc_hw);
2724
2725 }
2726
2727 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2728 {
2729         return (u16) wlc_hw->wlc->stf->txant;
2730 }
2731
2732 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2733 {
2734         wlc_hw->antsel_type = antsel_type;
2735
2736         /* Update the antsel type for phy module to use */
2737         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2738 }
2739
2740 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2741 {
2742         bool fatal = false;
2743         uint unit;
2744         uint intstatus, idx;
2745         d11regs_t *regs = wlc_hw->regs;
2746
2747         unit = wlc_hw->unit;
2748
2749         for (idx = 0; idx < NFIFO; idx++) {
2750                 /* read intstatus register and ignore any non-error bits */
2751                 intstatus =
2752                     R_REG(wlc_hw->osh,
2753                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2754                 if (!intstatus)
2755                         continue;
2756
2757                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2758                          unit, idx, intstatus);
2759
2760                 if (intstatus & I_RO) {
2761                         WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2762                                  unit, idx);
2763                         wlc_hw->wlc->pub->_cnt->rxoflo++;
2764                         fatal = true;
2765                 }
2766
2767                 if (intstatus & I_PC) {
2768                         WL_ERROR("wl%d: fifo %d: descriptor error\n",
2769                                  unit, idx);
2770                         wlc_hw->wlc->pub->_cnt->dmade++;
2771                         fatal = true;
2772                 }
2773
2774                 if (intstatus & I_PD) {
2775                         WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2776                         wlc_hw->wlc->pub->_cnt->dmada++;
2777                         fatal = true;
2778                 }
2779
2780                 if (intstatus & I_DE) {
2781                         WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2782                                  unit, idx);
2783                         wlc_hw->wlc->pub->_cnt->dmape++;
2784                         fatal = true;
2785                 }
2786
2787                 if (intstatus & I_RU) {
2788                         WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2789                                  idx, unit);
2790                         wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
2791                 }
2792
2793                 if (intstatus & I_XU) {
2794                         WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2795                                  idx, unit);
2796                         wlc_hw->wlc->pub->_cnt->txuflo++;
2797                         fatal = true;
2798                 }
2799
2800                 if (fatal) {
2801                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2802                         break;
2803                 } else
2804                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2805                               intstatus);
2806         }
2807 }
2808
2809 void wlc_intrson(struct wlc_info *wlc)
2810 {
2811         struct wlc_hw_info *wlc_hw = wlc->hw;
2812         ASSERT(wlc->defmacintmask);
2813         wlc->macintmask = wlc->defmacintmask;
2814         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2815 }
2816
2817 /* callback for siutils.c, which has only wlc handler, no wl
2818  * they both check up, not only because there is no need to off/restore d11 interrupt
2819  *  but also because per-port code may require sync with valid interrupt.
2820  */
2821
2822 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2823 {
2824         if (!wlc->hw->up)
2825                 return 0;
2826
2827         return wl_intrsoff(wlc->wl);
2828 }
2829
2830 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2831 {
2832         if (!wlc->hw->up)
2833                 return;
2834
2835         wl_intrsrestore(wlc->wl, macintmask);
2836 }
2837
2838 u32 wlc_intrsoff(struct wlc_info *wlc)
2839 {
2840         struct wlc_hw_info *wlc_hw = wlc->hw;
2841         u32 macintmask;
2842
2843         if (!wlc_hw->clk)
2844                 return 0;
2845
2846         macintmask = wlc->macintmask;   /* isr can still happen */
2847
2848         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2849         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
2850         udelay(1);              /* ensure int line is no longer driven */
2851         wlc->macintmask = 0;
2852
2853         /* return previous macintmask; resolve race between us and our isr */
2854         return wlc->macintstatus ? 0 : macintmask;
2855 }
2856
2857 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2858 {
2859         struct wlc_hw_info *wlc_hw = wlc->hw;
2860         if (!wlc_hw->clk)
2861                 return;
2862
2863         wlc->macintmask = macintmask;
2864         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2865 }
2866
2867 static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2868 {
2869         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2870
2871         if (on) {
2872                 /* suspend tx fifos */
2873                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2874                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2875                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2876                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2877
2878                 /* zero the address match register so we do not send ACKs */
2879                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2880                                        null_ether_addr);
2881         } else {
2882                 /* resume tx fifos */
2883                 if (!wlc_hw->wlc->tx_suspended) {
2884                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2885                 }
2886                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2887                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2888                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2889
2890                 /* Restore address */
2891                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2892                                        wlc_hw->etheraddr);
2893         }
2894
2895         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2896
2897         if (on)
2898                 wlc_ucode_mute_override_set(wlc_hw);
2899         else
2900                 wlc_ucode_mute_override_clear(wlc_hw);
2901 }
2902
2903 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
2904 {
2905         if (fifo >= NFIFO)
2906                 return BCME_RANGE;
2907
2908         *blocks = wlc_hw->xmtfifo_sz[fifo];
2909
2910         return 0;
2911 }
2912
2913 /* wlc_bmac_tx_fifo_suspended:
2914  * Check the MAC's tx suspend status for a tx fifo.
2915  *
2916  * When the MAC acknowledges a tx suspend, it indicates that no more
2917  * packets will be transmitted out the radio. This is independent of
2918  * DMA channel suspension---the DMA may have finished suspending, or may still
2919  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2920  * request.
2921  */
2922 static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2923 {
2924         /* check that a suspend has been requested and is no longer pending */
2925
2926         /*
2927          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2928          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2929          * chnstatus register.
2930          * The tx fifo suspend completion is independent of the DMA suspend completion and
2931          *   may be acked before or after the DMA is suspended.
2932          */
2933         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2934             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
2935              (1 << tx_fifo)) == 0)
2936                 return true;
2937
2938         return false;
2939 }
2940
2941 static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2942 {
2943         u8 fifo = 1 << tx_fifo;
2944
2945         /* Two clients of this code, 11h Quiet period and scanning. */
2946
2947         /* only suspend if not already suspended */
2948         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2949                 return;
2950
2951         /* force the core awake only if not already */
2952         if (wlc_hw->suspended_fifos == 0)
2953                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
2954
2955         wlc_hw->suspended_fifos |= fifo;
2956
2957         if (wlc_hw->di[tx_fifo]) {
2958                 /* Suspending AMPDU transmissions in the middle can cause underflow
2959                  * which may result in mismatch between ucode and driver
2960                  * so suspend the mac before suspending the FIFO
2961                  */
2962                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2963                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
2964
2965                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2966
2967                 if (WLC_PHY_11N_CAP(wlc_hw->band))
2968                         wlc_enable_mac(wlc_hw->wlc);
2969         }
2970 }
2971
2972 static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
2973 {
2974         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
2975          * here for PIO otherwise the watchdog will catch the inconsistency and fire
2976          */
2977         /* Two clients of this code, 11h Quiet period and scanning. */
2978         if (wlc_hw->di[tx_fifo])
2979                 dma_txresume(wlc_hw->di[tx_fifo]);
2980
2981         /* allow core to sleep again */
2982         if (wlc_hw->suspended_fifos == 0)
2983                 return;
2984         else {
2985                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2986                 if (wlc_hw->suspended_fifos == 0)
2987                         wlc_ucode_wake_override_clear(wlc_hw,
2988                                                       WLC_WAKE_OVERRIDE_TXFIFO);
2989         }
2990 }
2991
2992 /*
2993  * Read and clear macintmask and macintstatus and intstatus registers.
2994  * This routine should be called with interrupts off
2995  * Return:
2996  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2997  *   0 if the interrupt is not for us, or we are in some special cases;
2998  *   device interrupt status bits otherwise.
2999  */
3000 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3001 {
3002         struct wlc_hw_info *wlc_hw = wlc->hw;
3003         d11regs_t *regs = wlc_hw->regs;
3004         u32 macintstatus;
3005         struct osl_info *osh;
3006
3007         osh = wlc_hw->osh;
3008
3009         /* macintstatus includes a DMA interrupt summary bit */
3010         macintstatus = R_REG(osh, &regs->macintstatus);
3011
3012         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
3013
3014         /* detect cardbus removed, in power down(suspend) and in reset */
3015         if (DEVICEREMOVED(wlc))
3016                 return -1;
3017
3018         /* DEVICEREMOVED succeeds even when the core is still resetting,
3019          * handle that case here.
3020          */
3021         if (macintstatus == 0xffffffff)
3022                 return 0;
3023
3024         /* defer unsolicited interrupts */
3025         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3026
3027         /* if not for us */
3028         if (macintstatus == 0)
3029                 return 0;
3030
3031         /* interrupts are already turned off for CFE build
3032          * Caution: For CFE Turning off the interrupts again has some undesired
3033          * consequences
3034          */
3035         /* turn off the interrupts */
3036         W_REG(osh, &regs->macintmask, 0);
3037         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3038         wlc->macintmask = 0;
3039
3040         /* clear device interrupts */
3041         W_REG(osh, &regs->macintstatus, macintstatus);
3042
3043         /* MI_DMAINT is indication of non-zero intstatus */
3044         if (macintstatus & MI_DMAINT) {
3045                 /*
3046                  * only fifo interrupt enabled is I_RI in RX_FIFO. If
3047                  * MI_DMAINT is set, assume it is set and clear the interrupt.
3048                  */
3049                 W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3050                       DEF_RXINTMASK);
3051         }
3052
3053         return macintstatus;
3054 }
3055
3056 /* Update wlc->macintstatus and wlc->intstatus[]. */
3057 /* Return true if they are updated successfully. false otherwise */
3058 bool wlc_intrsupd(struct wlc_info *wlc)
3059 {
3060         u32 macintstatus;
3061
3062         ASSERT(wlc->macintstatus != 0);
3063
3064         /* read and clear macintstatus and intstatus registers */
3065         macintstatus = wlc_intstatus(wlc, false);
3066
3067         /* device is removed */
3068         if (macintstatus == 0xffffffff)
3069                 return false;
3070
3071         /* update interrupt status in software */
3072         wlc->macintstatus |= macintstatus;
3073
3074         return true;
3075 }
3076
3077 /*
3078  * First-level interrupt processing.
3079  * Return true if this was our interrupt, false otherwise.
3080  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3081  * false otherwise.
3082  */
3083 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3084 {
3085         struct wlc_hw_info *wlc_hw = wlc->hw;
3086         u32 macintstatus;
3087
3088         *wantdpc = false;
3089
3090         if (!wlc_hw->up || !wlc->macintmask)
3091                 return false;
3092
3093         /* read and clear macintstatus and intstatus registers */
3094         macintstatus = wlc_intstatus(wlc, true);
3095
3096         if (macintstatus == 0xffffffff)
3097                 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3098
3099         /* it is not for us */
3100         if (macintstatus == 0)
3101                 return false;
3102
3103         *wantdpc = true;
3104
3105         /* save interrupt status bits */
3106         ASSERT(wlc->macintstatus == 0);
3107         wlc->macintstatus = macintstatus;
3108
3109         return true;
3110
3111 }
3112
3113 static bool BCMFASTPATH
3114 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3115 {
3116         /* discard intermediate indications for ucode with one legitimate case:
3117          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3118          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3119          *   transmission count)
3120          */
3121         if (!(txs->status & TX_STATUS_AMPDU)
3122             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3123                 return false;
3124         }
3125
3126         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3127 }
3128
3129 /* process tx completion events in BMAC
3130  * Return true if more tx status need to be processed. false otherwise.
3131  */
3132 static bool BCMFASTPATH
3133 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3134 {
3135         bool morepending = false;
3136         struct wlc_info *wlc = wlc_hw->wlc;
3137         d11regs_t *regs;
3138         struct osl_info *osh;
3139         tx_status_t txstatus, *txs;
3140         u32 s1, s2;
3141         uint n = 0;
3142         /*
3143          * Param 'max_tx_num' indicates max. # tx status to process before
3144          * break out.
3145          */
3146         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3147
3148         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3149
3150         txs = &txstatus;
3151         regs = wlc_hw->regs;
3152         osh = wlc_hw->osh;
3153         while (!(*fatal)
3154                && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3155
3156                 if (s1 == 0xffffffff) {
3157                         WL_ERROR("wl%d: %s: dead chip\n",
3158                                  wlc_hw->unit, __func__);
3159                         ASSERT(s1 != 0xffffffff);
3160                         return morepending;
3161                 }
3162
3163                 s2 = R_REG(osh, &regs->frmtxstatus2);
3164
3165                 txs->status = s1 & TXS_STATUS_MASK;
3166                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3167                 txs->sequence = s2 & TXS_SEQ_MASK;
3168                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3169                 txs->lasttxtime = 0;
3170
3171                 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3172
3173                 /* !give others some time to run! */
3174                 if (++n >= max_tx_num)
3175                         break;
3176         }
3177
3178         if (*fatal)
3179                 return 0;
3180
3181         if (n >= max_tx_num)
3182                 morepending = true;
3183
3184         if (!pktq_empty(&wlc->active_queue->q))
3185                 wlc_send_q(wlc, wlc->active_queue);
3186
3187         return morepending;
3188 }
3189
3190 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3191 {
3192         struct wlc_hw_info *wlc_hw = wlc->hw;
3193         d11regs_t *regs = wlc_hw->regs;
3194         u32 mc, mi;
3195         struct osl_info *osh;
3196
3197         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3198                  wlc_hw->unit, wlc_hw->band->bandunit);
3199
3200         /*
3201          * Track overlapping suspend requests
3202          */
3203         wlc_hw->mac_suspend_depth++;
3204         if (wlc_hw->mac_suspend_depth > 1)
3205                 return;
3206
3207         osh = wlc_hw->osh;
3208
3209         /* force the core awake */
3210         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3211
3212         mc = R_REG(osh, &regs->maccontrol);
3213
3214         if (mc == 0xffffffff) {
3215                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3216                 wl_down(wlc->wl);
3217                 return;
3218         }
3219         ASSERT(!(mc & MCTL_PSM_JMP_0));
3220         ASSERT(mc & MCTL_PSM_RUN);
3221         ASSERT(mc & MCTL_EN_MAC);
3222
3223         mi = R_REG(osh, &regs->macintstatus);
3224         if (mi == 0xffffffff) {
3225                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3226                 wl_down(wlc->wl);
3227                 return;
3228         }
3229         ASSERT(!(mi & MI_MACSSPNDD));
3230
3231         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3232
3233         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3234                  WLC_MAX_MAC_SUSPEND);
3235
3236         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3237                 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3238                          wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3239                 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3240                          wlc_hw->unit,
3241                          R_REG(osh, &regs->psmdebug),
3242                          R_REG(osh, &regs->phydebug),
3243                          R_REG(osh, &regs->psm_brc));
3244         }
3245
3246         mc = R_REG(osh, &regs->maccontrol);
3247         if (mc == 0xffffffff) {
3248                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3249                 wl_down(wlc->wl);
3250                 return;
3251         }
3252         ASSERT(!(mc & MCTL_PSM_JMP_0));
3253         ASSERT(mc & MCTL_PSM_RUN);
3254         ASSERT(!(mc & MCTL_EN_MAC));
3255 }
3256
3257 void wlc_enable_mac(struct wlc_info *wlc)
3258 {
3259         struct wlc_hw_info *wlc_hw = wlc->hw;
3260         d11regs_t *regs = wlc_hw->regs;
3261         u32 mc, mi;
3262         struct osl_info *osh;
3263
3264         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3265                  wlc_hw->unit, wlc->band->bandunit);
3266
3267         /*
3268          * Track overlapping suspend requests
3269          */
3270         ASSERT(wlc_hw->mac_suspend_depth > 0);
3271         wlc_hw->mac_suspend_depth--;
3272         if (wlc_hw->mac_suspend_depth > 0)
3273                 return;
3274
3275         osh = wlc_hw->osh;
3276
3277         mc = R_REG(osh, &regs->maccontrol);
3278         ASSERT(!(mc & MCTL_PSM_JMP_0));
3279         ASSERT(!(mc & MCTL_EN_MAC));
3280         ASSERT(mc & MCTL_PSM_RUN);
3281
3282         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3283         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3284
3285         mc = R_REG(osh, &regs->maccontrol);
3286         ASSERT(!(mc & MCTL_PSM_JMP_0));
3287         ASSERT(mc & MCTL_EN_MAC);
3288         ASSERT(mc & MCTL_PSM_RUN);
3289
3290         mi = R_REG(osh, &regs->macintstatus);
3291         ASSERT(!(mi & MI_MACSSPNDD));
3292
3293         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3294 }
3295
3296 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3297 {
3298         u8 rate;
3299         u8 rates[8] = {
3300                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3301                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3302         };
3303         u16 entry_ptr;
3304         u16 pctl1;
3305         uint i;
3306
3307         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3308                 return;
3309
3310         /* walk the phy rate table and update the entries */
3311         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3312                 rate = rates[i];
3313
3314                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3315
3316                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3317                 pctl1 =
3318                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3319
3320                 /* modify the value */
3321                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3322                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3323
3324                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3325                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3326                                    pctl1);
3327         }
3328 }
3329
3330 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3331 {
3332         uint i;
3333         u8 plcp_rate = 0;
3334         struct plcp_signal_rate_lookup {
3335                 u8 rate;
3336                 u8 signal_rate;
3337         };
3338         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3339         const struct plcp_signal_rate_lookup rate_lookup[] = {
3340                 {WLC_RATE_6M, 0xB},
3341                 {WLC_RATE_9M, 0xF},
3342                 {WLC_RATE_12M, 0xA},
3343                 {WLC_RATE_18M, 0xE},
3344                 {WLC_RATE_24M, 0x9},
3345                 {WLC_RATE_36M, 0xD},
3346                 {WLC_RATE_48M, 0x8},
3347                 {WLC_RATE_54M, 0xC}
3348         };
3349
3350         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3351                 if (rate == rate_lookup[i].rate) {
3352                         plcp_rate = rate_lookup[i].signal_rate;
3353                         break;
3354                 }
3355         }
3356
3357         /* Find the SHM pointer to the rate table entry by looking in the
3358          * Direct-map Table
3359          */
3360         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3361 }
3362
3363 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3364 {
3365         wlc_hw->hw_stf_ss_opmode = stf_mode;
3366
3367         if (wlc_hw->clk)
3368                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3369 }
3370
3371 void BCMFASTPATH
3372 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3373                   u32 *tsf_h_ptr)
3374 {
3375         d11regs_t *regs = wlc_hw->regs;
3376
3377         /* read the tsf timer low, then high to get an atomic read */
3378         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3379         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3380
3381         return;
3382 }
3383
3384 static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3385 {
3386         d11regs_t *regs;
3387         u32 w, val;
3388         struct osl_info *osh;
3389
3390         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3391
3392         regs = wlc_hw->regs;
3393         osh = wlc_hw->osh;
3394
3395         /* Validate dchip register access */
3396
3397         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3398         (void)R_REG(osh, &regs->objaddr);
3399         w = R_REG(osh, &regs->objdata);
3400
3401         /* Can we write and read back a 32bit register? */
3402         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3403         (void)R_REG(osh, &regs->objaddr);
3404         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3405
3406         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3407         (void)R_REG(osh, &regs->objaddr);
3408         val = R_REG(osh, &regs->objdata);
3409         if (val != (u32) 0xaa5555aa) {
3410                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3411                          wlc_hw->unit, val);
3412                 return false;
3413         }
3414
3415         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3416         (void)R_REG(osh, &regs->objaddr);
3417         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3418
3419         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3420         (void)R_REG(osh, &regs->objaddr);
3421         val = R_REG(osh, &regs->objdata);
3422         if (val != (u32) 0x55aaaa55) {
3423                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3424                          wlc_hw->unit, val);
3425                 return false;
3426         }
3427
3428         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3429         (void)R_REG(osh, &regs->objaddr);
3430         W_REG(osh, &regs->objdata, w);
3431
3432         /* clear CFPStart */
3433         W_REG(osh, &regs->tsf_cfpstart, 0);
3434
3435         w = R_REG(osh, &regs->maccontrol);
3436         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3437             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3438                 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3439                          wlc_hw->unit, w,
3440                          (MCTL_IHR_EN | MCTL_WAKE),
3441                          (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3442                 return false;
3443         }
3444
3445         return true;
3446 }
3447
3448 #define PHYPLL_WAIT_US  100000
3449
3450 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3451 {
3452         d11regs_t *regs;
3453         struct osl_info *osh;
3454         u32 tmp;
3455
3456         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3457
3458         tmp = 0;
3459         regs = wlc_hw->regs;
3460         osh = wlc_hw->osh;
3461
3462         if (on) {
3463                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3464                         OR_REG(osh, &regs->clk_ctl_st,
3465                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3466                                 CCS_ERSRC_REQ_PHYPLL));
3467                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3468                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3469                                  PHYPLL_WAIT_US);
3470
3471                         tmp = R_REG(osh, &regs->clk_ctl_st);
3472                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3473                             (CCS_ERSRC_AVAIL_HT)) {
3474                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3475                                          __func__);
3476                                 ASSERT(0);
3477                         }
3478                 } else {
3479                         OR_REG(osh, &regs->clk_ctl_st,
3480                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3481                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3482                                   (CCS_ERSRC_AVAIL_D11PLL |
3483                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3484                                  (CCS_ERSRC_AVAIL_D11PLL |
3485                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3486
3487                         tmp = R_REG(osh, &regs->clk_ctl_st);
3488                         if ((tmp &
3489                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3490                             !=
3491                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3492                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3493                                          __func__);
3494                                 ASSERT(0);
3495                         }
3496                 }
3497         } else {
3498                 /* Since the PLL may be shared, other cores can still be requesting it;
3499                  * so we'll deassert the request but not wait for status to comply.
3500                  */
3501                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3502                 tmp = R_REG(osh, &regs->clk_ctl_st);
3503         }
3504 }
3505
3506 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3507 {
3508         bool dev_gone;
3509
3510         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3511
3512         ASSERT(!wlc_hw->up);
3513
3514         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3515
3516         if (dev_gone)
3517                 return;
3518
3519         if (wlc_hw->noreset)
3520                 return;
3521
3522         /* radio off */
3523         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3524
3525         /* turn off analog core */
3526         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3527
3528         /* turn off PHYPLL to save power */
3529         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3530
3531         /* No need to set wlc->pub->radio_active = OFF
3532          * because this function needs down capability and
3533          * radio_active is designed for BCMNODOWN.
3534          */
3535
3536         /* remove gpio controls */
3537         if (wlc_hw->ucode_dbgsel)
3538                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3539
3540         wlc_hw->clk = false;
3541         si_core_disable(wlc_hw->sih, 0);
3542         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3543 }
3544
3545 /* power both the pll and external oscillator on/off */
3546 static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3547 {
3548         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3549
3550         /* dont power down if plldown is false or we must poll hw radio disable */
3551         if (!want && wlc_hw->pllreq)
3552                 return;
3553
3554         if (wlc_hw->sih)
3555                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3556
3557         wlc_hw->sbclk = want;
3558         if (!wlc_hw->sbclk) {
3559                 wlc_hw->clk = false;
3560                 if (wlc_hw->band && wlc_hw->band->pi)
3561                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3562         }
3563 }
3564
3565 static void wlc_flushqueues(struct wlc_info *wlc)
3566 {
3567         struct wlc_hw_info *wlc_hw = wlc->hw;
3568         uint i;
3569
3570         wlc->txpend16165war = 0;
3571
3572         /* free any posted tx packets */
3573         for (i = 0; i < NFIFO; i++)
3574                 if (wlc_hw->di[i]) {
3575                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3576                         TXPKTPENDCLR(wlc, i);
3577                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3578                                  i);
3579                 }
3580
3581         /* free any posted rx packets */
3582         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3583 }
3584
3585 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3586 {
3587         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3588 }
3589
3590 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3591 {
3592         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3593 }
3594
3595 /* Set a range of shared memory to a value.
3596  * SHM 'offset' needs to be an even address and
3597  * Buffer length 'len' must be an even number of bytes
3598  */
3599 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3600 {
3601         int i;
3602
3603         /* offset and len need to be even */
3604         ASSERT((offset & 1) == 0);
3605         ASSERT((len & 1) == 0);
3606
3607         if (len <= 0)
3608                 return;
3609
3610         for (i = 0; i < len; i += 2) {
3611                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3612         }
3613 }
3614
3615 static u16
3616 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3617 {
3618         d11regs_t *regs = wlc_hw->regs;
3619         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3620         volatile u16 *objdata_hi = objdata_lo + 1;
3621         u16 v;
3622
3623         ASSERT((offset & 1) == 0);
3624
3625         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3626         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3627         if (offset & 2) {
3628                 v = R_REG(wlc_hw->osh, objdata_hi);
3629         } else {
3630                 v = R_REG(wlc_hw->osh, objdata_lo);
3631         }
3632
3633         return v;
3634 }
3635
3636 static void
3637 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3638 {
3639         d11regs_t *regs = wlc_hw->regs;
3640         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3641         volatile u16 *objdata_hi = objdata_lo + 1;
3642
3643         ASSERT((offset & 1) == 0);
3644
3645         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3646         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3647         if (offset & 2) {
3648                 W_REG(wlc_hw->osh, objdata_hi, v);
3649         } else {
3650                 W_REG(wlc_hw->osh, objdata_lo, v);
3651         }
3652 }
3653
3654 /* Copy a buffer to shared memory of specified type .
3655  * SHM 'offset' needs to be an even address and
3656  * Buffer length 'len' must be an even number of bytes
3657  * 'sel' selects the type of memory
3658  */
3659 void
3660 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3661                        int len, u32 sel)
3662 {
3663         u16 v;
3664         const u8 *p = (const u8 *)buf;
3665         int i;
3666
3667         /* offset and len need to be even */
3668         ASSERT((offset & 1) == 0);
3669         ASSERT((len & 1) == 0);
3670
3671         if (len <= 0)
3672                 return;
3673
3674         for (i = 0; i < len; i += 2) {
3675                 v = p[i] | (p[i + 1] << 8);
3676                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3677         }
3678 }
3679
3680 /* Copy a piece of shared memory of specified type to a buffer .
3681  * SHM 'offset' needs to be an even address and
3682  * Buffer length 'len' must be an even number of bytes
3683  * 'sel' selects the type of memory
3684  */
3685 void
3686 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3687                          int len, u32 sel)
3688 {
3689         u16 v;
3690         u8 *p = (u8 *) buf;
3691         int i;
3692
3693         /* offset and len need to be even */
3694         ASSERT((offset & 1) == 0);
3695         ASSERT((len & 1) == 0);
3696
3697         if (len <= 0)
3698                 return;
3699
3700         for (i = 0; i < len; i += 2) {
3701                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3702                 p[i] = v & 0xFF;
3703                 p[i + 1] = (v >> 8) & 0xFF;
3704         }
3705 }
3706
3707 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3708 {
3709         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3710                  wlc_hw->vars_size);
3711
3712         *buf = wlc_hw->vars;
3713         *len = wlc_hw->vars_size;
3714 }
3715
3716 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3717 {
3718         wlc_hw->SRL = SRL;
3719         wlc_hw->LRL = LRL;
3720
3721         /* write retry limit to SCR, shouldn't need to suspend */
3722         if (wlc_hw->up) {
3723                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3724                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3725                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3726                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
3727                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3728                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3729                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3730                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
3731         }
3732 }
3733
3734 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3735 {
3736         wlc_hw->noreset = noreset_flag;
3737 }
3738
3739 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3740 {
3741         ASSERT(req_bit);
3742
3743         if (set) {
3744                 if (mboolisset(wlc_hw->pllreq, req_bit))
3745                         return;
3746
3747                 mboolset(wlc_hw->pllreq, req_bit);
3748
3749                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3750                         if (!wlc_hw->sbclk) {
3751                                 wlc_bmac_xtal(wlc_hw, ON);
3752                         }
3753                 }
3754         } else {
3755                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3756                         return;
3757
3758                 mboolclr(wlc_hw->pllreq, req_bit);
3759
3760                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3761                         if (wlc_hw->sbclk) {
3762                                 wlc_bmac_xtal(wlc_hw, OFF);
3763                         }
3764                 }
3765         }
3766
3767         return;
3768 }
3769
3770 /* this will be true for all ai chips */
3771 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
3772 {
3773         return true;
3774 }
3775
3776 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3777 {
3778         u16 table_ptr;
3779         u8 phy_rate, index;
3780
3781         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3782         /* XXX4321 fixup needed ? */
3783         if (IS_OFDM(rate))
3784                 table_ptr = M_RT_DIRMAP_A;
3785         else
3786                 table_ptr = M_RT_DIRMAP_B;
3787
3788         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3789          * the index into the rate table.
3790          */
3791         phy_rate = rate_info[rate] & RATE_MASK;
3792         index = phy_rate & 0xf;
3793
3794         /* Find the SHM pointer to the rate table entry by looking in the
3795          * Direct-map Table
3796          */
3797         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
3798 }
3799
3800 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
3801 {
3802         wlc_hw->antsel_avail = antsel_avail;
3803 }