2 include/comedi.h (installed as /usr/include/comedi.h)
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU Lesser General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #define COMEDI_MAJORVERSION 0
28 #define COMEDI_MINORVERSION 7
29 #define COMEDI_MICROVERSION 76
30 #define VERSION "0.7.76"
32 /* comedi's major device number */
33 #define COMEDI_MAJOR 98
36 maximum number of minor devices. This can be increased, although
37 kernel structures are currently statically allocated, thus you
38 don't want this to be much more than you actually use.
40 #define COMEDI_NDEVICES 16
42 /* number of config options in the config structure */
43 #define COMEDI_NDEVCONFOPTS 32
44 /*length of nth chunk of firmware data*/
45 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25
46 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26
47 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27
48 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28
49 /* most significant 32 bits of pointer address (if needed) */
50 #define COMEDI_DEVCONF_AUX_DATA_HI 29
51 /* least significant 32 bits of pointer address */
52 #define COMEDI_DEVCONF_AUX_DATA_LO 30
53 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */
55 /* max length of device and driver names */
56 #define COMEDI_NAMELEN 20
58 /* packs and unpacks a channel/range number */
60 #define CR_PACK(chan, rng, aref) \
61 ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
62 #define CR_PACK_FLAGS(chan, range, aref, flags) \
63 (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
65 #define CR_CHAN(a) ((a)&0xffff)
66 #define CR_RANGE(a) (((a)>>16)&0xff)
67 #define CR_AREF(a) (((a)>>24)&0x03)
69 #define CR_FLAGS_MASK 0xfc000000
70 #define CR_ALT_FILTER (1<<26)
71 #define CR_DITHER CR_ALT_FILTER
72 #define CR_DEGLITCH CR_ALT_FILTER
73 #define CR_ALT_SOURCE (1<<27)
74 #define CR_EDGE (1<<30)
75 #define CR_INVERT (1<<31)
77 #define AREF_GROUND 0x00 /* analog ref = analog ground */
78 #define AREF_COMMON 0x01 /* analog ref = analog common */
79 #define AREF_DIFF 0x02 /* analog ref = differential */
80 #define AREF_OTHER 0x03 /* analog ref = other (undefined) */
82 /* counters -- these are arbitrary values */
83 #define GPCT_RESET 0x0001
84 #define GPCT_SET_SOURCE 0x0002
85 #define GPCT_SET_GATE 0x0004
86 #define GPCT_SET_DIRECTION 0x0008
87 #define GPCT_SET_OPERATION 0x0010
88 #define GPCT_ARM 0x0020
89 #define GPCT_DISARM 0x0040
90 #define GPCT_GET_INT_CLK_FRQ 0x0080
92 #define GPCT_INT_CLOCK 0x0001
93 #define GPCT_EXT_PIN 0x0002
94 #define GPCT_NO_GATE 0x0004
95 #define GPCT_UP 0x0008
96 #define GPCT_DOWN 0x0010
97 #define GPCT_HWUD 0x0020
98 #define GPCT_SIMPLE_EVENT 0x0040
99 #define GPCT_SINGLE_PERIOD 0x0080
100 #define GPCT_SINGLE_PW 0x0100
101 #define GPCT_CONT_PULSE_OUT 0x0200
102 #define GPCT_SINGLE_PULSE_OUT 0x0400
106 #define INSN_MASK_WRITE 0x8000000
107 #define INSN_MASK_READ 0x4000000
108 #define INSN_MASK_SPECIAL 0x2000000
110 #define INSN_READ (0 | INSN_MASK_READ)
111 #define INSN_WRITE (1 | INSN_MASK_WRITE)
112 #define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE)
113 #define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE)
114 #define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
115 #define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
116 #define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
119 /* These flags are used in comedi_trig structures */
121 #define TRIG_BOGUS 0x0001 /* do the motions */
122 #define TRIG_DITHER 0x0002 /* enable dithering */
123 #define TRIG_DEGLITCH 0x0004 /* enable deglitching */
124 /*#define TRIG_RT 0x0008 *//* perform op in real time */
125 #define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */
126 #define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */
127 /*#define TRIG_WRITE 0x0040*//* write to bidirectional devices */
130 /* These flags are used in comedi_cmd structures */
132 /* try to use a real-time interrupt while performing command */
133 #define CMDF_PRIORITY 0x00000008
135 #define TRIG_RT CMDF_PRIORITY /* compatibility definition */
137 #define CMDF_WRITE 0x00000040
138 #define TRIG_WRITE CMDF_WRITE /* compatibility definition */
140 #define CMDF_RAWDATA 0x00000080
142 #define COMEDI_EV_START 0x00040000
143 #define COMEDI_EV_SCAN_BEGIN 0x00080000
144 #define COMEDI_EV_CONVERT 0x00100000
145 #define COMEDI_EV_SCAN_END 0x00200000
146 #define COMEDI_EV_STOP 0x00400000
148 #define TRIG_ROUND_MASK 0x00030000
149 #define TRIG_ROUND_NEAREST 0x00000000
150 #define TRIG_ROUND_DOWN 0x00010000
151 #define TRIG_ROUND_UP 0x00020000
152 #define TRIG_ROUND_UP_NEXT 0x00030000
154 /* trigger sources */
156 #define TRIG_ANY 0xffffffff
157 #define TRIG_INVALID 0x00000000
159 #define TRIG_NONE 0x00000001 /* never trigger */
160 #define TRIG_NOW 0x00000002 /* trigger now + N ns */
161 #define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */
162 #define TRIG_TIME 0x00000008 /* trigger at time N ns */
163 #define TRIG_TIMER 0x00000010 /* trigger at rate N ns */
164 #define TRIG_COUNT 0x00000020 /* trigger when count reaches N */
165 #define TRIG_EXT 0x00000040 /* trigger on external signal N */
166 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
167 #define TRIG_OTHER 0x00000100 /* driver defined */
169 /* subdevice flags */
171 #define SDF_BUSY 0x0001 /* device is busy */
172 #define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */
173 #define SDF_LOCKED 0x0004 /* subdevice is locked */
174 #define SDF_LOCK_OWNER 0x0008 /* you own lock */
175 #define SDF_MAXDATA 0x0010 /* maxdata depends on channel */
176 #define SDF_FLAGS 0x0020 /* flags depend on channel */
177 #define SDF_RANGETYPE 0x0040 /* range type depends on channel */
178 #define SDF_MODE0 0x0080 /* can do mode 0 */
179 #define SDF_MODE1 0x0100 /* can do mode 1 */
180 #define SDF_MODE2 0x0200 /* can do mode 2 */
181 #define SDF_MODE3 0x0400 /* can do mode 3 */
182 #define SDF_MODE4 0x0800 /* can do mode 4 */
183 #define SDF_CMD 0x1000 /* can do commands (deprecated) */
184 #define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */
185 #define SDF_CMD_WRITE 0x4000 /* can do output commands */
186 #define SDF_CMD_READ 0x8000 /* can do input commands */
188 /* subdevice can be read (e.g. analog input) */
189 #define SDF_READABLE 0x00010000
190 /* subdevice can be written (e.g. analog output) */
191 #define SDF_WRITABLE 0x00020000
192 #define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */
193 /* subdevice does not have externally visible lines */
194 #define SDF_INTERNAL 0x00040000
195 #define SDF_GROUND 0x00100000 /* can do aref=ground */
196 #define SDF_COMMON 0x00200000 /* can do aref=common */
197 #define SDF_DIFF 0x00400000 /* can do aref=diff */
198 #define SDF_OTHER 0x00800000 /* can do aref=other */
199 #define SDF_DITHER 0x01000000 /* can do dithering */
200 #define SDF_DEGLITCH 0x02000000 /* can do deglitching */
201 #define SDF_MMAP 0x04000000 /* can do mmap() */
202 #define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */
203 #define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */
204 #define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */
205 /* re recyle these flags for PWM */
206 #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */
207 #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */
209 /* subdevice types */
211 enum comedi_subdevice_type {
212 COMEDI_SUBD_UNUSED, /* unused by driver */
213 COMEDI_SUBD_AI, /* analog input */
214 COMEDI_SUBD_AO, /* analog output */
215 COMEDI_SUBD_DI, /* digital input */
216 COMEDI_SUBD_DO, /* digital output */
217 COMEDI_SUBD_DIO, /* digital input/output */
218 COMEDI_SUBD_COUNTER, /* counter */
219 COMEDI_SUBD_TIMER, /* timer */
220 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */
221 COMEDI_SUBD_CALIB, /* calibration DACs */
222 COMEDI_SUBD_PROC, /* processor, DSP */
223 COMEDI_SUBD_SERIAL, /* serial IO */
224 COMEDI_SUBD_PWM /* PWM */
227 /* configuration instructions */
229 enum configuration_ids {
230 INSN_CONFIG_DIO_INPUT = 0,
231 INSN_CONFIG_DIO_OUTPUT = 1,
232 INSN_CONFIG_DIO_OPENDRAIN = 2,
233 INSN_CONFIG_ANALOG_TRIG = 16,
234 /* INSN_CONFIG_WAVEFORM = 17, */
235 /* INSN_CONFIG_TRIG = 18, */
236 /* INSN_CONFIG_COUNTER = 19, */
237 INSN_CONFIG_ALT_SOURCE = 20,
238 INSN_CONFIG_DIGITAL_TRIG = 21,
239 INSN_CONFIG_BLOCK_SIZE = 22,
240 INSN_CONFIG_TIMER_1 = 23,
241 INSN_CONFIG_FILTER = 24,
242 INSN_CONFIG_CHANGE_NOTIFY = 25,
244 INSN_CONFIG_SERIAL_CLOCK = 26, /*ALPHA*/
245 INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
246 INSN_CONFIG_DIO_QUERY = 28,
247 INSN_CONFIG_PWM_OUTPUT = 29,
248 INSN_CONFIG_GET_PWM_OUTPUT = 30,
249 INSN_CONFIG_ARM = 31,
250 INSN_CONFIG_DISARM = 32,
251 INSN_CONFIG_GET_COUNTER_STATUS = 33,
252 INSN_CONFIG_RESET = 34,
253 /* Use CTR as single pulsegenerator */
254 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001,
255 /* Use CTR as pulsetraingenerator */
256 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,
257 /* Use the counter as encoder */
258 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,
259 INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */
260 INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */
261 /* Set master clock source */
262 INSN_CONFIG_SET_CLOCK_SRC = 2003,
263 INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */
264 INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */
265 /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */
266 /* Get size in bytes of subdevice's on-board fifos used during
267 * streaming input/output */
268 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,
269 INSN_CONFIG_SET_COUNTER_MODE = 4097,
270 /* INSN_CONFIG_8254_SET_MODE is deprecated */
271 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,
272 INSN_CONFIG_8254_READ_STATUS = 4098,
273 INSN_CONFIG_SET_ROUTING = 4099,
274 INSN_CONFIG_GET_ROUTING = 4109,
276 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */
277 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */
278 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */
279 /* sets H bridge: duty cycle and sign bit for a relay at the
281 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,
282 /* gets H bridge data: duty cycle and the sign bit */
283 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004
287 * Settings for INSN_CONFIG_DIGITAL_TRIG:
288 * data[0] = INSN_CONFIG_DIGITAL_TRIG
289 * data[1] = trigger ID
290 * data[2] = configuration operation
291 * data[3] = configuration parameter 1
292 * data[4] = configuration parameter 2
293 * data[5] = configuration parameter 3
295 * operation parameter 1 parameter 2 parameter 3
296 * --------------------------------- ----------- ----------- -----------
297 * COMEDI_DIGITAL_TRIG_DISABLE
298 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES left-shift rising-edges falling-edges
299 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS left-shift high-levels low-levels
301 * COMEDI_DIGITAL_TRIG_DISABLE returns the trigger to its default, inactive,
302 * unconfigured state.
304 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES sets the rising and/or falling edge inputs
305 * that each can fire the trigger.
307 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS sets a combination of high and/or low
308 * level inputs that can fire the trigger.
310 * "left-shift" is useful if the trigger has more than 32 inputs to specify the
311 * first input for this configuration.
313 * Some sequences of INSN_CONFIG_DIGITAL_TRIG instructions may have a (partly)
314 * accumulative effect, depending on the low-level driver. This is useful
315 * when setting up a trigger that has more than 32 inputs or has a combination
316 * of edge and level triggered inputs.
318 enum comedi_digital_trig_op {
319 COMEDI_DIGITAL_TRIG_DISABLE = 0,
320 COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1,
321 COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2
324 enum comedi_io_direction {
330 enum comedi_support_level {
331 COMEDI_UNKNOWN_SUPPORT = 0,
339 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
340 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
341 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
342 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
343 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
344 #define COMEDI_LOCK _IO(CIO, 5)
345 #define COMEDI_UNLOCK _IO(CIO, 6)
346 #define COMEDI_CANCEL _IO(CIO, 7)
347 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
348 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
349 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
350 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
351 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
352 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
353 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
354 #define COMEDI_POLL _IO(CIO, 15)
359 unsigned int subdev; /* subdevice */
360 unsigned int mode; /* mode */
362 unsigned int n_chan; /* number of channels */
363 unsigned int *chanlist; /* channel/range list */
364 short *data; /* data list, size depends on subd flags */
365 unsigned int n; /* number of scans */
366 unsigned int trigsrc;
367 unsigned int trigvar;
368 unsigned int trigvar1;
369 unsigned int data_len;
370 unsigned int unused[3];
376 unsigned int __user *data;
378 unsigned int chanspec;
379 unsigned int unused[3];
382 struct comedi_insnlist {
383 unsigned int n_insns;
384 struct comedi_insn __user *insns;
391 unsigned int start_src;
392 unsigned int start_arg;
394 unsigned int scan_begin_src;
395 unsigned int scan_begin_arg;
397 unsigned int convert_src;
398 unsigned int convert_arg;
400 unsigned int scan_end_src;
401 unsigned int scan_end_arg;
403 unsigned int stop_src;
404 unsigned int stop_arg;
406 unsigned int *chanlist; /* channel/range list */
407 unsigned int chanlist_len;
409 short __user *data; /* data list, size depends on subd flags */
410 unsigned int data_len;
413 struct comedi_chaninfo {
415 unsigned int __user *maxdata_list;
416 unsigned int __user *flaglist;
417 unsigned int __user *rangelist;
418 unsigned int unused[4];
421 struct comedi_rangeinfo {
422 unsigned int range_type;
423 void __user *range_ptr;
426 struct comedi_krange {
427 int min; /* fixed point, multiply by 1e-6 */
428 int max; /* fixed point, multiply by 1e-6 */
432 struct comedi_subdinfo {
435 unsigned int subd_flags;
436 unsigned int timer_type;
437 unsigned int len_chanlist;
438 unsigned int maxdata;
439 unsigned int flags; /* channel flags */
440 unsigned int range_type; /* lookup in kernel */
441 unsigned int settling_time_0;
442 /* see support_level enum for values */
443 unsigned insn_bits_support;
444 unsigned int unused[8];
447 struct comedi_devinfo {
448 unsigned int version_code;
449 unsigned int n_subdevs;
450 char driver_name[COMEDI_NAMELEN];
451 char board_name[COMEDI_NAMELEN];
457 struct comedi_devconfig {
458 char board_name[COMEDI_NAMELEN];
459 int options[COMEDI_NDEVCONFOPTS];
462 struct comedi_bufconfig {
463 unsigned int subdevice;
466 unsigned int maximum_size;
469 unsigned int unused[4];
472 struct comedi_bufinfo {
473 unsigned int subdevice;
474 unsigned int bytes_read;
476 unsigned int buf_write_ptr;
477 unsigned int buf_read_ptr;
478 unsigned int buf_write_count;
479 unsigned int buf_read_count;
481 unsigned int bytes_written;
483 unsigned int unused[4];
488 #define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff))
490 #define RANGE_OFFSET(a) (((a)>>16)&0xffff)
491 #define RANGE_LENGTH(b) ((b)&0xffff)
493 #define RF_UNIT(flags) ((flags)&0xff)
494 #define RF_EXTERNAL (1<<8)
500 #define COMEDI_MIN_SPEED ((unsigned int)0xffffffff)
503 /* only relevant to kernel modules. */
505 #define COMEDI_CB_EOS 1 /* end of scan */
506 #define COMEDI_CB_EOA 2 /* end of acquisition/output */
507 #define COMEDI_CB_BLOCK 4 /* data has arrived:
508 * wakes up read() / write() */
509 #define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */
510 #define COMEDI_CB_ERROR 16 /* card error during acquisition */
511 #define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */
513 /**********************************************************/
514 /* everything after this line is ALPHA */
515 /**********************************************************/
518 8254 specific configuration.
520 It supports two config commands:
522 0 ID: INSN_CONFIG_SET_COUNTER_MODE
524 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
526 I8254_BCD, I8254_BINARY
528 0 ID: INSN_CONFIG_8254_READ_STATUS
529 1 <-- Status byte returned here.
532 B5 - B0 Current mode.
537 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
538 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
539 I8254_MODE2 = (2 << 1), /* Rate generator */
540 I8254_MODE3 = (3 << 1), /* Square wave mode */
541 I8254_MODE4 = (4 << 1), /* Software triggered strobe */
542 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe
544 I8254_BCD = 1, /* use binary-coded decimal instead of binary
545 * (pretty useless) */
549 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
551 if (pfi_channel < 10)
552 return 0x1 + pfi_channel;
554 return 0xb + pfi_channel;
557 static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
559 if (rtsi_channel < 7)
560 return 0xb + rtsi_channel;
565 /* mode bits for NI general-purpose counters, set with
566 * INSN_CONFIG_SET_COUNTER_MODE */
567 #define NI_GPCT_COUNTING_MODE_SHIFT 16
568 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
569 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
570 enum ni_gpct_mode_bits {
571 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
572 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
573 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
574 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
575 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
576 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
577 NI_GPCT_STOP_MODE_MASK = 0x60,
578 NI_GPCT_STOP_ON_GATE_BITS = 0x00,
579 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
580 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
581 NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
582 NI_GPCT_OUTPUT_MODE_MASK = 0x300,
583 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
584 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
585 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
586 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
587 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
588 NI_GPCT_DISARM_AT_TC_BITS = 0x400,
589 NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
590 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
591 NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
592 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
593 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
594 NI_GPCT_COUNTING_MODE_NORMAL_BITS =
595 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
596 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
597 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
598 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
599 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
600 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
601 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
602 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
603 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
604 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
605 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
606 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
607 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
608 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
609 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
610 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
611 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
612 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
613 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
614 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
615 NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
616 NI_GPCT_COUNTING_DIRECTION_MASK =
617 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
618 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
619 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
620 NI_GPCT_COUNTING_DIRECTION_UP_BITS =
621 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
622 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
623 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
624 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
625 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
626 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
627 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
628 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
629 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
630 NI_GPCT_OR_GATE_BIT = 0x10000000,
631 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
634 /* Bits for setting a clock source with
635 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
636 enum ni_gpct_clock_source_bits {
637 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
638 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
639 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
640 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
641 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
642 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
643 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
644 /* NI 660x-specific */
645 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,
646 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
647 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
648 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
649 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
650 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
651 /* divide source by 2 */
652 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000,
653 /* divide source by 8 */
654 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,
655 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
657 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
659 /* NI 660x-specific */
662 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
666 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
668 /* no pfi on NI 660x */
672 /* Possibilities for setting a gate source with
673 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
674 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
675 enum ni_gpct_gate_select {
677 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
678 NI_GPCT_AI_START2_GATE_SELECT = 0x12,
679 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
680 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
681 NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
682 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
683 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
684 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
685 /* more gates for 660x */
686 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
687 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
688 /* more gates for 660x "second gate" */
689 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
690 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
691 /* m-series "second gate" sources are unknown,
692 * we should add them here with an offset of 0x300 when
694 NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
696 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
700 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
702 return NI_USUAL_RTSI_SELECT(n);
704 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
706 return NI_USUAL_PFI_SELECT(n);
708 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
713 /* Possibilities for setting a source with
714 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
715 enum ni_gpct_other_index {
716 NI_GPCT_SOURCE_ENCODER_A,
717 NI_GPCT_SOURCE_ENCODER_B,
718 NI_GPCT_SOURCE_ENCODER_Z
720 enum ni_gpct_other_select {
722 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
723 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
725 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
727 return NI_USUAL_PFI_SELECT(n);
730 /* start sources for ni general-purpose counters for use with
732 enum ni_gpct_arm_source {
733 NI_GPCT_ARM_IMMEDIATE = 0x0,
734 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter
735 * and the adjacent paired
736 * counter simultaneously */
737 /* NI doesn't document bits for selecting hardware arm triggers.
738 * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
739 * significant bits (3 bits for 660x or 5 bits for m-series)
740 * through to the hardware. This will at least allow someone to
741 * figure out what the bits do later. */
742 NI_GPCT_ARM_UNKNOWN = 0x1000,
745 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
746 enum ni_gpct_filter_select {
747 NI_GPCT_FILTER_OFF = 0x0,
748 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
749 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
750 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
751 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
752 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
753 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
756 /* PFI digital filtering options for ni m-series for use with
757 * INSN_CONFIG_FILTER. */
758 enum ni_pfi_filter_select {
759 NI_PFI_FILTER_OFF = 0x0,
760 NI_PFI_FILTER_125ns = 0x1,
761 NI_PFI_FILTER_6425ns = 0x2,
762 NI_PFI_FILTER_2550us = 0x3
765 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
766 enum ni_mio_clock_source {
767 NI_MIO_INTERNAL_CLOCK = 0,
768 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use
769 NI_MIO_PLL_RTSI_CLOCK() */
770 /* the NI_MIO_PLL_* sources are m-series only */
771 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
772 NI_MIO_PLL_PXI10_CLOCK = 3,
773 NI_MIO_PLL_RTSI0_CLOCK = 4
775 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
777 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
780 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
781 The numbers assigned are not arbitrary, they correspond to the bits required
782 to program the board. */
783 enum ni_rtsi_routing {
784 NI_RTSI_OUTPUT_ADR_START1 = 0,
785 NI_RTSI_OUTPUT_ADR_START2 = 1,
786 NI_RTSI_OUTPUT_SCLKG = 2,
787 NI_RTSI_OUTPUT_DACUPDN = 3,
788 NI_RTSI_OUTPUT_DA_START1 = 4,
789 NI_RTSI_OUTPUT_G_SRC0 = 5,
790 NI_RTSI_OUTPUT_G_GATE0 = 6,
791 NI_RTSI_OUTPUT_RGOUT0 = 7,
792 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
793 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI
796 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
798 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
801 /* Signals which can be routed to an NI PFI pin on an m-series board with
802 * INSN_CONFIG_SET_ROUTING. These numbers are also returned by
803 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
804 * cannot be changed. The numbers assigned are not arbitrary, they correspond
805 * to the bits required to program the board. */
806 enum ni_pfi_routing {
807 NI_PFI_OUTPUT_PFI_DEFAULT = 0,
808 NI_PFI_OUTPUT_AI_START1 = 1,
809 NI_PFI_OUTPUT_AI_START2 = 2,
810 NI_PFI_OUTPUT_AI_CONVERT = 3,
811 NI_PFI_OUTPUT_G_SRC1 = 4,
812 NI_PFI_OUTPUT_G_GATE1 = 5,
813 NI_PFI_OUTPUT_AO_UPDATE_N = 6,
814 NI_PFI_OUTPUT_AO_START1 = 7,
815 NI_PFI_OUTPUT_AI_START_PULSE = 8,
816 NI_PFI_OUTPUT_G_SRC0 = 9,
817 NI_PFI_OUTPUT_G_GATE0 = 10,
818 NI_PFI_OUTPUT_EXT_STROBE = 11,
819 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
820 NI_PFI_OUTPUT_GOUT0 = 13,
821 NI_PFI_OUTPUT_GOUT1 = 14,
822 NI_PFI_OUTPUT_FREQ_OUT = 15,
823 NI_PFI_OUTPUT_PFI_DO = 16,
824 NI_PFI_OUTPUT_I_ATRIG = 17,
825 NI_PFI_OUTPUT_RTSI0 = 18,
826 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
827 NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
828 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
829 NI_PFI_OUTPUT_CDI_SAMPLE = 29,
830 NI_PFI_OUTPUT_CDO_UPDATE = 30
832 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
834 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
837 /* Signals which can be routed to output on a NI PFI pin on a 660x board
838 with INSN_CONFIG_SET_ROUTING. The numbers assigned are
839 not arbitrary, they correspond to the bits required
840 to program the board. Lines 0 to 7 can only be set to
841 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to
842 NI_660X_PFI_OUTPUT_COUNTER. */
843 enum ni_660x_pfi_routing {
844 NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
845 NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */
848 /* NI External Trigger lines. These values are not arbitrary, but are related
849 * to the bits required to program the board (offset by 1 for historical
851 static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
853 return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
855 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
857 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
860 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
861 enum comedi_counter_status_flags {
862 COMEDI_COUNTER_ARMED = 0x1,
863 COMEDI_COUNTER_COUNTING = 0x2,
864 COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
867 /* Clock sources for CDIO subdevice on NI m-series boards. Used as the
868 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
869 * with CR_INVERT to change polarity. */
870 enum ni_m_series_cdio_scan_begin_src {
871 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
872 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
873 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
874 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
875 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
876 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
877 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
878 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
879 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
880 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
882 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
884 return NI_USUAL_PFI_SELECT(pfi_channel);
886 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
888 return NI_USUAL_RTSI_SELECT(rtsi_channel);
891 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
892 * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to
893 * change polarity. */
894 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
896 return NI_USUAL_PFI_SELECT(pfi_channel);
898 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
900 return NI_USUAL_RTSI_SELECT(rtsi_channel);
903 /* Bits for setting a clock source with
904 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
905 enum ni_freq_out_clock_source_bits {
906 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
907 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */
910 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
911 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
912 enum amplc_dio_clock_source {
913 AMPLC_DIO_CLK_CLKN, /* per channel external clock
914 input/output pin (pin is only an
915 input when clock source set to this
916 value, otherwise it is an output) */
917 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */
918 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */
919 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */
920 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */
921 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */
922 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel
923 (for channel 0, preceding counter
924 channel is channel 2 on preceding
925 counter subdevice, for first counter
926 subdevice, preceding counter
927 subdevice is the last counter
929 AMPLC_DIO_CLK_EXT, /* per chip external input pin */
930 /* the following are "enhanced" clock sources for PCIe models */
931 AMPLC_DIO_CLK_VCC, /* clock input HIGH */
932 AMPLC_DIO_CLK_GND, /* clock input LOW */
933 AMPLC_DIO_CLK_PAT_PRESENT, /* "pattern present" signal */
934 AMPLC_DIO_CLK_20MHZ /* 20 MHz internal clock */
937 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
938 * timer subdevice on some Amplicon DIO PCIe boards (amplc_dio200 driver). */
939 enum amplc_dio_ts_clock_src {
940 AMPLC_DIO_TS_CLK_1GHZ, /* 1 ns period with 20 ns granularity */
941 AMPLC_DIO_TS_CLK_1MHZ, /* 1 us period */
942 AMPLC_DIO_TS_CLK_1KHZ /* 1 ms period */
945 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
946 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
947 enum amplc_dio_gate_source {
948 AMPLC_DIO_GAT_VCC, /* internal high logic level */
949 AMPLC_DIO_GAT_GND, /* internal low logic level */
950 AMPLC_DIO_GAT_GATN, /* per channel external gate input */
951 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel
952 minus 2 (for channels 0 or 1,
953 channel minus 2 is channel 1 or 2 on
954 the preceding counter subdevice, for
955 the first counter subdevice the
956 preceding counter subdevice is the
957 last counter subdevice) */
958 AMPLC_DIO_GAT_RESERVED4,
959 AMPLC_DIO_GAT_RESERVED5,
960 AMPLC_DIO_GAT_RESERVED6,
961 AMPLC_DIO_GAT_RESERVED7,
962 /* the following are "enhanced" gate sources for PCIe models */
963 AMPLC_DIO_GAT_NGATN = 6, /* negated per channel gate input */
964 AMPLC_DIO_GAT_OUTNM2, /* non-negated output of counter
966 AMPLC_DIO_GAT_PAT_PRESENT, /* "pattern present" signal */
967 AMPLC_DIO_GAT_PAT_OCCURRED, /* "pattern occurred" latched */
968 AMPLC_DIO_GAT_PAT_GONE, /* "pattern gone away" latched */
969 AMPLC_DIO_GAT_NPAT_PRESENT, /* negated "pattern present" */
970 AMPLC_DIO_GAT_NPAT_OCCURRED, /* negated "pattern occurred" */
971 AMPLC_DIO_GAT_NPAT_GONE /* negated "pattern gone away" */
974 #endif /* _COMEDI_H */